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Funding for the research activities carried out at IMSE-CNM comes primarily from the participation in competitive tender processes. The research is then conducted out via agreements, projects and contracts with national and international public organizations and private companies and organizations.


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TOGETHER
Towards Trusted Low-Power Things: Devices, Circuits and Architectures
PI: Francisco V. Fernández Fernández / Rafael Castro López
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Type: Research project
Reference: TEC2016-75151-C3-3-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2019
Funding: 240.911,00 €
Abstract: To bridge the gap between the physical and digital worlds, any type of product would need to integrate networked electronic components and systems, built on micro/nanotechnologies, in what has been called "Internet of Things" (IoT). To fulfill the IoT vision, many technology enablers are required, with trusted (i.e., reliable and secure) as well as low-power ICs and components, among others, playing a pivotal role. All these enablers must be properly handled with a multidomain approach -covering device, circuit and architectural levels- in a context where technology scaling has slowed down. Thus, at technology level, innovations in materials and device structures will be required and, next to this, low-power robust circuits and alternative architectures will have to be implemented. Consequently, the experience of researchers with complementary expertise must be properly combined under a collaborative framework. Following these guidelines, device reliability engineers (UAB) and analog and digital circuit designers (IMSE and UPC) will work together in this project on the design of low-power, variability-resilient nanoelectronic circuits and systems, by using a multilevel approach and taking into account IoT challenges.
To achieve this general objective, several lines of work will be followed. Since circuit and system design for IoT relies upon a deep knowledge of phenomena at device level, a detailed statistical and multiscale characterization of the variability in advanced CMOS devices will be done in all regimes of operation, for the development of variability-aware compact models. Emerging devices (i.e., memristors and graphene-based devices) will be also considered to evaluate their suitability as building components in alternative circuits and architectures. At circuit and system levels, low-power and variability-resilient design strategies and methodologies will be developed. Variability will be tackled from two perspectives: palliation and exploitation. From a palliative perspective, adequate design methodologies will be created, able to consider and reduce variability across many hierarchical levels in a complex AMS/RF system. Also, the use of Body Bias modulation for variability mitigation in RF and digital circuits in FDSOI technologies will be analyzed. From the exploitation perspective, unreliability aspects in CMOS and memristive devices will be explored for the implementation of cryptographic primitives. Energy-efficient hierarchical design methodologies will be implemented to reduce power consumption in AMS/RF circuits and ultra-low voltage AMS/RF and digital circuits will be designed. Non-conventional strategies for computing systems and non-von Neumann computing architectures will be studied too. Finally, the adoption of emerging technologies for alternative computing architectures (combining memristors and FETs) as well as neuromorphic architectures will be addressed. The innovations in devices, design techniques, extremely low-power and reliable circuits and architectures will enable competitive advantages in numerous IoT applications and markets, supporting the relevance of the proposed research from the societal, industrial and economical points of view. This fact, together with the experience of the proposing partners, foresees publications and technology transfer of the results.

IPANEMA
Integrated Pattern-Adaptive optical NEurostimulator with Multi-site recording Array
PI: Manuel Delgado Restituto
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Type: Research project
Reference: TEC2016-80923-P
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2019
Funding: 145.200,00 €
Abstract: This Project aims to provide enabling microelectronic technologies for the integration and miniaturization of a smart neural stimulation system based on optogenetics, which serves as experimental vehicle for the development of new procedures in neurobiology and, ultimately, for the implementation of new neural prosthesis, more focus and secure than those currently available, for the treatment of different pathologies of the nervous system (severe sensory deficits, brain diseases, chronic pain, and others).
Within this general scenario, our objective will be to provide the basis towards a reliable and efficient closed-loop mechanism which, based on the electrical activity recorded from the genetically encoded cells, is able to provide an efficient and non-harmful actuation by optic means. This real-time feedback procedure will support the adaptability of the system to the plasticity of the neural tissue and, thereby, it will open up doors for the implementation of robust, long lifetime neural prosthesis whose operation self-adjusts to the patient's progress.
The system to be developed will be scalable and reconfigurable with the number of recording electrodes and optical stimulation sources (it might be regarded as a MIMO -multi-input, multi-output- control system) and will allow the activation of LEOs incorporated into the probe or, alternatively, the triggering of any convenient external light source by means of a custom data pathway. In the former case, LEOs may be placed in direct contact with the tissue (by using micro-LEOs integrated in the probe) or employ optical fibers for guiding photostimulation. For the sake of easy handling, data transfer to/from the complete recording/stimulation system will employ wireless techniques.
According to this concept, the system implementation will encompass the fabrication of two Application-Specific Integrated Circuits (ASICs) together with so me commercial components (essentially, a microcontroller for supervising the stimulation feedback loop and an ultra-low power wireless transceiver). One of the ASICs, denoted as stimulation ASIC, will implement the stimulation circuitry, whereas, the other ASIC, denoted as acquisition ASIC, will include circuits for recording, processing and communications, as well as a power management unit!. A multi-chip solution is preferred over a single monolithic integration in order to increase the reliability of the system, reduce the fabrication risks, and improve the performance of the neural recording channels which, otherwise, it would become adversely affected by the commutations of the stimulation circuitry.
The ASICs will be fabricated in a low-cost O.18um CMOS technology and tested either individually, or connected one to another in the final system platform. Their characterizations will consist in mixed-signal and optical tests in the premises of our laboratories. Additionally, we will lay plans on the validations of the prototypes with in vitro and in vivo measurements, to be carried out in Bioengineering Institutes with which the applicant group holds collaboration agreements.

INTERVALO
Integration and validation in laboratory of countermeasures against side-channel attacks in microelectronic cryptocircuits
PI: Antonio J. Acosta Jiménez / Carlos J. Jiménez Fernández
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Type: Research project
Reference: TEC2016-80549-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2019
Funding: 104.544,00 €
Abstract: Security and privacy in communication are certainly one major right for institutions and people in general, being those factors of strategic interest in our society. Nowadays there are many electronic devices in which security is a must and most of these systems use cryptographic techniques to achieve confidentiality and inviolability in private data management. Many secure electronic systems include cryptographic devices implementing mathematical algorithms that are directed to hide sensitive information. However, due to their specific implementation as a circuit, side channel attacks can be successfully performed and information extracted. Therefore, paying special attention to the physic implementation of cryptographic devices is a crucial point to minimize the leak of information under side channel attacks. Hence, hardware implementations in the case of cryptographic algorithms require an adequate and correct realization of algorithms from the functional point of view as much as the inclusion of robust security mechanisms in order to diminish vulnerability. Most of portable security applications (RFID keys, USB memories, smart cards, etc.) use symmetric encryption that has to be integrated in very low power hardware (lightweight cryptography) what has to be required in the new environments resulting of the Internet of things. This Project aims to obtain a set of countermeasures libraries to be included in high performance hardware implementations (ASICs) in CMOS nanometer technology. The focus will be to increase the security of portable systems against side attacks facing secure (de)ciphering problems. Countermeasures will be proposed at a variety of abstraction levels, going from architecture to layout. These will be ready to be used in any stream or block cipher for any kind of application. Different strategies of passive attacks based on power analysis (DPA), electromagnetic emissions (DEMA) and active non-invasive attacks based on fault injection (clock signal, power supply, temperature) and invasive (light source or pulsed laser) will be considered. Hardware implementations (ASIC) will be developed, including area, frequency and power consumption optimization as well as side channel attacks security improvement. The main concern will be to optimize the systems performance accomplishing security increases with no penalties for this performance. To this aim, vulnerability measures, both experimental and simulated will be very important to qualify the countermeasures and the designed hardware.
The three primary targets of the Project are:
To develop automatic experimental mechanisms to analyze the vulnerability of hardware implementations of ciphering circuits and its application on real implementations.
To propose, design and test hardware countermeasures of different categories to diminish vulnerability in crypto circuits.
To design, integrate and test an ASIC with ciphers including the proposed countermeasures and include the ASIC in a IoT system to evaluate the improvements in security in real systems.

MINES-SVM
Microelectronics for Space Instrumentation: MEDA Wind-Sensor ASIC
PI: Servando Espejo Meana
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Type: Research project
Reference: ESP2016-79612-C3-3-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2018
Funding: 266.200,00 €
Abstract: MINES-SVM, as a sub-project within the coordinated project M3EC, has specific objectives related to the development of the mixed-signal ASIC required for the MEDA wind sensor, which will be included in NASA's Mars2020 mission. An operative prototype of this ASIC is currently (April 2016) available, as a result of previous projects and contracts. It is in its final functional verification stage, and will probably satisfy the requirements and specs of the instrument. The technology employed for the design and manufacturing of the ASIC is a standard 0.35 microns CMOS process. This technology had been previously characterized for space use by the research team, also in the framework of previous projects.
The MEDA ASIC performs the functions of analog front-end for temperature sensors based on platinum resistors and thermopiles, and sigma-delta thermal control loops and power measurements. This includes signal conditioning and analog to digital conversion, as well as configuration and data communications through a standard digital interface. The design employs Radiation Hardening By Design (RHBD) techniques, including functional redundancy and specific layout techniques.
Within this framework, the first objective of MINES-SVM is to finalize the test and validation for space use of this ASIC. This includes the completion of the electrical functional tests, as well as the verification of the radiation hardness and the behavior at low and high temperatures through specific additional tests.
The ASIC must be manufactured again in order to achieve a minimum number of samples, as required by the formal screening associated with its use in space. Minor refinements could be introduced in the design in this new manufacturing lot, depending on the results of the functional tests and the radiation hardness and low-temperature tests. In any case, the final version of the ASIC, with its final packaging, will need to be qualified for space use following formal processes by an external agent. This will require the design of several test systems for the functional/electrical validation tests, and for those tests related to radiation tolerance (both TID and SEEs), low-temperature behaviour, and life-tests of the ASIC. The second objective of MINES-SVM is the integration of the ASIC in the engineering and flight modules of the wind sensor, and the calibration of the overall measuring system. The integration of the wind sensor within the rover, considering possible effects on the measuring function, will also be supported.
The main result of MINES-SVM will be the availability of this space-qualified ASIC. This will represent a clear competitive advantage for future missions and similar designs.
As a collateral result, this subproject will help to consolidate the space-microelectronics design capability at a national level. The technologies involved have been identified as critical at the European level, including microelectronics, discrete-components electronics, advanced packaging materials, and the mitigation of the radiation effects on electronic systems. In summary, the background objective is to generate, at a national level, a complete set of mature and high performance resources for the development of space instruments demanded by the national or international scientific community, or by other sectors traditionally linked to the space sector like those of Security and Defense.

ASIC-SIS
ASIC for compacts solar irradiation sensor
PI: Diego Vázquez García de la Vega
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Type: Research project
Reference: ESP2016-80320-C2-2-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2018
Funding: 169.400,00 €
Abstract: This Project (ASIC-SIS) represents a very important technology activity for the development of a Mixed-Signal ASIC for special applications in the Mars surface. This activity started years ago (2008) in the context of the MetNet mission and give as a result the creation of a research group in the IMSE-CNM/University of Seville specialized in this kind of designs. Thanks to these efforts, it was possible to provide solutions to the needs of signal conditioning and compaction of wind sensors for the MEDA station.
It should be mentioned that the development of Mixed-Signal ASICs for space use has been identified in H200 as a strategic line for Europe and the not dependence. This project follows this line intending the development of an ASIC to support future and even more compact Solar Irradiation Sensors (SIS) that are being recursively used for surface mission in Mars (SIS are present in 4 missions: MetNet, EXM'16, EXM'18 y Mars2020); it demonstrates the large interest of this kind of systems. So, the project aims the maximum compaction as possible of the SIS but also providing added values of reliability and re-usability as well as incrementing its scientific potential to become a reference sensor at international level for future missions.
Namely, the global ASIC-SIS objective is the development of a Mixed-Signal CMOS ASIC for the advanced Solar Irradiation Sensor (SIS). It contemplates all the required phases or steps: definition of specifications and/or requirements, synthesis at different levels (architectural, circuits blocks, devices, etc.), fabrication, validation, qualification, etc., AII the work concerning the design of the ASIC will be carried out by the US but in collaboration with INTA, who will give the necessary support in the specifications and requirements during the different validation steps. Finally, the US will give to INTA the support to perform the validations of a compact SIS prototype including the ASIC.

COGNET
Event-based cognitive vision system. Extension to audio with sensory fusion
PI: Teresa Serrano Gotarredona
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Type: Research project
Reference: TEC2015-63884-C2-1-P
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2016
End date: 31/12/2019
Funding: 197.956,00 €
Abstract: The global goal of the COGNET project is to advance in the theoretical and technological development of event-based sensing and processing systems and demonstrate its potential to solve practical problems in a more efficient way than conventional technologies do. In particular, in the COGNET project we will address event-based vision and audition sensing, event-based vision and audition recognition systems and their off-line and on-line training, and the fusion of visual and auditive information to perform multisensory recognition tasks in real time. In COGNET, we are trying to demonstrate the superior performance of the event-based technology in two practical problems. The first one is binocular-based high-speed vehicle obstacle detection with few milliseconds response time, and the second one is visually guided speech recognition in a noisy environment.

ICAVEATS
Integrated components and architectures for embedded vision in transportation and security applications
PI: Ricardo Carmona Galán
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Type: Research project
Reference: TEC2015-66878-C3-1-R
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2016
End date: 31/12/2018
Funding: 197.714,00 €
Abstract: This project aims to the capitalization of the acquired know-how by developing a library of hardware components and architectures. They have to be compatible with OpenVX descriptions and aimed to reduce power consumption of mainly-software implementations. We will include low and medium-level processing blocks, new sensor abilities, like photon counting and time-of-flight estimation, and aspects more related to the system level, like energy management and interfacing with other signal processing chips. We will explore technological alternatives that may provide a more efficient implementation of OpenVX functions. These modifications will be transparent from the point of view of the application developer and the designer of computer vision algorithms.
In order to demonstrate the validity of the approach we will build a vision system on-a-chip for intelligent transportation and security applications. We will develop demonstrators to properly expose the potential of this approach to embedded vision.

n-PATETIC
New paradigms for testing mixed-signal integrated circuits
PI: Adoración Rueda Rueda
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Type: Research project
Reference: TEC2015-68448-R
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2016
End date: 31/12/2018
Funding: 196.020,00 €
Abstract: This project aims to develop low-cost, reliable, and verifiable test solutions for analog, mixed-signal, and radio frequency circuits (AMARF). Capitalizing the skill of the designer on the design process of such circuits and on the limitations of the test techniques developed to date, we intend to seek new test paradigms that allow safely abandon the traditional methods of functional test. In this way, it could contribute to decrease the test cost that represents today about half the cost of manufacturing a complex circuit. We will focus on functional alternative methods and indirect test methods. The first will measure functional parameters but will be less expensive than standard techniques, thus relaxing the requirements of the test equipments. The later would be aimed at the detection of defects, and will be based on the assumption of considering that the circuit is correct by construction and what is sought with the test are indications of possible degradation. This can be a paradigm shift of very important consequences in current electronic products; if the project gives the expected results, this methodology could have a similar impact on the AMS-RF circuits that it had the introduction of the Boundary-Scan in digital circuits.
Since it is extremely complex to reliably validate a technique test before mass production of circuits, also in this project we intend lo address the problem of lest verification, developing behavioral models aimed at facilitating the verification quickly and efficiently.
In this context, the project aims to address three general objectives:
1. Capitalize information on the design process and verification of AMS-RF circuits, creating documentation and/or modeling allowing the development of new test paradigms that represent significant improvements lo the quality/test tradeoff. We want to explore how we can formalize and systematize what we know of the circuit to develop robust and reliable test.
2. Develop reliable and verifiable solutions for the test of these circuits. The shift from a paradigm of functional test, in which the performance of the circuits are measured by standard processes for comparison with your specifications, to a paradigm of indirect test in which the decision to accept or reject a circuit is made based on deviations of so me firms, contains a great potential for significant cost reduction.
3. Explore and develop systematic methodologies for functional low-cost test not only for validating products in the post-production phase, but also with the purpose to their application in 81ST schemes for online test.
As vehicles for proof of concept we will use CMOS prototypes already made by the applicant team, namely, high performance Analog Digital converter (ADC) (> 12bits and up to 1 OOMS / s) and building blocks of front-ends in RF wireless transceivers. Some of these designs have to be adapted to incorporate additional circuitry to facilitate access to certain signals as well as for the implementation of the DfT or BIST techniques derived from the new developed test paradigms.

ID-EO
Design of crypto-biometric hardware for video encryption and authentication
PI: Iluminada Baturone Castillo / Piedad Brox Jiménez web
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Type: Research project
Reference: TEC2014-57971-R
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2015
End date: 31/12/2017
Funding: 187.550,00 €
Abstract: As more and more individuals and devices (Iaptops, tablets, smartphones, cameras, etc.) are interconnected through public networks, it is essential to ensure that the information exchanged (multimedia many times) really comes from individuals and devices that must generate, store, or process it. The generation of cryptographic keys from the intrinsic nature of devices or individuals not only ensures their digital identity when they access or provide information but also allow the encryption and authentication of such information, bonding it to the counterfeit-resistant identities.
Since a cryptographic system is as secure as its secret key, there is a growing interest in increasing the security of cryptographic key storage by using specific hardware, rather than just having software solutions. This is the reason why digital hardware (crypto-modules) will be designed in ID-EO project to generate the keys when needed instead of storing them, always involving the authentic device or individual designated to generate them. Moreover, they will be able to generate truly random numbers and identifíers. The modules will offer diversification, because they can generate different keys from the same identity, and revocability, because if one key is compromised, a new one can be generated at a new registration process.
The design of crypto-modules that could provide such functionality would find a very wide range of applications. In particular, a natural application domain is embedded vision systems that would become 'chains of trust', ensuring the authenticity of the system ítself and the confidentiality, privacy and integrity of the video captured and processed by the system. Nowadays, the proliferation of communications and web technologies has created an environment in which the security of the images and videos that are transmitted or stored in open channels is questioned. This is the reason why trust embedded vision systems will be designed in the ID-EO project, capable of real-time video selective encryption and authentication with constrained resources and low-power consumption.

CESAR
Secure microelectronic circuits against side-channel attacks
PI: Antonio J. Acosta Jiménez web
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Type: Research project
Reference: TEC2013-45523-R
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2014
End date: 31/12/2016
Funding: 144.474,00 €
Abstract: The aim of this project is the design and implementation of high-performance hardware implementations (ASICs) through nanometric CMOS technologies to fulfill the security requirements of (de)ciphering in portable systems. To achieve low power and high performance capabilities, stream ciphers will be used for securely encoding/decoding the information, owing to the fact that they can implement the necessary operations at an acceptable speed and with few resources without compromising on security (lightweight cryptography).
Weaknesses will be analysed and security measured for stream ciphers like Trivium, Grain or Mickey, since they are the more interesting ones for hardware implementations. Different power consumption and timing based passive attacks will be considered (DPA) as well as fault-injection based active attacks (clock signals, power supply, temperature) and combinations of both of them. Countermeasures will be proposed at any design level (architecture, circuit, layout). Optimized hardware solutions will be implemented in terms of design (area, speed, power consumption) in addition to sideattacks security. On account of considering different and key factors altogether it will be possible to optimize systems performance whilst increasing security.
Three are the main targets of the Project:
- To explore the weaknesses of stream ciphers against active and passive side-channel attacks through sistematic methodologies so as to obtain an efficient metric of the security.
- To develop architectural, circuit and layout level countermeasures for these attacks when appear isolated or, moreover, applied together.
- To design, implement and test nanometric CMOS ASIC demonstrators covering every characteristic of secure encoding/decoding and establish a metric for these figures.

KIT-LTCC
Design Kit Development in LTCC ceramic technology: modeling, simulation and fabrication of components and circuits, and design methodology
PI: Elisenda Roca Moreno
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Type: Research project
Reference: RTC-2014-2426-7
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/09/2014
End date: 31/08/2016
Funding: 47.205,44 €
Abstract: The main objective of this project is the development of a design methodology for electronic systems in an LTCC technology using a library of 3D components and basic blocks that can be distributed as a Process Design Kit (PDK) to potential users of the technology. The project is funded by the "Programa Estatal de Investigación, Desarrollo e Innovación Orientada a los Retos de la Sociedad", within the framework of the "Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016". Participants are FRANCISCO ALBERO S.A.U., Radiofrequency Group of the University of Barcelona (FBG-UB) and the Instituto de Microelectrónica de Sevilla.


NACLUDE
Nano-architectures for logic computing using emergent devices
PI: María J. Avedillo de Juan
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Type: Research project
Reference: TEC2013-40670-P
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2014
End date: 31/12/2016
Funding: 88.935,00 €
Abstract: Nowadays, a rising research activity in the development of technologies that increase processing capability beyond what CMOS technology can provide is observed. This project is intended to work in that direction, contributing to the development of integrated circuits using devices which are now considered potential candidates to complement/replace CMOS technology. Our main goal is to increase our experience in the realization of circuits based on architectures and/or unconventional logic models which these emerging devices make possible. In particular, the project aims to continue the development of nano-architectures for logical computing, which is the goal of an running projects of the National R&D&I Plan in which resonant tunneling diodes are used. This new project uses tunneling transistors and memristors (resistors with memory) for the implementation of these nano-architectures. Hybrid CMOS /memristor technologies have potential to provide designs with a high density of devices per unit of area and very competitive delay/energy trade-offs and its applications are huge. In the field of logic computation, memristors allow efficient non-boolean alternatives to realize logic functions. We intend to use its continuous resistance to implement threshold logic, which will increase the functionality of previously proposed architectures using two sets of nanowires with memristors which operate as switches at the intersections.
Tunnel transistors are one of the most attractive inverse subthreshold slope (SS) devices. A reduced SS implies a reduction of the threshold voltage without excessively increasing leakage current, allowing extremely low bias voltages and very energy efficient circuit realizations. In this project we explore its application to the realization of nano-level pipelines gates inspired by those that we have developed with RTDs and which implementation with MOSFETs transistors have limitations due to excessive power consumption.
The specific objectives of the project are: 1) Development of efficient regular structures for hybrid CMOS/memristor logic circuits and 2) Development of competitive nano-architectures for logic computation based on tunnel transistors.

MARAGDA
Multilevel approach to the reliability-aware design of analog and digital integrated circuits
PI: Francisco V. Fernández Fernández web
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Type: Research project
Reference: TEC2013-45638-C3-3-R
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2014
End date: 31/12/2016
Funding: 268.257,00 €
Abstract: The MARAGDA project is proposed in a context where the manufacturing variability challenge in nanoscale CMOS technologies imposes an important paradigm change in all the aspects related to the IC design.
The fabrication processes introduce random atomic-level inhomogeneities, which are observed in the form of device-to-device shifts in the parameters that describe their behavior and performance. In addition, the high electric fields and temperatures in the device, resulting from the aggressive scaling, can trigger aging mechanisms (whose origin should be also found at the nanoscale), which introduce a time dependent drift in the device electrical properties as well. Therefore, the combination of variability and aging leads to a dramatic random and time-dependent variability of the device electrical characteristics, so that nominally identical devices will show statistically distributed performances that change with time. This device- level time-dependent uncertainty will be transferred to circuits and systems, impacting their yield, performance and reliability under conventional design rules.
To fight against the time-dependent variability, as dictated by the ITRS, a multilevel approach has to be adopted, going from the fabrication up to the applications, in which variability and aging effects are propagated and evaluated, through all the stages of the IC manufacturing process.
MARAGDA project adopts such multilevel approach, for the design of high-performance and reliable analog, mixed-signal, RF (AMS/RF) and digital circuits, by coordinating three research teams with complementary expertise in the fields of variability and aging in nanoelectronics: electrical characterization and reliability of devices (UAB), design methodologies for AMS/RF circuits (IMSE-US) and design of AMS/RF (IMSE-US and UPC) and digital (UPC) circuits.
Taking advantage of the groups background, the IC design will be addressed by using a multilevel approach, from the nanoscale (where variability and aging have their origin) to circuit/system level (where their effects will be observed), accounting for the interactions between all the abstraction levels. For ultrascaled devices, variability and aging will be (statistically) studied, using standard (wafer level) and high resolution (nanoscale) characterization techniques, with the aim of proposing device aging models which can be implemented in circuit simulators. These models, together with an efficient reliability-aware circuit simulation methodology (to be developed in the project), will allow the translation of device-level time-dependent variability into statistical circuit performance fluctuation and yield and reliability drop.
The resulting simulation methodology will allow the development of new reliability-aware design methodologies, which tackle variability before (preventive techniques) and/or after the circuit fabrication (reactive strategies). New architectural paradigms that explore the benefits that emerging devices could offer to deal with (time-dependent) variability will be also considered. The project includes complete experimental deliverables in all the levels above to validate the investigated concepts and principles.

MIXCELL
Integrated MicroSystems for Cell-Culture Assays
PI: Alberto Yúfera García
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Type: Research project
Reference: TEC2013-46242-C3-1-P
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2014
End date: 31/12/2016
Funding: 108.900,00 €
Abstract: This project will be focused on cell-culture monitoring by using impedance and/or capacity measurements. It means a radical change in the conception of the work on cell-culture laboratories, making it possible to supervise an experiment in real-time and remotely during days and, therefore, to increase the measurement sensitivity in many cell-processes like motility and cytotoxicity. The present approach pursues the implementation of integrated CMOS systems for measuring impedance and capacity in cell-cultures in real-time, contributing not only with techniques and strategies but also to the design of high performance integrated circuits: energetic autonomy (LP, LV), capacity for wireless communication, accuracy and bandwidth. The goal of this proposal is to develop new useful analogical front-ends for bio-impedance measurements. In parallel, we will address the problems of characterizing and modeling the employed bio-sensors, and their incorporation into the flow design of the measurement integrated circuits. Our purpose is to evolve towards the concept of on-chip, autonomous systems or laboratories (LoC). The main and final objective, based on the obtained results, will be to achieve a system capable of carrying out the characterization of a cell-culture, establishing a biometric procedure allowing us the identification of different cellular lines and types, characterizing experiments of motility in lines of cancer cells, and evaluating the possibilities of sensing for measuring stem cell proliferation, giving solutions based on electrical resistance and capacity. Our concluding results will be validated with the experimental standards used in biomedical laboratories.
The aims to develop in this project are:
1) Generate techniques and strategies for measuring bio-impedances based on analog signal processing.
2) Design of analog and mixed-signal CMOS integrated systems.
3) Verification of the existing models for the interface sensor-cells and development of new alternatives. Application to simulation, cellular-biometry and microscopy.
4) Experimentation in biomedical labs for monitoring and characterization of cell-cultures, proliferation assays, cancer-cell motility and stem cell proliferation.

SENIAC
Security in interconnected devices by injection of authentication and ciphering algorithms
PI: Iluminada Baturone Castillo web
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Type: Research project
Reference: RTC-2014-2932-8
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/10/2014
End date: 30/09/2016
Funding: 77.809,64 €
Abstract: The main objective of SENIAC project is to achieve that interconnected devices form a chain-of-trust, providing information confidentiality and integrity as well as authentication and non revocability, through the secure injection of ciphering and authentication methods. A highly secure software platform will be developed that, once injected in the devices via firmware reprogramming, will provide cryptographic and physical authentication techniques, avoiding counterfeit of the devices in a network.

SMMEI
Space Microelectronics for Mars Environmental Instrumentation
PI: Servando Espejo Meana
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Type: Research project
Reference: ESP2014-54256-C
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2015
End date: 31/12/2016
Funding: 24.200,00 €
Abstract: SMMEI, as a subproject within the coordinated project M3EC, has two central specific objectives. The first one is to contribute to the development of the microelectronics required for the wind sensor included in the space instrument MEDA, to be developed in the framework of the coordinated project for NASA's Mars 2020 mission. The research team in charge of the subproject, with previous experience in the design and test of mixed-signal ASICs for space use, will support the specification, manufacturing process selection (foundry), design, validation, qualification, and integration of the ASIC into the final instrument. The second objective consists in the design and qualification of a mlxed-signal ASIC, in this case for the electronics of an evolved version of the solar irradiance sensor SIS developed by the Payloads Electronic Laboratory of INTA, aimed to the payIoad of the EXOMARS 2018 mission.

INFRAESTRUCTURA Y EQUIPAMIENTO CIENTÍFICO-TÉCNICO
Equipamiento del servicio científico-técnico de caracteriazación de circuitos integrados de aplicaciones de radiofrecuencia, aeroespaciales y de procesado de señal del IMSE
PI: Santiago Sánchez Solano
[+]
Type: Facilities
Reference: CSIC13-1E-1826
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2013
End date: 31/12/2015
Funding: 113.031,52 €
Abstract: Tomando como base el equipamiento científico disponible en el Instituto de Microelectrónica de Sevilla, así como la experiencia del personal científico y técnico que lo integra, este proyecto pretende potenciar la participación de los grupos de I+D y PYMEs de su área de especialización en el programa Horizonte 2020, mediante la creación de un servicio que ofrezca sus facilidades de caracterización y test de circuitos integrados a distintos organismos públicos de investigación y empresas de base tecnológica. De especial interés resulta el previsible uso de dicho servicio por empresas del entorno geográfico más inmediato, como las implantadas en el Parque Científico Tecnológico Cartuja y el cercano Parque Aeroespacial Aerópolis. Asimismo, la integración del servicio en la Red de Servicios Científico-Técnicos del CSIC permitirá abrir la oferta a cualquier institución o empresa de ámbito nacional e internacional.
El servicio previsto integrará distintas facilidades para la caracterización de dispositivos semiconductores, circuitos analógico-digitales, circuitos optoelectrónicos y de radiofrecuencia, así como para el estudio de compatibilidad electromagnética y la realización de test de eventos simples mediante láser pulsado.
Para ofrecer un servicio de calidad y adecuado al estado del arte se requieren las inversiones que se detallan en la memoria adjunta con objeto de completar el equipamiento y la dotación de personal técnico ya existentes en el Instituto.

BIOSENSE
Bioinspired event-based system for sensory fusion and neurocortical processing. High-speed low-cost applications in robotics and automotion
PI: Teresa Serrano Gotarredona
[+]
Type: Research project
Reference: TEC2012-37868-C04-01
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2013
End date: 31/12/2015
Funding: 164.385 €
Abstract: AER (Adress-Event-Representation) is a bioinspired information sensing and processing technique based on information codification and transmission as a continuous flow of electrical pulses (events), in a similar way as neuro-biological systems send and process nervous impulses. The frame concept that appears in classical vision processing, and that biological systems completely lack, also disappears in AER systems. In previous national and international projects, the participants have demostrated the great potential of AER technology to sense and process high-speed vision, and to actuate on the perception and actuating subsystems in the neuro-robotics field. The participants have developed microchips for vision sensing and processing, that have been embedded in hybrid processing systems with FPGAs, and have been proved in an incipient way in the automotive and robotics industrial fields.
The BIOSENSE project intends to build a bioinspired sensing-processing-actuating robotic platform based on modular AER technology. In that platform, the visual-motor coordination among several cameras for 3D vision, auditive cochleas and motor actuation on a high number of motors (more than 10) should be virtually instantaneous, with delays in the order of mili seconds or even lower. This platform will allow us to face problems of auditive and 3D visual sensing, sensory fusion, processing and decision taking, as well as motor actuation, still unsolved in the field of survaillance and robotics.
The BIOSENSE platform will include multisensorial AER information: a 3D vision system based on the interconnection of two and more AER retinae, AER audition, AER tactile sensing and propioceptive sensing. The sensor fusion in the event domain will be studied as well as its integration with sensing information coming from commercial automotion sensors. New visual retina and auditive cochlea sensing microchips and new neurocortical event (nervous impulses) processors using 3D high-integration CMOS technology will be developed. This microchips will be combined with last-generation FPGAs to maximize system reconfigurability and adaptability, and will be integrated in demonstrators for automotive and robotics.
The sensorial information will be processed by a system composed by the interconnection of programmable AER processing modules with reconfigurable topology. The system will emulate biological brain cortex hierarchical structure.
The BIOSENSE platform will include an antropomorph bimanual robotic module, with cognitive self-learning of manipulation tasks, that will be operated through AER domain motor control. Thus, maximizing the mechanical speed response as well as allowing the coordinated multi-motor control.
In the BIOSENSE project, we will also study the learning problem in the event domain using STDP (spike time dependent plasticity) techniques, coming from neuroscience, not only to learn the synaptic weights in the brain cortex and for trajectory self-programming and learning, but also at the motor actuation control level.
The potential of the knowledge and technology developed in BIOSENSE will be demonstrated in two concrete applications where the speed requirements limit the success of classical frame-based processing systems. The first one is a system for supervision of driver behaviour inside a vehicle. The second one is a robot catching and manipulating high-speed moving objects.

MONDEGO
Single-chip vision system for networked and distributed vision applications
PI: Ricardo Carmona Galán web
[+]
Type: Research project
Reference: TEC2012-38921-C02-01
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2013
End date: 31/12/2015
Funding: 174.915 €
Abstract: The main goal of this project is building a hardware platform for the development of distributed, co-operative and collaborative, vision applications, with special emphasis in outdoor surveillance and monitoring with a limited infrastructure.

CB-DOC
Content management system with secure authentication by cripto-biometric techniques based on hardware
PI: Iluminada Baturone Castillo web
[+]
Type: Research project
Reference: IPT-2012-0695-390000
Funding Body: Ministerio de Economía y Competitividad
Start date: 17/07/2012
End date: 31/03/2015
Funding: 141.790 €
Abstract: The main objective of this project is to achieve that the components of a content management system (CMS) form a chain of trust thanks to the inclusion of hardware solutions besides software solutions. The consequences of an insecure CMS can be dramatic not only from a personal point of view, but also for the enterprises or corporations, beca use the lost of sensitive information carries out economic and/or legal problems.The project will develop a mixed software/hardware platform (referred to as CB-DOC) to manage contents and documents, which will be highly secure beca use it will apply cryptographic and biometric techniques from a hardware element (referred to as epadlock) that will be difficult to be cloned.

CLEPSYDRA
Towards a Closed-Loop Epileptogenic Prediction SYstem based on sub-Dural Recording Arrays
PI: Manuel Delgado Restituto web
[+]
Type: Research project
Reference: TEC2012-33634
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2013
End date: 31/12/2015
Funding: 294.489 €
Abstract: This Project aims to provide enabling technologies for the integration and miniaturization of biomimetic systems, which can be used for building neurocortical implants suitable for scientific (to allow new advances in neuroscience) and clinical (to provide neuroprosthesis for the treatment of neurological diseases) issues. Within this general scenario, our objective will be to provide the basis towards a reliable and efficient closed-loop epileptogenic prediction system with higher specificity and sensitivity than current therapeutic devices. This will be accomplished by the heterogeneous integration and 3D stacking of three different System-on-Chips (SoC); one for the acquisition and conditioning of neural activity, another to process the recorded information and extract only those parameters relevant to effective seizure prediction, and one final SoC for powering and communication purposes. Additionally, novel versatile setups for measuring the system under in vivo and in vitro conditions will be provided.
The seamless integration of all these functional blocks involves many exciting design challenges and, thereby, represents a fertile scenario for new ideas in the field of ultra-low power applications (needed to avoid tissue damages due to excessive heating) in a wide range of frequencies, from nearly DC up to the tens of MHz band. At low frequencies, in the mHz to kHz range, advances on the design of low-noise, low-power amplifiers for biopotential measurements, as well as on the design of band-pass filtering and converting stages will be pursued. In the MHz range, short-distance wireless data transfer/powering techniques based on inductive links will be proposed. This is done to avoid large size battery or percutaneous physical links that are prone to damage due to mismatch in material properties or scarring at the tissue interface. At intermediate frequencies, a sophisticated bio-signal processor involving tasks such as artifact removal, real-time spike sorting and classification, or multivariate seizure prediction will be targeted.
The SoCs will be fabricated in a low-cost 130nm CMOS technology and tested either individually, or connected one to another via stacked-die wire bonding techniques. Their characterizations will not only consist in mixed-signal tests in a conventional electronic laboratory, but also include in vitro and in vivo measurements.

INNPACTO 3D2
Intelligent Image Sensors in CMOS Technology with 3D Stacked Chips
PI: Ángel Rodríguez Vázquez web
[+]
Type: Research project
Reference: IPT-2011-1625-430000
Funding Body: Ministerio de Ciencia e Innovación
Start date: 01/01/2011
End date: 31/03/2015
Funding: 402.942,50 €
Abstract: This research deals with the incorporation of 3D visual capabilities, i.e. the generation of a depth map to the set of functionalities implemented in a smart CMOS image sensor. The techniques explored in this project are based in the estimation of the time-of-flight (ToF), both by properly clocked conventional integrating photodiodes, or by using CMOS-compatible single-photon avalanche diodes. Another objective is the incorporation of intelligent processing at chip level in order to enhance 3D information extraction.

FENIX-SDR
FlExible Nanometer CMOS Analog Integrated Circuits for the NeXt Generation of Software-Defined-Radio Mobile Terminals
PI: José M. de la Rosa Utrera web
[+]
Type: Research project
Reference: TEC2010-14825
Funding Body: Ministerio de Ciencia e Innovación
Start date: 01/01/2011
End date: 31/03/2015
Funding: 236.676 €
Abstract: The main objective of this project is the systematic design of flexible Radio-Frequency (RF), Analog and Mixed-Signal (AMS) circuits to be incorporated in Software-Defined-Radio (SDR)-based transceivers intended for future Cognitive-Radio (CR) applications. To this purpose, the project will focus on the design, implementation using nanometer CMOS technologies (45nm and beyond) and experimental characterization of flexible digitally-assisted RF/AMS front-ends as well as their supporting design methodologies. This ambitious objective goes beyond state-of-the-art multi-standard ICs-based on including adaptability capabilities to RF/AMS circuits.

PNEUMA
Plasticity in NEUral Memristive Architectures
PI: Bernabé Linares Barranco web
[+]
Type: Research project
Reference: PRI-PIMCHI-2011-0768
Funding Body: Ministerio de Ciencia e Innovación
Start date: 01/09/2011
End date: 01/03/2015
Funding: 89.000 €
Abstract: This project aspires to develop experimental platforms capable of perceiving, learning and adapting to stimuli by leveraging on the latest developments of five leading European institutions in neuroscience, nanotechnology, modeling and circuit design. The non-linear dynamics as well as the plasticity of the newly discovered memristor are shown to support Spike-based- and Spike-Timing-Dependent-Plasticity (STDP), making this extremely compact device an excellent candidate for realizing large-scale self-adaptive circuits; a step towards 'autonomous cognitive systems'. The intrinsic properties of real neurons and synapses as well as their organization in forming neural circuits will be exploited for optimizing CMOS-based neurons, memristive grids and the integration of the two into real time biophysically realistic neuromorphic systems. Finally, the platforms would be tested with conventional as well as abstract methods to evaluate the technology and its autonomous capacity.

SEIs
Hardware design for embedded systems in intelligent environments
PI: Santiago Sánchez Solano web
[+]
Type: Research project
Reference: TEC2011-24319
Funding Body: Ministerio de Ciencia e Innovación
Start date: 01/01/2012
End date: 30/09/2015
Funding: 134.310 €
Abstract: This project is aimed at exploring the use of new processing techniques and providing design tools that facilitate the development of embedded systems for intelligent environments. In order to achieve these goals we will, on the one hand, make use of soft-computing techniques to manage the inaccuracy and ambiguity of information supplied by the sensors, implement approximate inference mechanisms that emulate the human reasoning, and facilitate human-machine interaction by means of descriptions in natural language. On the other hand, we will develop new methodologies and design techniques to make it easier to explore the design space of proposed solutions.

DANTE
Adapting Mixed-signal and RF ICs Design and Test to Process and Evironment Variability
PI: Adoración Rueda Rueda
[+]
Type: Research project
Reference: TEC2011-28302
Funding Body: Ministerio de Ciencia e Innovación
Start date: 01/01/2012
End date: 31/12/2015
Funding: 276.122 €
Abstract: This project aims to face design and test challenges arisen in nanometer CMOS. It will contribute with new techniques for adapting the design and test of AMS/RF devices to process and environment variations, paving the way to the development of robust complex chips. The project is intended for dealing with three main macro-objectives:
a. The development of adaptive design techniques supporting tuning and/or calibration of circuits to face up process and environment variations.
b. The search for DfT (Design-for-Test) and BIST (Built-in self-test) solutions, directed towards facilitating component test at different abstraction levels inside a complex integrated system.
c. The devising of new experimental paradigms to verify in a lab the different concepts, methods and techniques developed in the first two bullets above. In particular, the development of experimental methodology to evaluate the sensitivity of the proposed test and calibration techniques to Single-Event Effects (SEE).

FLEXICS
Design techniques of low-cost, low-consumption, flexible and reconfigurable micro-nanoelectronic circuits and systems with application to wireless communications
PI: Francisco V. Fernández Fernández
[+]
Type: Research project
Reference: P12-TIC-1481
Funding Body: Junta de Andalucía
Start date: 30/01/2014
End date: 16/02/2019
Funding: 181.492,50 €
Abstract: The rapid development of communications systems has been possible thanks to the relentless advance of the micro / nano-electronic circuits. Although the domain of digital circuits is overwhelming, the fact remains that analog circuits, mixed signal and RF (AMS / RF) play a key role in the interface of digital circuits with the outside world, either to sense signals, act or transmitting signals in a communication channel.

Among other factors, the development of electronic technologies has been made possible thanks to the development of tools and AMS / RF design techniques, although it is true that this development has been far behind their digital counterparts. However, factors linked to technological scaling, demands for greater flexibility and reconfigurability, the greater variability of processes, degradation of the devices during operation, increasing complexity, the demand for higher performance and new business challenges, lie altogether beyond the capabilities of existing design paradigms. In fact, the strategic research agenda of the European Technology Platform on Nanoelectronics, has established the Design Tools and Techniques domain (and among them, those dedicated to AMS / RF circuits) as a critical technological domain to prioritize if we want to achieve the objectives of health, transportation, security, energy and communications in the year 2020.

In this project, we intend to address these challenges through the development of new design techniques, introducing novel techniques of modeling and synthesis of circuits that allow to design circuits beyond the current state of art, as well as new architectures and circuit topologies that facilitate incorporating greater flexibility and reconfigurability, taking next-generation wireless communications as application and demonstration field. To do this, we will deepen in the generation and application of performance fronts (models showing the best compromise between performances), defining a new concept, which we call meta-front. This new concept allows the incorporation of crucial information, beyond just circuit performances, in the design process. Thus, the meta-front includes the variability derived from manufacturing technology, parametric drifts along the life cycle of the circuits, and parasitics associated to the physical implementation, as well as the flexibility and reconfiguration capabilities required for the circuit to adapt to new condition operations. In addition, we will explore flexible architectures and circuit blocks and develop new synthesis strategies that make use of the performance modeling techniques and the information these models provide to achieve the balanced design in terms of energy consumption and cost.

As hardware demonstrator of the project, a flexible receiver will be designed and manufactured. This receiver can be continuously reconfigurable in the range of 800 MHz to 6 GHz, with bandwidths from 100KHz to 100MHz and dynamic ranges of 50dB to 75dB, thus covering the performance specifications of all communication standards in this band (GSM, UMTS, BT, GPS, DVB-H, WLAN, WiMAX, LTE etc.). This design will be done with minimum consumption and minimum cost, and it will be done so the receiver can adapt to different operating conditions. The advantages of the new techniques will be also demonstrated through its application to the design of a multi-standard data converter, a reconfigurable low noise amplifier and a circuit in commercial operation, designed with previously existing techniques and whose characterization experimental data are available.

SMART CIS3D
Smart CMOS image sensors for time-of-flight estimation and embedded analytics of 3D images
PI: Ángel Rodríguez Vázquez
[+]
Type: Research project
Reference: P12-TIC-2338 MO
Funding Body: Junta de Andalucía
Start date: 30/01/2014
End date: 16/02/2019
Funding: 239.894,00 €
Abstract: This project covers the design of image sensors that can simultaneously acquire 2D and 3D images. These sensors are able to provide both intensity maps and depth maps of the scene. One of the different approaches studied is the use of SPADs, i. e. single-photon avalanche diodes. We also contemplate the incorporation of intelligence at the sensor level. The goals are the adaptive the response of the sensors to different image capture conditions, and on-chip image processing and feature extraction.
This project covers the many different levels in the development of the sensors, from the photosensitive structures to system-on-a-chip demonstrators. We contemplate the design of the pixel circuitry, data readout and data conversion, as well as the processing blocks that confer intelligence to the sensor. We will explore the use of architectures that exploit the operation of multi-functional pixels. We will consider processing architectures based in distributed resources, like multicore architectures, based on our previous experience. We will emphasize the development of re-usable architectures using heterogeneously distributed topographic processors. In these architectural concept, processing structures are distributed across the focal plane with a different scale than the elementary sensor array. Their interaction is assigned dinamically based on the on-line identification of salient points and image features.

NANONEURO
Design of neurocortical architectures for vision applications
PI: Teresa Serrano Gotarredona
[+]
Type: Research project
Reference: TIC-6091
Funding Body: Junta de Andalucía
Start date: 13/04/2013
End date: 12/04/2017
Funding: 102.890 €
Abstract: The main goal of the NANONEURO project is to develop a neurocortical processing layer consisting of a hybrid nano/cmos convolution module with pulse-based learning. In the project, the use of different nanodevices proposed in the literature for building cortical systems will be evaluated.

 
ECOMODE
Event-driven compressive vision for multimodal interaction with mobile devices
PI: Bernabé Linares Barranco web
[+]
Type: Research project
Reference: 644096
Funding Body: European Union
Start date: 01/01/2015
End date: 31/12/2018
Funding: 556.278,75 €
Abstract: The visually impaired and the elderly, often suffering from mild speech and/or motor disabilities, are experiencing a significant and increasing barrier in accessing ICT technology and services. Yet, in order to be able to participate in a modern, interconnected society that relies on ICT technologies for handling everyday issues, there is clear need also for these user groups to have access to ICT, in particular to mobile platforms such as tablet computers or smart-phones. The proposed project aims at developing and exploiting the recently matured and quickly advancing biologically-inspired technology of event-driven, compressive sensing (EDC) of audio-visual information, to realize a new generation of low-power multi-modal human-computer interface for mobile devices.
The project is based on two main technology pillars: (A) an air gesture control set, and (B) a vision-assisted speech recognition set. (A) exploits EDC vision for low and high level hand and finger gesture recognition and subsequent command execution; (B) combines temporal dynamics from lip and chin motion acquired using EDC vision sensors with the auditory sensor input to gain robustness and background noise immunity of spoken command recognition and speech-to-text input. In contrast to state-of-the-art technologies, both proposed human-computer communication channels will be designed to work reliably under uncontrolled conditions. Particularly, mobile devices equipped with the proposed interface technology will facilitate unrestricted outdoor use under uncontrolled lighting and background noise conditions. Furthermore, due to the sparse nature of information encoding, EDC excels conventional approaches in energy efficiency, yielding an ideal solution for mobile, battery-powered devices.
ECOMODE is committed to pave the way for industrialization of commercial products by demonstrating the availability of the required hardware and software components and their integrability into a mobile platform.

NEURAM3
NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies
PI: Teresa Serrano Gotarredona web
[+]
Type: Research project
Reference: 687299
Funding Body: European Union
Start date: 01/01/2016
End date: 31/12/2018
Funding: 483.220,00 €
Abstract: We propose to fabricate a chip implementing a neuromorphic architecture that supports state-of-the-art machine learning algorithms and spike-based learning mechanisms. With respect to its physical architecture this chip will feature an ultra low power, scalable and highly configurable neural architecture that will deliver a gain of a factor 50x in power consumption on selected applications compared to conventional digital solutions; and a monolithically integrated 3D technology in Fully-Depleted Silicon on Insulator (FDSOI) at 28nm design rules with integrated Resistive Random Access Memory (RRAM) synaptic elements;
We will complete this vision and develop complementary technologies that will allow to address the full spectrum of applications from mobile/autonomous objects to high performance computing coprocessing, by realising (1) a technology to implement on-chip learning, using native adaptive characteristics of electronic synaptic elements; and (2) a scalable platform to interconnect multiple neuromorphic processor chips to build large neural processing systems. The neuromorphic computing system will be developed jointly with advanced neural algorithms and computational architectures for online adaptation, learning, and high throughput on-line signal processing, delivering:
1. An ultra-low power massively parallel non von Neumann computing platform with non-volatile nano-scale devices that support on-line learning mechanisms.
2. A programming toolbox of algorithms and data structures tailored to the specific constraints and opportunities of the physical architecture.
3. An array of fundamental application demonstrations instantiating the basic classes of signal processing tasks.
The neural chip will validate the concept and be a first step to develop a European technology platform addressing from ultra-low power data processing in autonomous systems (Internet of Things) to energy efficient large data processing in servers and networks.

HBP
Human Brain Project
PI: Bernabé Linares Barranco web
[+]
Type: Research project
Reference: 604102
Funding Body: European Union
Start date: 01/10/2013
End date: 31/03/2016
Funding: 116.250,00 €
Abstract: This proposal addresses the use of the HBP spiking hardware platforms to explore and exploit neuromorphic spiking computational architectures with feedback for high speed vision. We will combine the new spiking Dynamic Vision Sensors (DVS) with novel event-driven computing paradigms. The aim is to use a pair of DVS sensors for stereo based object recognition, with attentional feedback for recognizing and tracking objects at very high speeds. Spike-based (also called 'event-driven' (ED)) sensing and processing allows to perform multi-Iayer signal processing (with feedback), while the sensor is observing reality. This contrasts with conventional computer vision where a sensor first acquires frames and afterwards a computing system processes the frames.

 
I-COOP+ 2016
Implementación hardware de protocolos criptográficos basados en curvas elípticas para protección de sistemas de intercambio de información
PI: Santiago Sánchez Solano
[+]
Type: Research project
Reference: COOPA20141
Funding Body: CSIC
Start date: 01/01/2017
End date: 31/12/2018
Funding: 19.000,00 €
Abstract: El proyecto propuesto aborda el desarrollo e implementación de módulos hardware para acelerar el cálculo de emparejamientos bilineales sobre curvas elípticas ordinarias en el contexto de los protocolos criptográficos presentes en los sistemas de intercambio de información de efectivo electrónico.
Los elementos que inciden en el costo computacional del cálculo de emparejamientos bilineales sobre curvas elípticas pueden dividirse en cuatro niveles: la aritmética de los campos finitos; la aritmética de puntos de curva; los tipos de emparejamientos; y la integración de los emparejamientos en el contexto de un protocolo criptográfico específico. A partir de estos aspectos se identifican métodos adecuados a aplicar en el diseño de arquitecturas hardware para las operaciones involucradas en cada nivel que conduzcan a una implementación eficiente en cuanto a velocidad de respuesta, consumo de recursos y eficacia, del cálculo de los emparejamientos.
Los resultados del trabajo tendrán aplicabilidad directa en el proyecto "Mecanismos de protección en sistemas de intercambio de Información" que se desarrolla en la CUJAE y pueden resultar de gran impacto socioeconómico en Cuba.
La estrecha colaboración existente desde hace más de 15 años con el Grupo de investigación de Sistemas Digitales Empotrados de la CUJAE favorece la realización del presente proyecto.

ICOOP-A20025
Protección de sistemas empotrados sobre hardware reconfigurable para redes de sensores
PI: Santiago Sánchez Solano
[+]
Type: International cooperation project
Reference: COOPA20025
Funding Body: CSIC
Start date: 23/01/2014
End date: 31/12/2015
Funding: 22.300,00 €
Abstract: El trabajo de investigación que se propone plantea dar soluciones a los problemas de seguridad inherentes a los sistemas empotrados sobre hardware reconfigurable utilizados en redes de sensores inteligentes. Estos problemas se relacionan, tanto con la posible alteración de la funcionalidad de los nodos de la red, como con la autenticidad y confidencialidad de la información intercambiada entre los diferentes nodos. Para ello se parte de un modelo de nodo de red basado en una realización híbrida hardware/software empotrada en una FPGA, que incluye asimismo memorias externas RAM y Flash. A partir de este modelo se identifican las diferentes amenazas de seguridad y se plantean soluciones para eliminarlas. Los resultados del trabajo tendrán aplicabilidad directa en el proyecto Sistema Inteligente de Transporte que se desarrolla en el Instituto Superior Politécnico 'José Antonio Echeverría' (CUJAE) y pueden resultar de gran impacto socioeconómico en Cuba por su repercusión en el incremento de la seguridad vial, la disminución del consumo de combustible y la reducción de la contaminación ambiental. La estrecha colaboración existente desde hace más de 10 años con el Grupo de investigación de Sistemas Digitales Empotrados de la CUJAE favorece la realización del presente proyecto.