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Funding for the research activities carried out at IMSE-CNM comes primarily from the participation in competitive tender processes. The research is then conducted out via agreements, projects and contracts with national and international public organizations and private companies and organizations.


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PULPOSS
Processing for Ultra Low POwer using Steep Slope devices: circuits and arquitectures
PI: María J. Avedillo de Juan / José M. Quintana Toledo
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Type: Research project
Reference: TEC2017-87052-P
Funding Body: Ministerio de Ciencia, Innovación y Universidades
Start date: 2018
End date: 2020
Funding: 85.910,00 €
Abstract: Different applications with a great social and economic impact (loT, wearables, implantable devices, WSNs) demand circuits with very low power consumption and efficient in terms of energy. In this context, the field-effect transistor has severe limitations associated with its SS, that cannot be reduced below 60mVldec, which prevents it from reducing its polarization voltage, without significantly degrading its performance in terms of speed or excessively increasing its leakage curren!. Currently important efforts are devoted to the development of "steep slope" devices that do not exhibit this limitation. This project addresses the design of circuits and architectures implemented with these transistors in order to contribute to the development of such applications. The work developed in NACLUDE (TEC2013-40670-P) with tunneling transistors (TFETs) is extended to other steep slope devices, including negative capacitan ce transistors (NCFET, FeFET), transistors incorporating materials that exhibi! phase !ransitions (HyperFET, PC-FET) or "super steep slope" devices tha! combine these physical phenomena with TFETs (PC-TFET, NC-TFET) to improve their performance.
Although there is consensus in the scientific community about !he potential of these devices to implement circuits more efficient in terms of power consumption and energy than MaS and FinFET transistors, the simple replacement of conventional transistors by steep slope devices does not allow to obtain the maximum benefit of its use. It is necessary to adapt the topologies andlor architectures to the distinctive characteristics of ea eh device. The general objective of this project is the development of logical architectures and circuits with steep slope devices to optimize their performance in terms of power, energy or power-speed trade-offs in different application scenarios. The specific objectives that we formulate are: 1) To develop, analyze, validate and evaluate appropriate topologies for basic logical blocks; 2) to Develop, analyze, validate and evaluate appropriate logic architectures; 3) To apply design techniques for low power; 4) To explore alternative computing paradigms to CMOS logic; 5) To maintain a library of models of steep-slope devices updated with the advances and proposals that are taking place.

HW-IDENTIoTY
Design of hardware solutions to manage people and things identities with trust, security, and privacy in IoT ecosystem
PI: Iluminada Baturone Castillo / Piedad Brox Jiménez web
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Type: Research project
Reference: TEC2017-83557-R
Funding Body: Ministerio de Ciencia, Innovación y Universidades
Start date: 2018
End date: 2020
Funding: 139.150,00 €
Abstract: In the Internet of Things (IoT) ecosystem, people will be surrounded by a growing number of smart devices with sensors and actuators, which capture information about our environments and act upon them autonomously (our cities, homes, cars or bycicles and even our body). As a matter of fact, people already interact more with or through these devices instead of interacting directly. The IoT infraestructure is aimed at improving our quality of life, but if it is not trust, secure and does not guarantee our privacy, the consequences can be catastrophic.
A first challenging aspect is to ensure that individuals and devices are trusted and authentic and, hence, that their identities are resistant to impersonation and counterfeiting. Since the physical nature of an IoT device lies in the hardware it is made of, HW-IDENTIoTY project will design hardware solutions based on physical unclonable functions (PUFs) to generate inherent identities of devices. Since the unique features of a person can be captured by a biometric recognition system, HW-IDENTIoTY project will design hardware solutions to implement lightweight biometric recognition techniques that could be implemented in a wearable, so that the digital identity of the person is generated locally by a trusted device under the supervision of the identity owner.
A second critical issue is to guarantee privacy. For this purpose, the digital identities will be transformed in such a way that the resulting data cannot be attributed to a specific individual or device without the use of additional information. HW-IDENTIoTY project will design hardware solutions to implement Helper Data algorithms in the case of devices and template protection techniques in the case of individuals.
The third aspect addressed will be the design of hardware solutions robust against attacks to implement cryptographic primitives paradigm. They will be related to symmetric and lightweight cryptography in the case of wearables (with constrained resources and low-power consumption requirements) and to elliptic curve cryptography in the case of embedded systems. The availability of counterfeit-resistant identities will be exploited to address problems associated with digital chains of custody and traceability in IoT.

TOGETHER
Towards Trusted Low-Power Things: Devices, Circuits and Architectures
PI: Francisco V. Fernández Fernández / Rafael Castro López
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Type: Research project
Reference: TEC2016-75151-C3-3-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2019
Funding: 240.911,00 €
Abstract: To bridge the gap between the physical and digital worlds, any type of product would need to integrate networked electronic components and systems, built on micro/nanotechnologies, in what has been called "Internet of Things" (IoT). To fulfill the IoT vision, many technology enablers are required, with trusted (i.e., reliable and secure) as well as low-power ICs and components, among others, playing a pivotal role. All these enablers must be properly handled with a multidomain approach -covering device, circuit and architectural levels- in a context where technology scaling has slowed down. Thus, at technology level, innovations in materials and device structures will be required and, next to this, low-power robust circuits and alternative architectures will have to be implemented. Consequently, the experience of researchers with complementary expertise must be properly combined under a collaborative framework. Following these guidelines, device reliability engineers (UAB) and analog and digital circuit designers (IMSE and UPC) will work together in this project on the design of low-power, variability-resilient nanoelectronic circuits and systems, by using a multilevel approach and taking into account IoT challenges.
To achieve this general objective, several lines of work will be followed. Since circuit and system design for IoT relies upon a deep knowledge of phenomena at device level, a detailed statistical and multiscale characterization of the variability in advanced CMOS devices will be done in all regimes of operation, for the development of variability-aware compact models. Emerging devices (i.e., memristors and graphene-based devices) will be also considered to evaluate their suitability as building components in alternative circuits and architectures. At circuit and system levels, low-power and variability-resilient design strategies and methodologies will be developed. Variability will be tackled from two perspectives: palliation and exploitation. From a palliative perspective, adequate design methodologies will be created, able to consider and reduce variability across many hierarchical levels in a complex AMS/RF system. Also, the use of Body Bias modulation for variability mitigation in RF and digital circuits in FDSOI technologies will be analyzed. From the exploitation perspective, unreliability aspects in CMOS and memristive devices will be explored for the implementation of cryptographic primitives. Energy-efficient hierarchical design methodologies will be implemented to reduce power consumption in AMS/RF circuits and ultra-low voltage AMS/RF and digital circuits will be designed. Non-conventional strategies for computing systems and non-von Neumann computing architectures will be studied too. Finally, the adoption of emerging technologies for alternative computing architectures (combining memristors and FETs) as well as neuromorphic architectures will be addressed. The innovations in devices, design techniques, extremely low-power and reliable circuits and architectures will enable competitive advantages in numerous IoT applications and markets, supporting the relevance of the proposed research from the societal, industrial and economical points of view. This fact, together with the experience of the proposing partners, foresees publications and technology transfer of the results.

INTERVALO
Integration and validation in laboratory of countermeasures against side-channel attacks in microelectronic cryptocircuits
PI: Antonio J. Acosta Jiménez / Carlos J. Jiménez Fernández
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Type: Research project
Reference: TEC2016-80549-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2019
Funding: 104.544,00 €
Abstract: Security and privacy in communication are certainly one major right for institutions and people in general, being those factors of strategic interest in our society. Nowadays there are many electronic devices in which security is a must and most of these systems use cryptographic techniques to achieve confidentiality and inviolability in private data management. Many secure electronic systems include cryptographic devices implementing mathematical algorithms that are directed to hide sensitive information. However, due to their specific implementation as a circuit, side channel attacks can be successfully performed and information extracted. Therefore, paying special attention to the physic implementation of cryptographic devices is a crucial point to minimize the leak of information under side channel attacks. Hence, hardware implementations in the case of cryptographic algorithms require an adequate and correct realization of algorithms from the functional point of view as much as the inclusion of robust security mechanisms in order to diminish vulnerability. Most of portable security applications (RFID keys, USB memories, smart cards, etc.) use symmetric encryption that has to be integrated in very low power hardware (lightweight cryptography) what has to be required in the new environments resulting of the Internet of things. This Project aims to obtain a set of countermeasures libraries to be included in high performance hardware implementations (ASICs) in CMOS nanometer technology. The focus will be to increase the security of portable systems against side attacks facing secure (de)ciphering problems. Countermeasures will be proposed at a variety of abstraction levels, going from architecture to layout. These will be ready to be used in any stream or block cipher for any kind of application. Different strategies of passive attacks based on power analysis (DPA), electromagnetic emissions (DEMA) and active non-invasive attacks based on fault injection (clock signal, power supply, temperature) and invasive (light source or pulsed laser) will be considered. Hardware implementations (ASIC) will be developed, including area, frequency and power consumption optimization as well as side channel attacks security improvement. The main concern will be to optimize the systems performance accomplishing security increases with no penalties for this performance. To this aim, vulnerability measures, both experimental and simulated will be very important to qualify the countermeasures and the designed hardware.
The three primary targets of the Project are:
To develop automatic experimental mechanisms to analyze the vulnerability of hardware implementations of ciphering circuits and its application on real implementations.
To propose, design and test hardware countermeasures of different categories to diminish vulnerability in crypto circuits.
To design, integrate and test an ASIC with ciphers including the proposed countermeasures and include the ASIC in a IoT system to evaluate the improvements in security in real systems.

IPANEMA
Integrated Pattern-Adaptive optical NEurostimulator with Multi-site recording Array
PI: Manuel Delgado Restituto
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Type: Research project
Reference: TEC2016-80923-P
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 01/01/2017
End date: 29/12/2019
Funding: 145.200,00 €
Abstract: This Project aims to provide enabling microelectronic technologies for the integration and miniaturization of a smart neural stimulation system based on optogenetics, which serves as experimental vehicle for the development of new procedures in neurobiology and, ultimately, for the implementation of new neural prosthesis, more focus and secure than those currently available, for the treatment of different pathologies of the nervous system (severe sensory deficits, brain diseases, chronic pain, and others).
Within this general scenario, our objective will be to provide the basis towards a reliable and efficient closed-loop mechanism which, based on the electrical activity recorded from the genetically encoded cells, is able to provide an efficient and non-harmful actuation by optic means. This real-time feedback procedure will support the adaptability of the system to the plasticity of the neural tissue and, thereby, it will open up doors for the implementation of robust, long lifetime neural prosthesis whose operation self-adjusts to the patient's progress.
The system to be developed will be scalable and reconfigurable with the number of recording electrodes and optical stimulation sources (it might be regarded as a MIMO -multi-input, multi-output- control system) and will allow the activation of LEOs incorporated into the probe or, alternatively, the triggering of any convenient external light source by means of a custom data pathway. In the former case, LEOs may be placed in direct contact with the tissue (by using micro-LEOs integrated in the probe) or employ optical fibers for guiding photostimulation. For the sake of easy handling, data transfer to/from the complete recording/stimulation system will employ wireless techniques.
According to this concept, the system implementation will encompass the fabrication of two Application-Specific Integrated Circuits (ASICs) together with so me commercial components (essentially, a microcontroller for supervising the stimulation feedback loop and an ultra-low power wireless transceiver). One of the ASICs, denoted as stimulation ASIC, will implement the stimulation circuitry, whereas, the other ASIC, denoted as acquisition ASIC, will include circuits for recording, processing and communications, as well as a power management unit!. A multi-chip solution is preferred over a single monolithic integration in order to increase the reliability of the system, reduce the fabrication risks, and improve the performance of the neural recording channels which, otherwise, it would become adversely affected by the commutations of the stimulation circuitry.
The ASICs will be fabricated in a low-cost O.18um CMOS technology and tested either individually, or connected one to another in the final system platform. Their characterizations will consist in mixed-signal and optical tests in the premises of our laboratories. Additionally, we will lay plans on the validations of the prototypes with in vitro and in vivo measurements, to be carried out in Bioengineering Institutes with which the applicant group holds collaboration agreements.

MINES-SVM
Microelectronics for Space Instrumentation: MEDA Wind-Sensor ASIC
PI: Servando Espejo Meana
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Type: Research project
Reference: ESP2016-79612-C3-3-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2018
Funding: 266.200,00 €
Abstract: MINES-SVM, as a sub-project within the coordinated project M3EC, has specific objectives related to the development of the mixed-signal ASIC required for the MEDA wind sensor, which will be included in NASA's Mars2020 mission. An operative prototype of this ASIC is currently (April 2016) available, as a result of previous projects and contracts. It is in its final functional verification stage, and will probably satisfy the requirements and specs of the instrument. The technology employed for the design and manufacturing of the ASIC is a standard 0.35 microns CMOS process. This technology had been previously characterized for space use by the research team, also in the framework of previous projects.
The MEDA ASIC performs the functions of analog front-end for temperature sensors based on platinum resistors and thermopiles, and sigma-delta thermal control loops and power measurements. This includes signal conditioning and analog to digital conversion, as well as configuration and data communications through a standard digital interface. The design employs Radiation Hardening By Design (RHBD) techniques, including functional redundancy and specific layout techniques.
Within this framework, the first objective of MINES-SVM is to finalize the test and validation for space use of this ASIC. This includes the completion of the electrical functional tests, as well as the verification of the radiation hardness and the behavior at low and high temperatures through specific additional tests.
The ASIC must be manufactured again in order to achieve a minimum number of samples, as required by the formal screening associated with its use in space. Minor refinements could be introduced in the design in this new manufacturing lot, depending on the results of the functional tests and the radiation hardness and low-temperature tests. In any case, the final version of the ASIC, with its final packaging, will need to be qualified for space use following formal processes by an external agent. This will require the design of several test systems for the functional/electrical validation tests, and for those tests related to radiation tolerance (both TID and SEEs), low-temperature behaviour, and life-tests of the ASIC. The second objective of MINES-SVM is the integration of the ASIC in the engineering and flight modules of the wind sensor, and the calibration of the overall measuring system. The integration of the wind sensor within the rover, considering possible effects on the measuring function, will also be supported.
The main result of MINES-SVM will be the availability of this space-qualified ASIC. This will represent a clear competitive advantage for future missions and similar designs.
As a collateral result, this subproject will help to consolidate the space-microelectronics design capability at a national level. The technologies involved have been identified as critical at the European level, including microelectronics, discrete-components electronics, advanced packaging materials, and the mitigation of the radiation effects on electronic systems. In summary, the background objective is to generate, at a national level, a complete set of mature and high performance resources for the development of space instruments demanded by the national or international scientific community, or by other sectors traditionally linked to the space sector like those of Security and Defense.

ASIC-SIS
ASIC for compacts solar irradiation sensor
PI: Diego Vázquez García de la Vega
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Type: Research project
Reference: ESP2016-80320-C2-2-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2018
Funding: 169.400,00 €
Abstract: This Project (ASIC-SIS) represents a very important technology activity for the development of a Mixed-Signal ASIC for special applications in the Mars surface. This activity started years ago (2008) in the context of the MetNet mission and give as a result the creation of a research group in the IMSE-CNM/University of Seville specialized in this kind of designs. Thanks to these efforts, it was possible to provide solutions to the needs of signal conditioning and compaction of wind sensors for the MEDA station.
It should be mentioned that the development of Mixed-Signal ASICs for space use has been identified in H200 as a strategic line for Europe and the not dependence. This project follows this line intending the development of an ASIC to support future and even more compact Solar Irradiation Sensors (SIS) that are being recursively used for surface mission in Mars (SIS are present in 4 missions: MetNet, EXM'16, EXM'18 y Mars2020); it demonstrates the large interest of this kind of systems. So, the project aims the maximum compaction as possible of the SIS but also providing added values of reliability and re-usability as well as incrementing its scientific potential to become a reference sensor at international level for future missions.
Namely, the global ASIC-SIS objective is the development of a Mixed-Signal CMOS ASIC for the advanced Solar Irradiation Sensor (SIS). It contemplates all the required phases or steps: definition of specifications and/or requirements, synthesis at different levels (architectural, circuits blocks, devices, etc.), fabrication, validation, qualification, etc., AII the work concerning the design of the ASIC will be carried out by the US but in collaboration with INTA, who will give the necessary support in the specifications and requirements during the different validation steps. Finally, the US will give to INTA the support to perform the validations of a compact SIS prototype including the ASIC.

COGNET
Event-based cognitive vision system. Extension to audio with sensory fusion
PI: Teresa Serrano Gotarredona
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Type: Research project
Reference: TEC2015-63884-C2-1-P
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2016
End date: 31/12/2019
Funding: 197.956,00 €
Abstract: The global goal of the COGNET project is to advance in the theoretical and technological development of event-based sensing and processing systems and demonstrate its potential to solve practical problems in a more efficient way than conventional technologies do. In particular, in the COGNET project we will address event-based vision and audition sensing, event-based vision and audition recognition systems and their off-line and on-line training, and the fusion of visual and auditive information to perform multisensory recognition tasks in real time. In COGNET, we are trying to demonstrate the superior performance of the event-based technology in two practical problems. The first one is binocular-based high-speed vehicle obstacle detection with few milliseconds response time, and the second one is visually guided speech recognition in a noisy environment.

iCAVEATS
Integrated components and architectures for embedded vision in transportation and security applications
PI: Ricardo Carmona Galán web
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Type: Research project
Reference: TEC2015-66878-C3-1-R
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2016
End date: 31/12/2018
Funding: 197.714,00 €
Abstract: This project aims to the capitalization of the acquired know-how by developing a library of hardware components and architectures. They have to be compatible with OpenVX descriptions and aimed to reduce power consumption of mainly-software implementations. We will include low and medium-level processing blocks, new sensor abilities, like photon counting and time-of-flight estimation, and aspects more related to the system level, like energy management and interfacing with other signal processing chips. We will explore technological alternatives that may provide a more efficient implementation of OpenVX functions. These modifications will be transparent from the point of view of the application developer and the designer of computer vision algorithms.
In order to demonstrate the validity of the approach we will build a vision system on-a-chip for intelligent transportation and security applications. We will develop demonstrators to properly expose the potential of this approach to embedded vision.

ID-EO
Design of crypto-biometric hardware for video encryption and authentication
PI: Piedad Brox Jiménez / Iluminada Baturone Castillo web
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Type: Research project
Reference: TEC2014-57971-R
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2015
End date: 31/12/2018
Funding: 187.550,00 €
Abstract: As more and more individuals and devices (Iaptops, tablets, smartphones, cameras, etc.) are interconnected through public networks, it is essential to ensure that the information exchanged (multimedia many times) really comes from individuals and devices that must generate, store, or process it. The generation of cryptographic keys from the intrinsic nature of devices or individuals not only ensures their digital identity when they access or provide information but also allow the encryption and authentication of such information, bonding it to the counterfeit-resistant identities.
Since a cryptographic system is as secure as its secret key, there is a growing interest in increasing the security of cryptographic key storage by using specific hardware, rather than just having software solutions. This is the reason why digital hardware (crypto-modules) will be designed in ID-EO project to generate the keys when needed instead of storing them, always involving the authentic device or individual designated to generate them. Moreover, they will be able to generate truly random numbers and identifíers. The modules will offer diversification, because they can generate different keys from the same identity, and revocability, because if one key is compromised, a new one can be generated at a new registration process.
The design of crypto-modules that could provide such functionality would find a very wide range of applications. In particular, a natural application domain is embedded vision systems that would become 'chains of trust', ensuring the authenticity of the system ítself and the confidentiality, privacy and integrity of the video captured and processed by the system. Nowadays, the proliferation of communications and web technologies has created an environment in which the security of the images and videos that are transmitted or stored in open channels is questioned. This is the reason why trust embedded vision systems will be designed in the ID-EO project, capable of real-time video selective encryption and authentication with constrained resources and low-power consumption.

n-PATETIC
New paradigms for testing mixed-signal integrated circuits
PI: Adoración Rueda Rueda
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Type: Research project
Reference: TEC2015-68448-R
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2016
End date: 31/12/2018
Funding: 196.020,00 €
Abstract: This project aims to develop low-cost, reliable, and verifiable test solutions for analog, mixed-signal, and radio frequency circuits (AMS/RF). Capitalizing the skill of the designer on the design process of such circuits and on the limitations of the test techniques developed to date, we intend to seek new test paradigms that allow safely abandon the traditional methods of functional test. In this way, it could contribute to decrease the test cost that represents today about half the cost of manufacturing a complex circuit. We will focus on functional alternative methods and indirect test methods. The first will measure functional parameters but will be less expensive than standard techniques, thus relaxing the requirements of the test equipments. The later would be aimed at the detection of defects, and will be based on the assumption of considering that the circuit is correct by construction and what is sought with the test are indications of possible degradation. This can be a paradigm shift of very important consequences in current electronic products; if the project gives the expected results, this methodology could have a similar impact on the AMS-RF circuits that it had the introduction of the Boundary-Scan in digital circuits.
Since it is extremely complex to reliably validate a technique test before mass production of circuits, also in this project we intend lo address the problem of lest verification, developing behavioral models aimed at facilitating the verification quickly and efficiently.
In this context, the project aims to address three general objectives:
1. Capitalize information on the design process and verification of AMS-RF circuits, creating documentation and/or modeling allowing the development of new test paradigms that represent significant improvements lo the quality/test tradeoff. We want to explore how we can formalize and systematize what we know of the circuit to develop robust and reliable test.
2. Develop reliable and verifiable solutions for the test of these circuits. The shift from a paradigm of functional test, in which the performance of the circuits are measured by standard processes for comparison with your specifications, to a paradigm of indirect test in which the decision to accept or reject a circuit is made based on deviations of so me firms, contains a great potential for significant cost reduction.
3. Explore and develop systematic methodologies for functional low-cost test not only for validating products in the post-production phase, but also with the purpose to their application in 81ST schemes for online test.
As vehicles for proof of concept we will use CMOS prototypes already made by the applicant team, namely, high performance Analog Digital converter (ADC) (> 12bits and up to 1 OOMS / s) and building blocks of front-ends in RF wireless transceivers. Some of these designs have to be adapted to incorporate additional circuitry to facilitate access to certain signals as well as for the implementation of the DfT or BIST techniques derived from the new developed test paradigms.

INFRAESTRUCTURAS Y EQUIPAMIENTO CIENTÍFICO-TÉCNICO
Mejora y actualización de equipos para el laboratorio de diseño de circuitos integrados del Instituto de Microelectrónica de Sevilla
PI: Santiago Sánchez Solano
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Type: Facilities
Reference: CSIC15-CE-3118
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2016
End date: 31/12/2017
Funding: 196.230,48 €
Abstract: El objetivo de este proyecto es la adquisición e instalación de los sistemas necesarios para actualizar y reforzar la infraestructura informática del Laboratorio de Diseño de Circuitos Integrados del Instituto de Microelectrónica de Sevilla (IMSE-CNM). Dicho laboratorio agrupa al conjunto de equipos de cálculo, sistemas de almacenamiento, herramientas de diseño y kits de tecnologías de fabricación que soportan las diferentes etapas de diseño de los circuitos integrados que se llevan a cabo en el centro.
Las actuaciones previstas van encaminadas a conseguir tres objetivos básicos:
- Incrementar la potencia de cálculo disponible, con idea de poder hacer frente al uso exhaustivo de las distintas herramientas de CAD que surge como consecuencia del aumento de la densidad de integración y la reducción de las tensiones de polarización y las dimensiones mínimas de los dispositivos en las actuales tecnologías de fabricación de circuitos integrados.
- Mejorar el sistema de almacenamiento de datos, tanto en capacidad como en velocidad, para posibilitar el diseño de sistemas de mayor complejidad y evitar que la tasa de transferencia de datos suponga un cuello de botella en el proceso de cómputo y generación de resultados.
- Remodelar y reforzar el sistema de enfriamiento de la sala de sistemas del instituto, con idea de proporcionar las condiciones de operación adecuadas para los distintos sistemas.
La infraestructura del Laboratorio de Diseño de Circuitos Integrados resulta básica para el desarrollo de las distintas actividades de diseño de circuitos y sistemas microelectrónicos que llevan a cabo los diferentes grupos de investigación del Instituto. La alta cualificación de su personal y la experiencia acumulada, así como el equipamiento científico-tecnológico con que cuenta, han permitido al IMSE-CNM alcanzar una posición de referencia en Europa respaldada por los resultados obtenidos en la ejecución de numerosos proyectos y contratos de investigación.

INFRAESTRUCTURAS Y EQUIPAMIENTO CIENTÍFICO-TÉCNICO
Equipamiento de medida y test de circuitos integrados en el Instituto de Microelectrónica de Sevilla
PI: Adoración Rueda Rueda
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Type: Facilities
Reference: UNSE15-CE-3191
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2016
End date: 31/12/2017
Funding: 163.092,00 €
Abstract: El objetivo de esta solicitud es la adquisición de diferentes equipos de medida y test para completar y renovar el equipamiento actualmente disponible en los laboratorios del Instituto de Microelectrónica de Sevilla (IMSE-CNM), con el doble propósito de fortalecer su posición como centro de referencia en actividades de diseño de circuitos integrados y afrontar con mayores garantías el reto que plantea su participación en numerosos proyectos y contratos de investigación.
Las actuaciones previstas persiguen un doble objetivo. Por una parte, complementar el equipamiento disponible en el Instituto con nuevo instrumental que proporcione prestaciones mejoradas acordes con las necesidades que plantean las actividades de I+D+I actualmente en curso, a la vez que sitúe a los grupos de investigación del centro en posición de abordar retos más exigentes en el futuro. Concretamente, se incorporarán cuatro nuevos osciloscopios con ancho de banda entre 350 y 500MHz, un analizador lógico de 48 canales de generación de patrones y 68 canales de adquisición a 250MHz, y dos analizadores de señal de DC de alta resolución.
Por otra parte, en relación con la línea de diseño de dispositivos y sistemas optoelectrónicos y con idea de afrontar los retos que se plantean a la hora de la caracterización de la nueva generación de sensores de luz (no específicamente restringida a la visible) se incorporará un nuevo sistema de caracterización que permita incrementar la potencia del haz de luz y el rango de longitud de onda.
Las mejoras en las facilidades de test del IMSE-CNM como consecuencia de la ejecución de esta acción reforzarán de forma notable la calidad y diversidad de los equipos y prestaciones incluidos en la Carta de Servicios ofrecida por el Instituto e incrementarán el número de potenciales usuarios pertenecientes a grupos de investigación de organismos públicos y privados en el área de la Microelectrónica.

SENIAC
Security in interconnected devices by injection of authentication and ciphering algorithms
PI: Iluminada Baturone Castillo web
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Type: Research project
Reference: RTC-2014-2932-8
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/10/2014
End date: 31/03/2017
Funding: 77.809,64 €
Abstract: The main objective of SENIAC project is to achieve that interconnected devices form a chain-of-trust, providing information confidentiality and integrity as well as authentication and non revocability, through the secure injection of ciphering and authentication methods. A highly secure software platform will be developed that, once injected in the devices via firmware reprogramming, will provide cryptographic and physical authentication techniques, avoiding counterfeit of the devices in a network.

KIT-LTCC
Design Kit Development in LTCC ceramic technology: modeling, simulation and fabrication of components and circuits, and design methodology
PI: Elisenda Roca Moreno
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Type: Research project
Reference: RTC-2014-2426-7
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/09/2014
End date: 31/01/2017
Funding: 47.205,44 €
Abstract: The main objective of this project is the development of a design methodology for electronic systems in an LTCC technology using a library of 3D components and basic blocks that can be distributed as a Process Design Kit (PDK) to potential users of the technology. The project is funded by the "Programa Estatal de Investigación, Desarrollo e Innovación Orientada a los Retos de la Sociedad", within the framework of the "Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016". Participants are FRANCISCO ALBERO S.A.U., Radiofrequency Group of the University of Barcelona (FBG-UB) and the Instituto de Microelectrónica de Sevilla.


MIXCELL
Integrated MicroSystems for Cell-Culture Assays
PI: Alberto Yúfera García
[+]
Type: Research project
Reference: TEC2013-46242-C3-1-P
Funding Body: Ministerio de Economía y Competitividad
Start date: 01/01/2014
End date: 31/12/2017
Funding: 108.900,00 €
Abstract: This project will be focused on cell-culture monitoring by using impedance and/or capacity measurements. It means a radical change in the conception of the work on cell-culture laboratories, making it possible to supervise an experiment in real-time and remotely during days and, therefore, to increase the measurement sensitivity in many cell-processes like motility and cytotoxicity. The present approach pursues the implementation of integrated CMOS systems for measuring impedance and capacity in cell-cultures in real-time, contributing not only with techniques and strategies but also to the design of high performance integrated circuits: energetic autonomy (LP, LV), capacity for wireless communication, accuracy and bandwidth. The goal of this proposal is to develop new useful analogical front-ends for bio-impedance measurements. In parallel, we will address the problems of characterizing and modeling the employed bio-sensors, and their incorporation into the flow design of the measurement integrated circuits. Our purpose is to evolve towards the concept of on-chip, autonomous systems or laboratories (LoC). The main and final objective, based on the obtained results, will be to achieve a system capable of carrying out the characterization of a cell-culture, establishing a biometric procedure allowing us the identification of different cellular lines and types, characterizing experiments of motility in lines of cancer cells, and evaluating the possibilities of sensing for measuring stem cell proliferation, giving solutions based on electrical resistance and capacity. Our concluding results will be validated with the experimental standards used in biomedical laboratories.
The aims to develop in this project are:
1) Generate techniques and strategies for measuring bio-impedances based on analog signal processing.
2) Design of analog and mixed-signal CMOS integrated systems.
3) Verification of the existing models for the interface sensor-cells and development of new alternatives. Application to simulation, cellular-biometry and microscopy.
4) Experimentation in biomedical labs for monitoring and characterization of cell-cultures, proliferation assays, cancer-cell motility and stem cell proliferation.

FLEXICS
Design techniques of low-cost, low-consumption, flexible and reconfigurable micro-nanoelectronic circuits and systems with application to wireless communications
PI: Francisco V. Fernández Fernández
[+]
Type: Research project
Reference: P12-TIC-1481
Funding Body: Junta de Andalucía
Start date: 30/01/2014
End date: 16/02/2019
Funding: 181.492,50 €
Abstract: The rapid development of communications systems has been possible thanks to the relentless advance of the micro / nano-electronic circuits. Although the domain of digital circuits is overwhelming, the fact remains that analog circuits, mixed signal and RF (AMS / RF) play a key role in the interface of digital circuits with the outside world, either to sense signals, act or transmitting signals in a communication channel.

Among other factors, the development of electronic technologies has been made possible thanks to the development of tools and AMS / RF design techniques, although it is true that this development has been far behind their digital counterparts. However, factors linked to technological scaling, demands for greater flexibility and reconfigurability, the greater variability of processes, degradation of the devices during operation, increasing complexity, the demand for higher performance and new business challenges, lie altogether beyond the capabilities of existing design paradigms. In fact, the strategic research agenda of the European Technology Platform on Nanoelectronics, has established the Design Tools and Techniques domain (and among them, those dedicated to AMS / RF circuits) as a critical technological domain to prioritize if we want to achieve the objectives of health, transportation, security, energy and communications in the year 2020.

In this project, we intend to address these challenges through the development of new design techniques, introducing novel techniques of modeling and synthesis of circuits that allow to design circuits beyond the current state of art, as well as new architectures and circuit topologies that facilitate incorporating greater flexibility and reconfigurability, taking next-generation wireless communications as application and demonstration field. To do this, we will deepen in the generation and application of performance fronts (models showing the best compromise between performances), defining a new concept, which we call meta-front. This new concept allows the incorporation of crucial information, beyond just circuit performances, in the design process. Thus, the meta-front includes the variability derived from manufacturing technology, parametric drifts along the life cycle of the circuits, and parasitics associated to the physical implementation, as well as the flexibility and reconfiguration capabilities required for the circuit to adapt to new condition operations. In addition, we will explore flexible architectures and circuit blocks and develop new synthesis strategies that make use of the performance modeling techniques and the information these models provide to achieve the balanced design in terms of energy consumption and cost.

As hardware demonstrator of the project, a flexible receiver will be designed and manufactured. This receiver can be continuously reconfigurable in the range of 800 MHz to 6 GHz, with bandwidths from 100KHz to 100MHz and dynamic ranges of 50dB to 75dB, thus covering the performance specifications of all communication standards in this band (GSM, UMTS, BT, GPS, DVB-H, WLAN, WiMAX, LTE etc.). This design will be done with minimum consumption and minimum cost, and it will be done so the receiver can adapt to different operating conditions. The advantages of the new techniques will be also demonstrated through its application to the design of a multi-standard data converter, a reconfigurable low noise amplifier and a circuit in commercial operation, designed with previously existing techniques and whose characterization experimental data are available.

SMART CIS3D
Smart CMOS image sensors for time-of-flight estimation and embedded analytics of 3D images
PI: Ángel Rodríguez Vázquez
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Type: Research project
Reference: P12-TIC-2338 MO
Funding Body: Junta de Andalucía
Start date: 30/01/2014
End date: 30/06/2019
Funding: 239.894,00 €
Abstract: This project covers the design of image sensors that can simultaneously acquire 2D and 3D images. These sensors are able to provide both intensity maps and depth maps of the scene. One of the different approaches studied is the use of SPADs, i. e. single-photon avalanche diodes. We also contemplate the incorporation of intelligence at the sensor level. The goals are the adaptive the response of the sensors to different image capture conditions, and on-chip image processing and feature extraction.
This project covers the many different levels in the development of the sensors, from the photosensitive structures to system-on-a-chip demonstrators. We contemplate the design of the pixel circuitry, data readout and data conversion, as well as the processing blocks that confer intelligence to the sensor. We will explore the use of architectures that exploit the operation of multi-functional pixels. We will consider processing architectures based in distributed resources, like multicore architectures, based on our previous experience. We will emphasize the development of re-usable architectures using heterogeneously distributed topographic processors. In these architectural concept, processing structures are distributed across the focal plane with a different scale than the elementary sensor array. Their interaction is assigned dinamically based on the on-line identification of salient points and image features.

NANONEURO
Design of neurocortical architectures for vision applications
PI: Teresa Serrano Gotarredona
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Type: Research project
Reference: TIC-6091
Funding Body: Junta de Andalucía
Start date: 13/04/2013
End date: 12/04/2017
Funding: 102.890 €
Abstract: The main goal of the NANONEURO project is to develop a neurocortical processing layer consisting of a hybrid nano/cmos convolution module with pulse-based learning. In the project, the use of different nanodevices proposed in the literature for building cortical systems will be evaluated.

 
ACHIEVE
Advanced Hardware/Software Components for Integrated/Embedded Vision Systems
PI: Ricardo Carmona Galán web
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Type: Research project
Reference: 765866
Funding Body: European Union
Start date: 01/10/2017
End date: 30/09/2021
Funding: 2.230.856,64 €
Abstract: ACHIEVE-ETN aims at training a new generation of scientists through a research programme on highly integrated hardware-software components for the implementation of ultra-efficient embedded vision systems as the basis for innovative distributed vision applications. They will develop core skills in multiple disciplines, from image sensor design to distributed vision algorithms, and at the same time they will share the multidisciplinary background that is necessary to understand complex problems in information-intensive vision-enabled aplliccations. Concurrently, they will develop a set of transferable skills to promote their ability to cast their research results into new products and services, as well as to boost their career solutions for emerging technology markets in Europe and worldwide but also to drive new businesses through engaging in related entrepreneurial activities. The consortium is composed of 6 academic and 1 insdustrial beneficiaries and 4 industrial partners. The training of the 9 ESRs will be achieved by the proper combination of excellent research, secondments with industry, specific courses on core and transferable skills, and academic-industrial workshops and networking events, all in compliance with the call´s objectives of international, intersectoral and interdisciplinary mobility.

NEURAM3
NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies
PI: Teresa Serrano Gotarredona web
[+]
Type: Research project
Reference: 687299
Funding Body: European Union
Start date: 01/01/2016
End date: 30/06/2019
Funding: 483.220,00 €
Abstract: We propose to fabricate a chip implementing a neuromorphic architecture that supports state-of-the-art machine learning algorithms and spike-based learning mechanisms. With respect to its physical architecture this chip will feature an ultra low power, scalable and highly configurable neural architecture that will deliver a gain of a factor 50x in power consumption on selected applications compared to conventional digital solutions; and a monolithically integrated 3D technology in Fully-Depleted Silicon on Insulator (FDSOI) at 28nm design rules with integrated Resistive Random Access Memory (RRAM) synaptic elements;
We will complete this vision and develop complementary technologies that will allow to address the full spectrum of applications from mobile/autonomous objects to high performance computing coprocessing, by realising (1) a technology to implement on-chip learning, using native adaptive characteristics of electronic synaptic elements; and (2) a scalable platform to interconnect multiple neuromorphic processor chips to build large neural processing systems. The neuromorphic computing system will be developed jointly with advanced neural algorithms and computational architectures for online adaptation, learning, and high throughput on-line signal processing, delivering:
1. An ultra-low power massively parallel non von Neumann computing platform with non-volatile nano-scale devices that support on-line learning mechanisms.
2. A programming toolbox of algorithms and data structures tailored to the specific constraints and opportunities of the physical architecture.
3. An array of fundamental application demonstrations instantiating the basic classes of signal processing tasks.
The neural chip will validate the concept and be a first step to develop a European technology platform addressing from ultra-low power data processing in autonomous systems (Internet of Things) to energy efficient large data processing in servers and networks.

ECOMODE
Event-driven compressive vision for multimodal interaction with mobile devices
PI: Bernabé Linares Barranco web
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Type: Research project
Reference: 644096
Funding Body: European Union
Start date: 01/01/2015
End date: 31/12/2018
Funding: 556.278,75 €
Abstract: The visually impaired and the elderly, often suffering from mild speech and/or motor disabilities, are experiencing a significant and increasing barrier in accessing ICT technology and services. Yet, in order to be able to participate in a modern, interconnected society that relies on ICT technologies for handling everyday issues, there is clear need also for these user groups to have access to ICT, in particular to mobile platforms such as tablet computers or smart-phones. The proposed project aims at developing and exploiting the recently matured and quickly advancing biologically-inspired technology of event-driven, compressive sensing (EDC) of audio-visual information, to realize a new generation of low-power multi-modal human-computer interface for mobile devices.
The project is based on two main technology pillars: (A) an air gesture control set, and (B) a vision-assisted speech recognition set. (A) exploits EDC vision for low and high level hand and finger gesture recognition and subsequent command execution; (B) combines temporal dynamics from lip and chin motion acquired using EDC vision sensors with the auditory sensor input to gain robustness and background noise immunity of spoken command recognition and speech-to-text input. In contrast to state-of-the-art technologies, both proposed human-computer communication channels will be designed to work reliably under uncontrolled conditions. Particularly, mobile devices equipped with the proposed interface technology will facilitate unrestricted outdoor use under uncontrolled lighting and background noise conditions. Furthermore, due to the sparse nature of information encoding, EDC excels conventional approaches in energy efficiency, yielding an ideal solution for mobile, battery-powered devices.
ECOMODE is committed to pave the way for industrialization of commercial products by demonstrating the availability of the required hardware and software components and their integrability into a mobile platform.

 
IndieTEST
Indirect test solutions for analog, mixed-signal, and RF integrated systems
PI: Gildas Léger
[+]
Type: Proyectos bilaterales
Reference: PIC2016FR5
Funding Body: CSIC
Start date: 01/01/2017
End date: 31/12/2019
Funding: 10.000,00 €
Abstract: The combination of indirect test and built-In Self-Test (BIST) is a promising solution to mitigate the increasing cost of testing complex mixed-signal integrated systems. Indirect test replaces complex specification measurements by simpler signatures, and then uses moden data analysis algorithms to map these signatures onto the specification space. Signatures can be efficiently monitored by simple on-chip test instruments that can be integrated together with the system under test. Indirect test is then an interesting path to enable cost-effective BIST for mixed-signal systems. This PICS project has the goal of developing reliable and accurate built-in indirect test methods for complex mixed-signal systems. The project is structured into two interconnected research lines: a) Combining causal inference techniques with feature selection anda feature extraction algotirhms for indirect test, and b) Developing a feature-driven strategy for the definition of on-chip test instruments.

I-COOP+ 2016
Hardware Implementation of Cryptographic Protocols Based on Elliptic Curves for Protection of Information Exchange Systems
PI: Santiago Sánchez Solano
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Type: Research project
Reference: COOPA20141
Funding Body: CSIC
Start date: 01/01/2017
End date: 31/12/2018
Funding: 19.000,00 €
Abstract: This project addresses the development and implementation of hardware modules to accelerate the calculation of bilinear pairings on ordinary elliptic curves in the context of cryptographic protocols used in electronic information exchange systems. The factors that affect the computational cost of the calculation of bilinear pairings on elliptic curves can be grouped into four levels: the arithmetic of finite fields; the arithmetic of curve points; the types of pairings; and the integration of pairings in the context of a specific cryptographic protocol. Considering these aspects, appropriate methods for the design of hardware architectures for the operations involved in each level will be identified in order to achieve an efficient implementation in terms of response speed, resources consumption and efficiency of the calculation of the pairings. The results of the work will have direct applicability in the project "Mechanisms of protection in systems of exchange of information" that is developed in the CUJAE and can result of great socioeconomic impact in Cuba.