Spanish National Research Council · University of Seville
esp    ing
IMSE-CNM in Digital.CSIC

Recent publications
Compensation of PVT Variations in ToF Imagers with In-Pixel TDC
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - Sensors, vol. 17, no. 5, 1072, 2017
MDPI    DOI: 10.3390/s17051072    ISSN: 1424-8220    » doi
The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a single-photon avalanche-diode (SPAD) array with an in-pixel time-to-digital converter (TDC) must contemplate system-level aspects that affect its overall performance. This paper provides a detailed analysis of the impact of process parameters, voltage supply, and temperature (PVT) variations on the time bin of the TDC array. Moreover, the design and characterization of a global compensation loop is presented. It is based on a phase locked loop (PLL) that is integrated on-chip. The main building block of the PLL is a voltage-controlled ring-oscillator (VCRO) that is identical to the ones employed for the in-pixel TDCs. The reference voltage that drives the master VCRO is distributed to the voltage control inputs of the slave VCROs such that their multiphase outputs become invariant to PVT changes. These outputs act as time interpolators for the TDCs. Therefore the compensation scheme prevents the time bin of the TDCs from drifting over time due to the aforementioned factors. Moreover, the same scheme is used to program different time resolutions of the direct time-of-flight (ToF) imager aimed at 3D ranging or depth map imaging. Experimental results that validate the analysis are provided as well. The compensation loop proves to be remarkably effective. The spreading of the TDCs time bin is lowered from: (i) 20% down to 2.4% while the temperature ranges from 0 °C to 100 °C; (ii) 27% down to 0.27%, when the voltage supply changes within ±10% of the nominal value; (iii) 5.2 ps to 2 ps standard deviation over 30 sample chips, due to process parameters´ variation.

A Wide Linear Dynamic Range Image Sensor Based on Asynchronous Self-Reset and Tagging of Saturation Events
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - IEEE Journal of Solid-State Circuits, first online, 2017
IEEE    DOI: 10.1109/JSSC.2017.2679058    ISSN: 0018-9200    » doi
We report a high dynamic range (HDR) image sensor with a linear response that overcomes some of the limitations of sensors with pixels with self-reset operation. It operates similar to an active pixel sensor, but its pixels have a novel asynchronous event-based overflow detection mechanism. Whenever the pixel voltages at the integration capacitance reach a programmable threshold, the pixels self-reset and send out asynchronously an event indicating this. At the end of the integration period, the voltage at the integration capacitance is digitized and readout. Combining this information with the number of events fired by each pixel, it is possible to render linear HDR images. Event operation is transparent to the final user. There is no limitation for the number of self-resets of each pixel. The output data format is compatible with frame-based devices. The sensor was fabricated in the AMS 0.18-μm HV technology. A detailed system description and experimental results are provided in this paper. The sensor can render images with an intra-scene dynamic range of up to 130 dB with linear outputs. The pixels' pitch is 25 μm and the sensor power consumption is 58.6 mW.

TFET-based Well Capacity Adjustment in Active Pixel Sensor for Enhanced High Dynamic Range
J. Fernández-Berni, M. Niemier, X.S. Hu, H. Lu, W. Li, P. Fay, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - Electronics Letters, vol.53, no. 9, pp 622-624, 2017
IEEE    DOI: 10.1049/el.2016.4548    ISSN: 0013-5194     » doi
A tunnel field-effect transistor (TFET)-based pixel circuit for well capacity adjustment that does not require subthreshold operation on the part of the reset transistor is presented. In CMOS, this subthreshold operation leads to temporal noise, distortion and fixed pattern noise, becoming a primary limiting performance factor. In the proposed circuit, the asymmetric conduction associated with TFETs is exploited. This property, arising from the inherent physical structure of the device, provides the selective well adjustments during photo-integration which are demanded for achieving high dynamic range. A GaN-based heterojunction TFET has been designed according to the specific requirements for this application.

A switched-capacitor skew-tent map implementation for random number generation
J.L. Valtierra, E. Tlelo-Cuautle and A. Rodriguez-Vazquez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 305-315, 2017
JOHN WILEY & SONS    DOI: 10.1002/cta.2305    ISSN: 0098-9886    » doi
Piecewise linear one-dimensional maps have been proposed as the basis for low-power analog and mixed-signal true random number generators (TRNGs). Recent research has moved towards conceiving maps that operate robustly under the consideration of parameter variations. In this paper, we introduce an oscillator circuit mapping a low-complexity map known as the skew-tent. This oscillator is employed as the basis for a TRNG scheme. Simulation results in TSMC 0.18 μm validate the chaotic oscillator and the randomness of the TRNG scheme is verified with the NIST test suite 800-22.

Guest Editorial 'Secure lightweight crypto-hardware'
A.J. Acosta and T. Addabbo
Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 143-144, 2017
JOHN WILEY & SONS    DOI: 10.1002/cta.2302    ISSN: 0098-9886    » doi
Abstract not avaliable

Incubating terns modify risk-taking according to diurnal variations in egg camouflage and ambient temperature
J.A. Amat, J. Gómez, G. Liñán-Cembrano, M.A. Rendón and C. Ramo
Journal Paper - Behavioral Ecology and Sociobiology, vol. 71, no. 4, 2017
SPRINGER    DOI: 10.1007/s00265-017-2306-4    ISSN: 0340-5443    » doi
Studies of risk-taking by breeding birds have frequently addressed the effect of brood value on the decisions taken by incubating birds when predators approach their nests. However, leaving eggs unattended during predator disturbance may expose embryos to other potentially harmful factors, to which parent birds should respond when making decisions about when to leave or return to their nest. In this study, we show that diurnal changes in flushing behaviour of incubating terns from nests during predator approach were affected by egg camouflage, the terns allowing a closer approach to individual nests when the eggs appeared better camouflaged. Return times to the nests were affected by ambient temperature, with the terns shortening such times at high ambient temperatures, thus diminishing the risk of egg overheating. As a whole, our results show that the decisions of the birds on when to leave or return to their nests depended on shifting payoffs, as a consequence of diurnal variations in both the thermal risks incurred by embryos and egg crypsis. Environmental costs of risk-taking, such as those considered here, should be addressed in studies of risk-taking by breeding birds. This type of study may have implications for our knowledge of cognitive processes that affect risk-taking.

Parametric macromodeling of integrated inductors for RF circuit design
F. Passos, Y. Ye, D. Spina, E. Roca, R. Castro-López, T. Dhaene and F.V. Fernández
Journal Paper - Microwave and Optical Technology Letters, vol. 59, no. 5, pp 1207-1212, 2017
JOHN WILEY & SONS    DOI: 10.1002/mop.30498    ISSN: 1098-2760    » doi
Nowadays, parametric macromodeling techniques are widely used to describe electromagnetic structures. In this contribution, the application of such parametric macromodeling techniques to the design of integrated inductors and radio-frequency circuit design is investigated. In order to allow such different operations, a new modeling methodology is proposed, which improves the modeling accuracy when compared to former techniques. The new methodology is tailored to the unique characteristics of the devices under study. The obtained parametric macromodel is then used in a synthesis methodology and in the design of a voltage controlled oscillator in a 0.35-μm CMOS technology.

In the quest of vision-sensors-on-chip: Pre-processing sensors for data reduction
A. Rodríguez-Vázquez
Conference - IS&T International Symposium on Electronic Imaging 2017
Abstract not available

A CMOS Digital SiPM with Focal-Plane Light-Spot Statistics for DOI Computation
I. Vornicu, F.N. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - IEEE Sensors Journal, vol. 17, no. 3, pp 632-643, 2017
IEEE    DOI: 10.1109/JSEN.2016.2632200    ISSN: 1530-437X     » doi
Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to improve the quality of the positron emission tomography images affected by the parallax error. This paper contemplates the computation of DOI based on the standard deviation of the light distribution. The simulations have been carried out by GAMOS. The design of the proposed digital silicon photomultiplier (d-SiPM) with focal plane detection of the center of mass position and dispersion of the scintillation light is presented. The d-SiPM shares the same off-chip time-to-digital converter such that each pixel can be individually connected to it. A miniature d-SiPM 8×8 single-photon avalanche-diode (SPAD) array has been fabricated as a proof of concept. The SPADs along each row and column are connected through an OR combination technique. It has 256×256μm2 without peripherals circuits and pads. The fill factor is about 11%. The average dark count rate of the mini d-SiPM is of 240 kHz. The average photon detection efficiency is 5% at 480 nm wavelength, room temperature, and 0.9 V excess voltage. The dynamic range is of 96 dB. The sensor array features a time resolution of 212 ps. The photon-timing SNR is 81 dB. The focal plane statistics of the light-spot has been proved as well by measurements.

Black-Box Calibration for ADCs with Hard Nonlinear Errors using a Novel INL-Based Additive Code: A Pipeline ADC Case Study
A.J. Ginés, E.J. Peralías and A. Rueda
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, first online, 2017
IEEE    DOI: 10.1109/TCSI.2017.2662085    ISSN: 1549-8328    » doi
This paper presents a digital nonlinearity calibration technique for ADCs with strong input-output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affecting the ADC's performance. As a solution to this problem, this paper proposes a novel INL-based calibration which incorporates information from the ADC's internal signals to provide a robust estimation of static nonlinear errors for multivalued ADCs. The method is fully generalizable and can be applied to any existing design as long as there is access to internal digital signals. In pipeline or subranging ADCs, this implies access to partial subcodes before digital correction; for algorithmic or SAR ADCs, conversion bit/bits per cycle are used. As a proof-of-concept demonstrator, the experimental results for a 1.2 V 23 mW 130 nm-CMOS pipeline ADC with a SINAD of 58.4 dBc (in nominal conditions without calibration) is considered. In a stressed situation with 0.95 V of supply, the ADC has SINAD values of 47.8 dBc and 56.1 dBc, respectively, before and after calibration (total power consumption, including the calibration logic, being 15.4 mW).

Scopus access Wok access