IMSE Publications

Recent publications

Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
abstract      doi      

This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.

A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing
M. Srivastava, A. Ferro, A. Sidun, P. Cantillon-Murphy, Daniel O’Hare, K. O’Donoghue and J.M. de la Rosa
Journal Paper · IEEE Open Journal of Circuits and Systems (Volume 5), 2024
IEEE    ISSN: 2644-1225
abstract      doi      

This work presents a small-area 2nd-order continuous-time ΔΣ Modulator (CTΔΣM) with a single low dropout regulator (LDO) serving as both the power supply for the CTΔΣM and reference voltage buffer. The CTΔΣM is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and Vref for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CTΔΣM consumes 300 μW of power when clocked at 10.24 MHz. The CTΔΣM achieves a state-of-the-art area of 0.07 mm.

A Control-Bounded Quadrature Leapfrog ADC
H. Malmberg, F. Feyling and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, 2024
IEEE    ISSN: 1549-8328
abstract      doi      

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated. A band-pass analog-to-digital converter is considered as an application and case study. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations on several filter orders, center frequencies, and oversampling ratios. Additionally, we consider an op-amp circuit realization where the effects of first-order op-amp non-idealities are shown. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.

Reliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of aging
A. Santana-Andreo, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · AEU - International Journal of Electronics and Communications, Volume 176, 155147, 2024
ELSEVIER    ISSN: 1434-8411
abstract      doi      

Physical Unclonable Functions (PUFs) have gained attention as a lightweight hardware security primitive. In particular, the SRAM-based PUF uses the unpredictable power-up value of the cells within an SRAM. Although these values should ideally be always the same within each SRAM to accomplish a correct PUF operation, this is often not the case, especially when factors like circuit aging are considered. While certain studies explore the effects of aging on SRAM PUFs, they often simplify the analysis. For instance, some studies assume that only Bias Temperature Instability (BTI) contributes to circuit degradation while others evaluate the overall degradation without accounting for the stochastic effects of aging on each individual cell. In this work, we first perform a detailed characterization of the nature of aging in SRAM PUFs, demonstrating that the impact of Non-Conductive Hot-Carrier Injection cannot be neglected. We also show that different cells degrade differently, highlighting the importance of accounting for the stochasticity of aging. After that, a method based on the Data Retention Voltage metric to select the cells with the most stable power-up response is introduced. Using these cells to generate the PUF identifier will result in a more stable response, and thus a better PUF performance.

On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators
P. Díaz-Lobo, G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
IEEE    ISSN: 1549-8328
abstract      doi      

This paper presents a high-level synthesis methodology for Sigma-Delta Modulators (ΣΔ Ms) that combines behavioral modeling and simulation for performance evaluation, and Artificial Neural Networks (ANNs) to generate high-level designs variables for the required specifications. To this end, comprehensive datasets made up of design variables and performance metrics, generated from accurate behavioral simulations of different kinds of ΣΔ Ms, are used to allow the ANN to learn the complex relationships between design-variables and specifications. Several representative case studies are considered, including single-loop and cascade architectures with single-bit and multi-bit quantization, as well as both Switched-Capacitor (SC) and Continuous-Time (CT) circuit techniques. The proposed solution works in two steps. First, for a given set of specifications, a trained classifier proposes one of the available ΣΔ M architectures in the dataset. Second, for the proposed architecture, a Regression-type Neural Network (RNN) infers the design variables required to produce the requested specifications. A comparison with other optimization methods - such as genetic algorithms and gradient descent - is discussed, demonstrating that the presented approach yields to more efficient design solutions in terms of performance metrics and CPU time.

On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators
J. Gorji, S. Pavan and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
IEEE    ISSN: 1549-8328
abstract      doi      

This paper presents a new architecture for bandpass delta-sigma modulators (BP-ΔΣMs) featuring finite impulse response (FIR) filters in the feedback path. The effectiveness of FIR feedback in lowpass delta-sigma modulators (LP-ΔΣMs) has been well-established in improving loop-filter linearity and robustness to clock jitter. Building upon these findings, we explore the application of bandpass FIR filters in single-bit BP-ΔΣMs. By contrast to conventional BP-ΔΣMs, the proposed technique significantly reduces out-of-band quantization error contents in the feedback signal. This approach is applicable to both discrete-time and continuous-time implementations. Further, we show that performance does not improve by increasing the number of FIR taps beyond a certain point. However, we can enhance filtering performance by employing non-equal coefficients within the filter. To validate the efficacy of the presented approach, the paper includes electrical simulation of a 4th-order active-RC BP-ΔΣM.

Experimental Demonstration of Coupled Differential Oscillator Networks for Versatile Applications
M. Jiménez, J. Núñez, J. Shamsi, B. Linares-Barranco and M.J. Avedillo
Journal Paper · Frontiers in Neuroscience, Neuromorphic Engineering, vol. 17, 2023
FRONTIERS    ISSN: 1662-453X
abstract      doi      

Oscillatory Neural Networks (ONNs) exhibit a high potential for energy-efficient computing. In ONNs, neurons are implemented with oscillators and synapses with resistive and/or capacitive coupling between pairs of oscillators. Computing is carried out on the basis of the rich, complex, nonlinear synchronization dynamics of a system of coupled oscillators. The exploited synchronization phenomena in ONNs are an example of fully parallel collective computing.A fast system´s convergence to stable states, which correspond to the desired processed information, enables an energy-efficient solution if small area and low-power oscillators are used, specifically, when they are built on the basis of the hysteresis exhibited by phase-transition materials such as VO2. In recent years, there have been numerous studies on ONNs using VO2. Most of them report simulation results. Although in some cases experimental results are also shown, they don´t implement the design techniques that other works on electrical simulations report that allow to improve the behavior of the ONNs.Experimental validation of these approaches is necessary. Therefore, in this work, we describe an ONN realized in a commercial CMOS technology in which the oscillators are built using a circuit that we have developed to emulate the VO2 device. The purpose is to be able to study in depth the synchronization dynamics of relaxation oscillators similar to those that can be performed with VO2 devices. The fabricated circuit is very flexible. It allows programming the synapses to implement different ONNs, calibrating the frequency of the oscillators or controlling their initialization. It uses differential oscillators and resistive synapses equivalent to the use of memristors. In this article, the designed and fabricated circuit is described in detail and experimental results are shown. Specifically, its satisfactory operation as an associative memory is demonstrated. The experiments carried out allow us to conclude that the ONN must be operated according to the type of computational task to be solved, and guidelines are extracted in this regard.

Learning Algorithms for Oscillatory Neural Networks as Associative Memory for Pattern Recognition
M. Jiménez, M.J. Avedillo, B. Linares-Barranco and J. Núñez
Journal Paper · Frontiers in Neuroscience, Neuromorphic Engineering, vol. 17, 2023
FRONTIERS    ISSN: 1662-453X
abstract      doi      

Alternative paradigms to the von Neumann computing scheme are currently arousing huge interest. Oscillatory neural networks (ONNs) using emerging phase-change materials like VO2 constitute an energy-efficient, massively parallel, brain-inspired, in-memory computing approach. The encoding of information in the phase pattern of frequency-locked, weakly coupled oscillators makes it possible to exploit their rich nonlinear dynamics and their synchronization phenomena for computing. A single fully connected ONN layer can implement an auto-associative memory comparable to that of a Hopfield network, hence Hebbian learning rule is the most widely adopted method for configuring ONNs for such applications, despite its well-known limitations. An extensive amount of literature is available about learning in Hopfield networks, with information regarding many different learning algorithms that perform better than the Hebbian rule. However, not all of these algorithms are useful for ONN training due to the constraints imposed by their physical implementation. This paper evaluates different learning methods with respect to their suitability for ONNs. It proposes a new approach, which is compared against previous works. The proposed method has been shown to produce competitive results in terms of pattern recognition accuracy with reduced precision in synaptic weights, and to be suitable for online learning.

Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices
J. Núñez, M.J. Avedillo and M. Jiménez
Conference · International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2023

Abstract not available

Energy-efficient Brain-inspired Oscillatory Neural Networks using Phase-Transition Material
M. Jiménez, B. Linares-Barranco, M.J. Avedillo and J. Núñez
Conference · Workshop on Deep Learning meets Neuromorphic Hardware. European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases ECML PKDD 2023

Oscillatory Neural Network (ONN) is a promising neuromorphic computing approach which uses networks of frequency-locked coupled oscillators, and their inherent parallel synchronization to compute. Also, ONN can be im-plemented using phase-transition materials using nano-scale area, low voltage amplitude and reduced power consumption, being an efficient way to im-plement oscillator-based computing. In state-of-theart, ONN is built with a fully-connected architecture, with coupling configured depending on the tar-get application. Its most widespread use has been as associative memory, but recently it is gathering interest as a solver for non-deterministic polynomial time problem (NP-hard). This is performed on the basis of encoding the NP-problem in the Ising model, so ONN operates as an Ising machine. ONN state naturally evolves to minimum points in the Hamiltonian energy function re-sorting to its rich non-lineal dynamics, supposing a promising paradigm of fast, low-power, parallel computation.
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