IMSE Publications

Recent publications

High-Level Design of Sigma-Delta Modulators using Artificial Neural Networks
P. Díaz-Lobo and J.M. de la Rosa
Journal Paper · IEEE International Symposium on Circuits and Systems ISCAS 2023
IEEE    ISSN: 2158-1525
abstract      doi      

This paper analyses the use of Artificial Neural Networks (ANNs) for the high-level synthesis and design of Sigma-Delta Modulators (ΣΔMs) . The presented methodology is based on training ANNs to identify optimum design patterns, so that they can learn to predict the best set of design variables for a given set of specifications. This strategy has been successfully applied in prior works to design basic analog building blocks, and it is explored in this work to automate the high-level sizing of ΣΔMs . Several ΣΔM case studies, which include both single-loop and cascade topologies as well as Switched-Capacitor (SC) and Continuous-Time (CT) circuit techniques are shown. The effect of ANN hyperparameters - such as the number of layers, neurons per layer, batch size, number of epochs, etc. - is analyzed in order to find out the best ANN architecture that finds an optimum design with less computational resources. A comparison with other optimization methods - such as genetic algorithms and gradient descent - is shown, demonstrating that the presented approach yields to more efficient design solutions in terms of performance metrics, power consumption and CPU time 1 1 This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future, and by ’’Junta de Andalucía’’ under Grant P20-00599.

Bandpass ΔΣ Modulators with FIR Feedback
J. Gorji, S. Pavan and J.M. de la Rosa
Journal Paper · IEEE International Symposium on Circuits and Systems ISCAS 2023
IEEE    ISSN: 2158-1525
abstract      doi      

This paper investigates finite impulse response (FIR) feedback in bandpass delta-sigma modulators (BP- ΔΣMs ). FIR feedback in lowpass delta-sigma modulators (LP- ΔΣMs ) improves loop filter linearity and reduces the sensitivity of the modulator to clock jitter. We show that similar benefits can be obtained in a BP- ΔΣM if the FIR filter in the feedback path is made a bandpass one 1 1 This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future, and by ’’Junta de Andalucía’’ under Grant P20-00599 and in part by the Center of Excellence in RF, Analog and Mixed-Signal ICs (CERAMIC), IIT Madras..

Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems
P.I. Enwere, E. Cervantes-Requena, L.A. Camuñas-Mesa and J.M. de la Rosa
Journal Paper · Integration, vol. 93, 2023
ELSEVIER    ISSN: 0167-9260
abstract      doi      

This paper analyzes the use of Artificial Neural Networks (ANNs) to identify and predict the evolution of vacant portions or frequency holes of the radio spectrum in Cognitive Radio (CR) systems. The operating frequency of CR transceivers can be modified over the air according to the information provided by the ANN in order to establish the communication in the least occupied band. To this end, ANNs are trained with time-series datasets sensed from the electromagnetic environment. Several network architectures are considered in the study, including Convolutional Neural Networks (CNNs), Long Short-Term Memory (LSTM) networks and hybrid combinations of them. These ANNs are modeled and compared in terms of their complexity, speed and accuracy of the prediction. Both simulations and experimental results are shown to validate the approach presented in this work.

A Low-Latency, Low-Power CMOS Sun Sensor for Attitude Calculation Using Photovoltaic Regime and On-Chip Centroid Computation
R. Gomez-Merchan, J. A. Leñero-Bardallo, M. López-Carmona and Á. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Instrumentation and Measurement, 2023
IEEE    ISSN: 0018-9456
abstract      doi      

The demand for sun sensors has skyrocketed in the last years due to the huge expected deployment of satellites associated with the New Space concept. Sun sensors compute the position of the sun relative to the observer and play a crucial role in navigation systems. However, the sensor itself and the associated electronics must be able to operate in harsh environments. Thus, reducing hardware and post-processing resources improves the robustness of the system. Furthermore, reducing power consumption increases the lifetime of microsatellites with a limited power budget. This work describes the design, implementation, and characterization of a proof-of-concept prototype of a low-power, high-speed sun sensor architecture. The proposed sensor uses photodiodes working in the photovoltaic regime and event-driven vision concepts to overcome the limitations of conventional digital sun sensors in terms of latency, data throughput, and power consumption. The temporal resolution of the prototype is in the microsecond range with an average power consumption lower than 100μW . Experimental results are discussed and compared with the state-of-the-art.

A 12-bit Low-input Capacitance SAR ADCwith a Rail-to-Rail Comparator
N. Shahpari, M. Habibi, P. Malcovati and J.M. de la Rosa
Journal Paper · IEEE Access, 2023
IEEE    ISSN: 2169-3536
abstract      doi      

The input capacitance of the SAR ADC is considered as a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance SAR based on separated DAC and sample-and-hold blocks (SB) structure is proposed. The SB structure suffers from variation of the input common-mode voltage of the comparator causing nonlinear input-referred offset and kickback noise. Here, a closed loop low-power rail-to-rail offset cancellation technique for the comparator based on the body voltage tuning is proposed. In order to stabilize the closed loop structure, the open loop gain is controlled by adapting the gain of the preamplifier. Using this structure, the rail-to-rail offset is kept lower than 110 μV and the overall power of the comparator is 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at the input the comparator to decrease the common-mode dependent kickback noise error to less than 1 LSB. The bootstrapped switch’s controlling signal is also modified to achieve less than 1 LSB error and 18.9% less power consumption. The proposed ADC is designed in standard 180 nm CMOS technology with a 1.8 V supply voltage and shrinking the input capacitance to 2 pF, which leads to 41 nW power consumption in the input voltage supply. Electrical simulations including PVT, Monte-Carlo, and post-layout parasitic extraction were run to ensure the effectiveness of the approach. The ADC features an ENOB of 11.1-bit and the sampling rate of 1 MHz with a power consumption of 117.9 μW including the input power supply which are competitive with the state-of-the-art, and demonstrate the virtue of the proposed approach.

Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 7, no.2, article 29, 2023
MDPI    ISSN: 2410-387X
abstract      doi      

The advent of quantum computing with high processing capabilities will enable brute force attacks in short periods of time, threatening current secure communication channels. To mitigate this situation, post-quantum cryptography (PQC) algorithms have emerged. Among the algorithms evaluated by NIST in the third round of its PQC contest was the NTRU cryptosystem. The main drawback of this algorithm is the enormous amount of time required for the multiplication of polynomials in both the encryption and decryption processes. Therefore, the strategy of speeding up this algorithm using hardware/software co-design techniques where this operation is executed on specific hardware arises. Using these techniques, this work focuses on the acceleration of polynomial multiplication in the encryption process for resource-constrained devices. For this purpose, several hardware multiplications are analyzed following different strategies, taking into account the fact that there are no possible timing information leaks and that the available resources are optimized as much as possible. The designed multiplier is encapsulated as a fully reusable and parametrizable IP module with standard AXI4-Stream interconnection buses, which makes it easy to integrate into embedded systems implemented on programmable devices from different manufacturers. Depending on the resource constraints imposed, accelerations of up to 30-45 times with respect to the software-level multiplication runtime can be achieved using dedicated hardware, with a device occupancy of around 5%.

On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 23, no. 8, article 4070, 2023
MDPI    ISSN: 1424-8220
abstract      doi      

The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive set of on-line tests to obtain the metrics that determine its quality in terms of uniqueness, reliability, and entropy characteristics. The results obtained prove that the proposed module is a suitable candidate for various security applications. As an example, an implementation that uses less than 5% of the resources of a low-cost programmable device is capable of obfuscating and recovering 512-bit cryptographic keys with virtually zero error rate.

A Pipelining-Based Heterogeneous Scheduling and Energy-Throughput Optimization Scheme for CNNs Leveraging Apache TVM
D. Velasco-Montero, B. Goossens, J. Fernández-Berni, Á. Rodríguez-Vázquez and W. Philips
Journal Paper · IEEE Access, 2023
IEEE    ISSN: 2169-3536
abstract      doi      

Extracting information of interest from continuous video streams is a strongly demanded computer vision task. For the realization of this task at the edge using the current de-facto standard approach, i.e., deep learning, it is critical to optimize key performance metrics such as throughput and energy consumption according to prescribed application requirements. This allows achieving timely decision-making while extending the battery lifetime as much as possible. In this context, we propose a method to boost neural-network performance based on a co-execution strategy that exploits hardware heterogeneity on edge platforms. The enabling tool is Apache TVM, a highly efficient machine-learning compiler compatible with a diversity of hardware back-ends. The proposed approach solves the problem of network partitioning and distributes the workloads to make concurrent use of all the processors available on the board following a pipeline scheme. We conducted experiments on various popular CNNs compiled with TVM on the Jetson TX2 platform. The experimental results based on measurements show a significant improvement in throughput with respect to a single-processor execution, ranging from 14% to 150% over all tested networks. Power-efficient configurations were also identified, accomplishing energy reductions above 10%.

Band-Pass Sigma-Delta Modulation: The Path towards RF-to-Digital Conversion in Software-Defined Radio
J.M. de la Rosa
Journal Paper · Chips, vol. 2 no. 1, articles 44-69, 2023
MDPI    ISSN: 2674-0729
abstract      doi      

This paper reviews the state of the art on bandpass sigma-delta modulators (BP-sigma-deltaMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-sigma-deltaM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals.

Ultra-High-Resistance Pseudo-Resistors with Small Variations in a Wide Symmetrical Input Voltage Swing
F. Karami-Horestani and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE    ISSN: 1549-7747
abstract      doi      

This paper presents a new strategy and circuit configuration composed of serially-connected PMOS devices operating in the subthreshold region for implementing ultra-highvalue resistors required in very low-frequency active-RC filters and bio-amplifiers. Depending on the application, signal bandwidth for instance in bio-amplifiers may vary from a few mHz up to a maximum of 10 kHz. Three different resistor structures are proposed to achieve ultra-high resistance. While ranging in the order of several TY, the proposed ultra-high-resistance pseudoresistors occupy a small on-chip silicon area, which is one of the main issues in the design of analog front-end circuits in ultra-low power implantable biomedical microsystems. In addition, these ultra-high-value resistors lead to the use of a small capacitance to create a very small cut-off frequency. Therefore, the large area to implement capacitances is also considerably reduced. The proposed resistor structures have very small variations about 7% and 12% in a wide input voltage range (-0.5 V +0.5 V), thus significantly improving the total harmonic distortion of bioamplifiers and the analog front-end of the system. Simulation results of different circuits designed in a 180nm CMOS technology, are shown to demonstrate the advantages of the proposed ultra-high-resistance pseudo-resistors.
  • Journals574
  • Conferences1154
  • Books30
  • Book chapters81
  • Others9
  • 202315
  • 202278
  • 202183
  • 2020103
  • 201977
  • 2018106
  • 2017111
  • 2016104
  • 2015111
  • 2014104
  • 201380
  • 2012108
  • 2011102
  • 2010120
  • 200977
  • 200867
  • 200770
  • 200665
  • 200578
  • 200468
  • 200362
  • 200259