Spanish National Research Council · University of Seville
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Editorial: A Year Ahead Full of New Initiatives
J.M. de la Rosa
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 1, pp 4-4, 2021
IEEE    DOI: 10.1109/TCSII.2020.3041170    ISSN: 1549-7747    » doi
First of all, I hope that you, your families and all yours remain healthy and safe. The thoughts of the Editorial Board (EB) of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS (TCAS-II) and all the staff from IEEE are with those who are facing health problems and have suffered the consequences of the COVID-19 pandemic. The first year of my term as Editor-in-Chief (EiC) of IEEE TCAS-II has run under this terrible situation which has changed the lifestyle of all of us. We have seen how almost all social and professional events, including of course most IEEE conferences, have been either cancelled or running virtual, what has precluded us from enjoying together with our friends and colleagues as we had always done. The New Year 2021 comes full of hope for humankind with the development of several vaccines and more effective drugs to fight against the coronavirus SARS-Cov-2, and I am firmly convinced that sooner than later we will be able to recover our way of living.

An efficient transformer modeling approach for mm-wave circuit design
F. Passos, E. Roca, J. Sieiro, R. Castro-Lopez and F.V. Fernandez
Journal Paper - AEU - International Journal of Electronics and Communications, vol. 128, article 153496, 2021
ELSEVIER    DOI: 10.1016/j.aeue.2020.153496    ISSN: 1434-8411    » doi
In this paper, a Gaussian-process surrogate modeling methodology is used to accurately and efficiently model transformers, which are still a bottleneck in radio-frequency and millimeter-wave circuit design. The proposed model is useful for a wide range of frequencies from DC up to the millimeter-wave range (over 100 GHz). The technique is statistically validated against full-wave electromagnetic simulations. The efficient model evaluation enables its exploitation in iterative user-driven design approaches, as well as automated design exploration involving thousands of simulations. As experimental results, the model is used in several scenarios, such as the design of an inter-stage amplifier operating at 60 GHz, where the model assisted in the simulation of the transformers and baluns used, and the design of individual transformers and a matching network.

A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-based CT MASH ΣΔ Modulator
M. Honarparvar, J.M. de la Rosa and M. Sawan
Conference - International Symposium on Integrated Circuits and Systems ISICAS 2020
We present in this brief a novel multi-stage noise-shaping (MASH) 3-1 continuous-time (CT) delta-sigma modulator ( Σ δM ) with gated ring oscillator based quantizers (GROQs) in both stages of the cascade. The use of GROQs increases the linearity performance with respect to the conventional voltage controlled oscillator based quantizers (VCOQs) and allows a more robust extraction of the front-end stage quantization error in the time domain, thus making the proposed architecture more suitable to implement high-order expandable scaling-friendly MASH Σ δ Ms, in which the back-end stages are implemented by mostly-digital GRO-based time-to-digital converters (TDCs). The circuit has been fabricated in a 65-nm CMOS technology with 1-V supply voltage, and it operates at 640-MHz sampling frequency to digitize 10-MHz signals. To the best of the authors‚ knowledge, this is the first reported experimental validation of a GRO-based CT MASH Σ δM , featuring a 79.8-dB signal to noise ratio (SNR) at -2.2-dBFS, a 77.3-dB signal to (noise + distortion) ratio (SNDR) at -4-dBFS and a dynamic range (DR) of 81.7 dB, with a power consumption of 12-mW. These metrics demonstrate state-of-the-art performance with a DR-based Schreier FOM of 170.9 dB.

Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions based on the Matrix Exponential
J.A. Serrano, A.J. Gines and E. Peralías
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
This paper presents a new simulation method for fast evaluation of non-linear circuits. The proposed approach solves the non-linear ordinary differential equation (ODE) set of the system using a semi-analytical solution based on the matrix exponential. The method is fully general and suitable for different circuits, including switched-capacitor (SC) architectures, analog to digital converters (Pipeline, SAR, Sigma-Delta ADCs) or digital to analog converters. For illustration purpose in this paper, an analog signal processing front-end for discrete-time data acquisition system is considered as case study. The circuit comprises a Flip-Around Sample&Hold followed by a Programmable Gain Amplifier (PGA), based on a Correlated Double-Sampling amplifier, and a back-end ADC. The model includes non-linearity associated to switches, capacitive parasitics, finite nonlinear DC-gain and non-linear settling behavior including slew-rate. Comparison with traditional ODE numerical solvers shows a reduction of the computation time in almost two orders of magnitude with negligible difference in terms of accuracy.

Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages-coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.

Auto-Calibrated Ring Oscillator TRNG Based on Jitter Accumulation
M.A. Prada-Delgado, C. Martínez-Gómez and I. Baturone
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
This paper provides a mathematical model that describes how deterministic and Gaussian jitter of an oscillating signal accumulated during a time interval are related to the bits of the binary-coded count value of the oscillations. The model is employed to propose a robust TRNG that has a simple interface (an initialization signal as input and the random bits as output) and that features auto-calibration to certify high entropy of the raw bits provided as well as to work at the highest throughput allowed by the available local Gaussian noise. The mathematical analysis is confirmed with experimental results of ring oscillator (RO) TRNGs described in VHDL and implemented in the programmable logic of Zynq family Xilinx FPGAs, using either another RO or the clock of the FPGA board to control the time interval of oscillations.

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers
F E. Potestad-Ordóñez, E. Tena-Sánchez, R. Chaves, M. Valencia-Barrero, A.J. Acosta-Jiménez and C.J. Jiménez-Fernández
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to minimize this type of vulnerabilities, several mechanisms have been proposed to detect this type of attacks. However, these mechanisms can have a significant cost or not adequately cover the implementations against fault attacks. In this paper a novel approach is proposed, consisting in generating the signatures of the internal state using a Hamming code. This allows to cover a larger amount of faults allowing to detect even or odd bit changes, as well as multi-bit and multi-byte changes, the ones that make ciphers more vulnerable to DFA attacks. As case of study, this approach has been applied to the Advanced Encryption Standard (AES) block cipher implemented on FPGA using T-boxes. The results suggest a higher fault coverage with an overhead of 16% of resource consumption and without any penalty in the frequency degradation.

Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy
A. Lopez-Angulo, A. Gines and E. Peralias
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can occur due to saturation of the redundancy intervals associated with implemented weights, eventually leading to a faulty behavior even with lower effective resolution than the case without calibration. To overcome this limitation, this work proposes a foreground technique which reuses the least-significant bit (LSB) capacitors in the array in a design with redundancy for offset compensation. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit SAR ADC case study with 3 redundant bits.

Low Order Wideband Multiplierless Comb Compensator
G.J. Dolecek, L. Camuñas-Mesa and J.M. de la Rosa
Conference - IEEE Midwest Symposium on Circuits and Systems MWSCAS 2020
This paper presents a novel multiplierless wideband comb compensator with a low absolute value of passband deviation and a low number of adders. The number of adders depends on the number of cascaded combs, and it is between 5 and 9. Similarly, the absolute value of the passband deviation of the compensated comb depends also on the number of cascaded combs and varies from 0.06 dB (single comb) to 0.11 dB (six cascaded combs). The magnitude response of the compensator is synthesized using sinewave functions resulting in a fourth-order compensator filter. The comparisons with some recent methods from literature are presented to show the benefits of the proposed approach.

Auxiliary Pulse-Extender and Current-Attenuator Circuits for Flexible Interaction with Memristive Crossbars in SNNs
J. Ahmadi-Farsani, B. Linares-Barranco and T. Serrano-Gotarredona
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2020
This paper presents a pulse-extender, a delay-element, and a current-attenuator as auxiliary circuits that make it possible to have flexible interaction with memristor crossbars in spiking neural networks. In the presynaptic part, the pulse-extender makes the inputs compatible with the pulsed-characterization of memristors. In the post-synaptic part, the current attenuator relaxes the system in terms of requiring low-offset amplifiers and also makes it possible to design neurons with small membrane capacitors. The circuits are fabricated in a CMOS 180nm technology. The measurements verify that these blocks play an important role in reaching an SNN with real-time performance.

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