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Real-time temporal frequency detection in FPGA using event-based vision sensor
S. Hoseini and B. Linares-Barranco
Conference - IEEE International Conference on Intelligent Computer Communication and Processing ICCP 2018
[abstract]
A dynamic vision sensor (DVS) is a new type of vision sensor in which each pixel acts as a motion sensor and generates highly time-accurate events when it detects movement in the scene. The high temporal precision of these types of vision sensors allows the extraction of different low-level temporal features, which is not possible when using a frame-based camera. Hierarchical vision-processing systems use low-level features to recognize a higher level of abstraction. One of the lowlevel features that can be extracted with DVS is the temporal frequency. This feature can be used along with other visual features for more accurate object recognition when the object has rotating parts, such as a quadcopter. This work is an extension of our previous work, wherein we proposed an algorithm to extract this temporal low-level feature by using a DVS. In this work, we proposed a digital circuit with a small footprint to extract the frequency of rotating objects in real time with very low latency. We have synthesized the digital circuit in Spartan-6 field-programmable gate array (FPGA) and also in UMC 180-nm technology to measure the performance, power consumption, and occupied area. MATLAB and Verilog codes for this work are available for academic purposes upon request.

Digital hardware realization of a novel adaptive ink drop spread operator and its application in modeling and classification and on-chip training
S. Haghzad Klidbary, S. Bagheri Shouraki and B. Linares-Barranco
Journal Paper - International Journal of Machine Learning and Cybernetics, first online, 2018
SPRINGER    DOI: 10.1007/s13042-018-0890-x    ISSN: 1868-8071    » doi
[abstract]
In artificial intelligence (AI), proposing an efficient algorithm with an appropriate hardware implementation has always been a challenge because of the well-accepted fact that AI hardware implementations should ideally be comparable to biological systems in terms of hardware area. Active learning method (ALM) is a fuzzy learning algorithm inspired by human brain computations. Unlike traditional algorithms, which employ complicated computations, ALM tries to model human brain computations using qualitative and behavioral descriptions of the problem. The main computational engine in ALM is the ink drop spread (IDS) operator, but this operator imposes high memory requirements and computational costs, making the ALM algorithm and its hardware implementation unsuitable for some of the applications. This paper proposes an adaptive alternative method for implementing the IDS operator; a method which results in a marked reduction in the algorithm´s computational complexity and in the amount of memory required and hardware. To check its validity and performance, the method was used to carry out modeling and pattern classification tasks. This paper used challenging and real-world datasets and compared with well-known algorithms (adaptive neuro-fuzzy inference system and multi-layer perceptron) in software simulation and hardware implementation. Compared to traditional implementations of the ALM algorithm and other learning algorithms, the proposed FPGA implementation offers higher speed, less hardware, and improved performance, thus facilitating real-time application. Our ultimate goal in this paper was to present a hardware implementation with an on-chip training that allows it to adapt to its environment without dependency on the host system (on-chip learning).

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
J. Diaz-Fortuny, J. Martin-Martines, R. Rodriguez, R. Castro-Lopez, E. Roca, X. Aragones, E. Barajas, D. Mateo, F.V. Fernandez and M. Nafria
Journal Paper - IEEE Journal of Solid-State Circuits, first online, 2018
IEEE    DOI: 10.1109/JSSC.2018.2881923    ISSN: 0018-9200    » doi
[abstract]
Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm2.

Color Tone-Mapping Circuit for a Focal-Plane Implementation
G.M. Nunes, F.D.V.R. Oliveira, J.G.R.C. Gomes, A. Petraglia, J. Fernandez-Berni, R. Carmona-Galan and A. Rodriguez-Vazquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
In this article, we present a review of the driving principles and parameters of a previously reported focal-plane tone-mapping operator. We then extend it in order to include color information processing. The signal processing operations required for handling color images are white balance and demosaicing. Neither white balance nor demosaicing are carried out in the focal plane, in order to avoid increasing circuit size and complexity. Since, in this case, white balance is carried out after tone mapping, multiplication of red and blue channels by constant gains may lead to wrong color results. An alternative approach is proposed, in which different gains are assigned for every red and blue pixel of the matrix. Because of the introduction of color, a modification in the original circuit is proposed, which affects the integration time of red and blue pixels. This modification leads to a reduction in the number of photodiodes required in the pixel array, and hence to a reduction of the sensing circuit area. The results produced by the operator are compared to those obtained from two other digital tone-mapping operators.

Live Demonstration: A Miniaturized Two-Axis Low Latency and Low-Power Sun Sensor for Attitude Determination of Sounding Rockets
L. Farian, J.A. Lenero-Bardallo and P. Hafliger
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
This demo shows a first prototype two-axis miniaturized spiking sun sensor. The device is composed of spiking pixels, and uses a novel Time-to-First-n-Spikes with time-out readout mode to reduce bandwidth consumption and post-processing computation. Due to on-chip processing, and compressing the angle information, the sensor produces much less data and is much faster than digital sensors. Its response latency is 88 µW, and average power consumption is 6.3 µW. An integrated circuit with core electronics was fabricated in the AMS 0.35 µm CMOS image sensor process, and was integrated inside a very small QFN64 package with micro-optics on top.

Results of 'iCaVeats', a project on the integration of architectures and components for embedded vision
R. Carmona-Galán, J. Fernández-Berni, A. Rodríguez-Vázquez, P. López-Martínez, V.M. Brea-Sánchez, D. Cabello-Ferrer, G. Domenech-Asensi, R. Ruiz-Merino and J. Zapata-Pérez
Conference - ACM International Conference on Distributed Smart Cameras ICDSC 2018
[abstract]
iCaveats is a Project on the integration of components and architectures for embedded vision in transport and security applications. A compact and efficient implementation of autonomous vision systems is difficult to be accomplished by using the conventional image processing chain. In this project we have targeted alternative approaches, that exploit the inherent parallelism in the visual stimulus, and hierarchical multilevel optimization. A set of demos showcase the advances at sensor level, in adapted architectures for signal processing and in power management and energy harvesting.

On the characterization of light sources irradiation profiles with an HDR image sensor
J.A. Leñero-Bardallo, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - ACM International Conference on Distributed Smart Cameras ICDSC 2018
[abstract]
We demonstrate how light emissions of very bright light sources can be rendered with an HDR image sensor with linear operation. We showcase the device usefulness to study transient variations of very high illumination levels and to determine the irradiance profile of light sources. The sensor can track transient illumination changes at video rates, preserving details of darker regions within the visual scene.

CMOS-SPAD camera prototype for single-sensor 2D/3D imaging
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - ACM International Conference on Distributed Smart Cameras ICDSC 2018
[abstract]
One of the research lines explored in project 'iCaveats' has been the combined capture of 2D and 3D visual information. With the objective of power-efficient feature learning/extraction, combined 2D/3D imaging is a useful tool to work on a lightweight but rich description of the scene. Single-sensor capture of both modalities is a potential improvement in cost and efficiency. In this demo, we present the performance and features of a CMOS-SPAD camera prototype that realizes photon counting and direct time-of-flight (d-ToF). The central elements of the camera module are a 64x64 SPAD imager and a FPGA board for real time histograming and image reconstruction at 1kfps.

Optimization and CMOS design of chaotic oscillators robust to PVT variations
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, J.M. Muñoz-Pacheco, L.G. de la Fraga, C. Sanchez-Lopez and F.V.Fernandez-Fernandez
Journal Paper - Integration, first online, 2018
ELSEVIER    DOI: 10.1016/j.vlsi.2018.10.010    ISSN: 0167-9260    » doi
[abstract]
Edward Lorenz was an early pioneer of the chaos theory. He discovered that small changes in initial conditions produce large changes in long-term outcome, and introduced a chaotic attractor already known as Lorenz chaotic oscillator, which produces a butterfly-like behavior. This and all kinds of continuous-time chaotic oscillators can be simulated with different numerical methods. However, a bad choice of the step size and/or parameters of the mathematical models can produce errors or even mitigate the chaotic behavior. These issues are related to the main property of chaotic oscillators, the high sensitivity to the initial conditions, which is quantified by evaluating the maximum Lyapunov exponent (MLE). The Lorenz and other representative oscillators like Lü, Chua's circuit and Rössler have been implemented using different discrete electronic devices and few ones with integrated circuits (IC) using CMOS technologies. Designing CMOS chaotic oscillators is challenging because a very small variation in their parameters from their mathematical models or in the sizes of the MOS transistors may suppress the chaotic behavior. This article describes how to perform a successful simulation and optimization, and how to synthesize the mathematical models using CMOS technology. The application of metaheuristics to optimize MLE by varying the parameters of the oscillators, and the optimization of the CMOS IC design to guarantee robustness to process, voltage and temperature (PVT) variations, are discussed. Finally, we discuss issues on the application of chaos generators in random number generators, robotics and chaotic secure communication systems.

PVT-robust CMOS programmable chaotic oscillator: Synchronization of two 7-scroll attractors
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, C. Sanchez-Lopez and F.V. Fernandez-Fernandez
Journal Paper - Electronics, vol. 7, no. 10, article 252, 2018
MDPI    DOI: 10.3390/electronics7100252    ISSN: 2079-9292    » doi
[abstract]
Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2-7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35 μm CMOS technology. Post-layout and process-voltage-temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master-slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.

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