Recent publications
Harvesting random telegraph noise for true random number generation
F.J. Rubio-Barbero, F. de los Santos-Prieto, R. Castro-López, E. Roca and F.V. Fernández
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 196, June 2025
AEU
abstract
doi
At first glance, Random Telegraph Noise (RTN) in deeply scaled CMOS transistors may seem like a reliability nuisance. Yet, behind the discrete trapping-and-detrapping events lurks a potent source of hardware entropy. In this paper, we harness RTN to build a dual-purpose security module that serves as both a Physical Unclonable Function (PUF) and a True Random Number Generator (TRNG). By measuring the so-called Maximum Current Fluctuation (MCF) at carefully chosen observation windows, our design switches effortlessly between the stable outputs needed for a PUF and the maximally unpredictable bitstreams demanded by a TRNG. Although single-defect RTN has long been deemed ideal for randomness, we show that multi-defect RTN scenarios, much more prevalent in real-world manufacturing, can also yield high-quality random bits, especially when aided by lightweight post-processing. Simple statistical metrics guide the initial tuning, after which the final bitstreams pass the NIST SP 800-22 test suite to validate the statistical soundness of our proposal. In doing so, we address key challenges that arise when designing an RTN-based TRNG and compare our results against state-of-the-art solutions, highlighting advantages in circuit simplicity, bit-rate scalability, and dual-use capability.
Design of Event-Driven SPAD-Based 3D Image Sensors
R. Gómez-Merchán, J. A. Leñero-Bardallo and Á. Rodríguez-Vázquez
Book · 234 P, 2024
CRC Press ISBN: 978-10-32-51353-9
abstract
The book presents a top-down circuit description for the implementation of asynchronous vision sensors based on Single-Photon Avalanche Diodes (SPADs). It provides design considerations to convey the SPADs pulses through a channel shared by all the pixels. The book also presents architectures where dynamic vision sensors and SPADs converge.
Design of Event-Driven SPAD-Based 3D Image Sensors provides detailed technical insights about novel image sensor architectures with SPADs with asynchronous operation. At the sensor level, the book provides asynchronous circuitry to read and arbiter the pixel outputs. The authors explore new LiDAR architectures with asynchronous operation and provide insights into their design. A detailed benchmark of modern and competitive LiDAR systems is also presented. At the pixel level, the book provides design considerations to convey the SPADs pulses through a channel shared by all the pixels. At the sensor level, the book provides asynchronous circuitry to read and arbiter the pixel outputs. Finally, experimental results of very novel LiDAR systems with asynchronous operation will be provided and analyzed.
The book is written for professionals who want to explore new tendencies on the design of image sensors for the implementation of LiDAR systems.
Exploiting the acousto-optic effect for developing secure digital identifiers
D. Martín-Sánchez and P. Brox
Conference · Moscone South, Room 302 (Level 3), San Francisco, Estados Unidos, 28 Enero 2025
abstract
Cybersecurity is rooted in hardware to achieve high security. Physical unclonable functions (PUFs) are cryptographic primitives that implement one-way functions to generate cryptographic keys on-demand. Current approaches implement PUFs using microelectronic circuits that exploit the random manufacturing variabilities. Other alternatives exploit optical principles to offer higher security. However, their reliability is compromised by environmental effects and integrated systems are still to be realized. Here a novel approach is proposed to enhance reliability and potentially enable integration in digital security systems. The proposed method uses the acousto-optical effect to interrogate optical PUFs, avoiding precision alignment of moving parts and bulky equipment. This way of interrogating the PUF can also be miniaturized in a photonic integrated circuit. The experimental results demonstrate the feasibility of this approach and the potential for generating a large number of truly random cryptographic keys.
Open Source API for a Hardware Root-of-Trust
E. Camacho-Ruiz, L.F. Rojas-Muñoz, A. Karmakar, P. Navarro-Torrero, P. Brox and M.C. Martínez-Rodríguez
Conference · XVIII Reunión Española de Criptología y Seguridad de la Información, 23-25 octubre 2024, León (España)
abstract
This paper presents an API designed for a hardware-based Root of Trust that provides a suite of essential cryptographic and security functions based on hardware cryptographic IP cores. The high-level abstraction of the API enables software developers to create secure applications within secure computing systems by leveraging the benefits of hardware IP cores. The hardware IP cores that support the API are compliant with international standards, ensuring robust security and reliability. The API development adheres to the open-source science policies and is published online under a public license. Additionally, the portability of the API across multiple platforms ensures wide compatibility and accessibility, enabling seamless integration and reproducibility.
Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems
P. Navarro-Torrero, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
abstract
doi
This paper presents the design and implementation of a Karatsuba multiplier to accelerate digital signature schemes on embedded systems. The Karatsuba algorithm is integrated into hardware accelerators for RSA and EdDSA, representing a fundamental component of contemporary, state-of-the-art implementations. A hardware/software co-design methodology is employed, implementing the architectures on a System-onChip platform that combines programmable logic with an ARM processor. The results showcase enhanced resource consumption and timing performance for both signature generation and verification, confirming the superiority of EdDSA over RSA when utilizing the same Karatsuba multiplier core and coding techniques.
VLSI integration of a RO-based PUF into a 65 nm technology
P. Ortega-Castro, L.F. Rojas-Muñoz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
abstract
doi
Ring Oscillator Physical Unclonable Functions (ROPUFs) take advantage of process variability during the manufacturing process to exploit the small differences in the RO oscillating frequencies and generate unique identifiers (ID). Its structure makes it suitable for, both, FPGA and ASIC applications. This paper presents a RO-PUF implementation using a semi-custom design methodology in TSMC 65 nm technology which has been validated through the entire design process, manufactured and experimentally characterized. Results show a good performance and robustness against temperature and voltage variations while obtaining up to three bits from each execution to generate digital IDs.
A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs
F. de los Santos-Prieto, F.J. Rubio-Barbero, R. Castro-López, E. Roca and F.V. Fernández
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers (Early Access), 2024
IEEE ISSN: 1549-8328
abstract
doi
Silicon Physical Unclonable Functions (PUFs) have emerged as a promising solution for generating cryptographic keys in low-cost resource-constrained devices. A PUF is expected to be reliable, meaning that its response bits should remain consistent each time the corresponding challenges are queried. Unfortunately, the stability of these challenge-response pairs (CRPs) can be seriously eroded by environmental factors like temperature variations and the aging of the integrated circuits implementing the PUF. Several approaches, including bit masking, bit selection techniques, and error-correcting codes, have been proposed to obtain a reliable PUF operation in the face of temperature variations. As for aging, a new kind of aging-resilient silicon PUF has been reported that uses the time-varying phenomenon known as Random Telegraph Noise (RTN) as the underlying entropy source. Although this type of PUF preserves its reliability well when aged, it is not immune to the impact of temperature variations. The work presented here shows that it is possible to improve the thermal reliability of RTN-based PUFs with a proper combination of (a) a novel optimization-based bit selection technique, that is also applicable to other types of PUFs based on differential measurements; and (b) a temperature-aware tuning of the entropy-harvesting function.
A Review of Ising Machines Implemented in Conventional and Emerging Technologies
T. Zhang, Q. Tao, B. Liu, A. Grimaldi, E. Raimondo, M. Jiménez, M.J. Avedillo, J. Núñez, B. Linares-Barranco, T. Serrano-Gotarredona, G. Finocchio and Jie Han
Journal Paper · IEEE Transactions on Nanotechnology (Early Access), 2024
IEEE ISSN: 1536-125X
abstract
doi
Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and pase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOSspintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management
S. Sánchez-Solano, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 24, no. 17, article 5674, 2024
MDPI ISSN: 1424-8220
abstract
doi
The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4
configurable logic blocks (CLBs) to accommodate the RO bank.
Full Open-Source Implementation of an Academic RISC-V on FPGA
P. Navarro-Torrero, M.C. Martínez-Rodríguez, A. Barriga-Barros and P. Brox
Conference · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
abstract
doi
In alignment with the ethos of openness and democracy inherent in the RISC-V architecture, our research endeavors have been directed towards the utilization of open-source tools for the implementation of a simple but didactic RISC-V processor denoted as ASTIRV32I. The paper discusses the design strategies, memory mapping, physical verification procedures, and performance evaluation of the ASTIRV32I processor. Furthermore, it highlights the successful validation of the implemented design through the execution of fundamental algorithms, exemplifying the practicality and viability of the RISC-V-based processor design and serving as a proof-of-concept for open-source FPGA design.
