Spanish National Research Council · University of Seville
 HOME
INTRANET
esp    ing
IMSE-CNM in Digital.CSIC


 


In all publications
Recent publications
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder
A.J. Ginés, E. Peralías, C. Aledo and A. Rueda
Journal Paper - International Journal of Circuit Theory and Applications, first online, 2019
JOHN WILEY & SONS    DOI: 10.1002/cta.2594    ISSN: 0098-9886    » doi
[abstract]
This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

Assessing AMS-RF test quality by defect simulation
V. Gutierrez, A. Gines and G. Leger
Journal Paper - IEEE Transactions on Device and Materials Reliability, first online, 2019
IEEE    DOI: 10.1109/TDMR.2019.2894534    ISSN: 1530-4388    » doi
[abstract]
In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on practical cases of study that it is beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality. The computational burden of defect and fault simulations is taken into account and accurate statistical estimates of defect and fault escapes are provided to allow safe early stopping of the simulations.

A Multilevel Bottom-up Optimization Methodology for the Automated Synthesis of RF Systems
F. Passos, E. Roca, J. Sieiro, R. Fiorelli, R. Castro-López, J.M. López-Villegas and F.V. Fernández
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, first online, 2019
IEEE    DOI: 10.1109/TCAD.2018.2890528    ISSN: 0278-0070    » doi
[abstract]
In recent years there has been a growing interest in electronic design automation methodologies for the optimizationbased design of radiofrequency circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle radiofrequency systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this work, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multi-objective optimization algorithms are used to design an entire radiofrequency system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.

On the implementation of asynchronous sun sensors
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IS&T International Symposium on Electronic Imaging 2019
[abstract]
Abstract not avaliable

Compact Real-Time Inter-Frame Histogram Builder for 15Bits High-Speed ToF-Imagers based on Single-Photon Detection
I. Vornicu, A. Darie, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper - IEEE Sensors Journal, vol. 19, no. 6, pp 2181-2190, 2019
IEEE    DOI: 10.1109/JSEN.2018.2885960    ISSN: 1530-437X    » doi
[abstract]
Time-of-flight image sensors based on single-photon detection, i.e. SPADs, require some filtering of pixel readings. Accurate depth measurements are only possible if the jitter of the detector is mitigated. Moreover, the time stamp needs to be effectively separated from uncorrelated noise such as dark counts and background illumination. A powerful tool for this is building a histogram of a number of pixel readings. Future generation of ToF imagers are seeking to increase spatial and temporal resolution along with the dynamic range and frame rate. Under these circumstances, storing the complete histogram for every pixel becomes practically impossible. Considering that most of the information contained by the histogram represents noise, we propose a highly efficient method to store just the relevant data required for ToF computation. This method makes use of the shifted inter-frame histogram (SifH). It requires a memory as low as 128 times smaller than storing the complete histogram if the pixel values are coded on up to 15 bits. Moreover, a fixed 28 words memory is enough to process histograms containing up to 215 bins. In exchange, the overall frame rate only decreases to one half. The hardware implementation of this algorithm is presented. Its remarkable robustness for a low SNR of the ToF estimation is demonstrated by Matlab simulations and FPGA implementation using input data from a SPAD camera prototype.

Power and Speed Evaluation of Hyper-FET Circuits
J. Núñez and M.J. Avedillo
Journal Paper - IEEE Access, vol. 7, pp 6724-6732, 2019
IEEE    DOI: 10.1109/ACCESS.2018.2889016    ISSN: 2169-3536    » doi
[abstract]
Many emerging devices are currently being explored as potential alternatives to complementary metal-oxide-semiconductor (CMOS) technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at circuit level. In this paper, we investigate the speed and power performance of Hyper-Field Effect Transistor (Hyper-FET) circuits, comparing them with both high-performance (HP) and low stand-by power (LSTP) Fin-Shaped Field Effect Transistor (FinFET) designs on the same technology node. The evaluation, which was carried out at gate and circuit level, includes characterization of 8 bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from transistor and gate level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated which support the obtained results.

Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks
E. Tena-Sánchez and A.J. Acosta
Journal Paper - International Journal of Circuit Theory and Applications, vol. 47, no. 2, pp 238-253, 2019
JOHN WILEY & SONS    DOI: 10.1002/cta.2587    ISSN: 0098-9886    » doi
[abstract]
This paper discusses the use of logic minimization techniques and wide fan-in primitives and how the design and evaluation of combinational blocks for full-custom dual-precharge-logic-based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed and applied to the gate-level design of substitution boxes, widely used in block ciphers, using sense-amplifier-based logic in a 90-nm technology. The security of several proposals was evaluated with simulation-based correlation power analysis attacks, using the secret key measurements to disclosure metric. The simulation results showed increased security-power-delay figures for our proposals and, surprisingly, indicated that those solutions which minimized area occupation were both the most secure and the most power-efficient.

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
J. Diaz-Fortuny, J. Martin-Martines, R. Rodriguez, R. Castro-Lopez, E. Roca, X. Aragones, E. Barajas, D. Mateo, F.V. Fernandez and M. Nafria
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp 476-488, 2019
IEEE    DOI: 10.1109/JSSC.2018.2881923    ISSN: 0018-9200    » doi
[abstract]
Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm2.

A Multilevel Approach for the Systematic Design of Radiofrequency Integrated Circuits
F. Moreira de Passos
Thesis - Date of defense: 13/04/2018
UNIVERSIDAD DE SEVILLA, IMSE-CNM    
[abstract]
La tesis que se presenta, se centra exactamente en el desarrollo de nuevas metodologías de diseño capaces de mejorar el estado del arte y acortar la brecha de productividad existente en el diseño de circuitos RF. Por lo tanto, con el fin de establecer una nueva metodología de diseño para sistemas RF, se han de abordar distintos cuellos de botella del diseño RF con el fin de diseñar con éxito dichos circuitos. El diseño de circuitos RF ha seguido tradicionalmente una estrategia basada en ecuaciones analíticas derivadas específicamente para cada circuito y que exige una gran experiencia del diseñador. Esto significa que el diseñador plantea una estrategia para diseñar el circuito manualmente y, tras varias iteraciones, normalmente logra que el circuito cumpla con las especificaciones deseadas. No obstante, conseguir diseños con prestaciones óptimas puede ser muy difícil utilizando esta metodología, ya que el espacio de diseño (o búsqueda) es enorme (decenas de variables de diseño con cientos de combinaciones diferentes). Aunque el diseñador llegue a una solución que cumpla todas las especificaciones, nunca estará seguro de que el diseño al que ha llegado es el mejor (por ejemplo, el que consuma menos energía).

Design of Trusted Piecewise-Affine Controllers and Virtual Sensors into CMOS Integrated Circuits
M.C. Martínez Rodríguez
Thesis - Date of defense: 25/06/2018
UNIVERSIDAD DE SEVILLA, IMSE-CNM    
[abstract]
This Ph.D. Dissertation presents hardware realizations to generate PWA functions that are easy to configure and program, and that allow including embedded controllers and sensors into challenging applications requiring very small size, low power consumption, rapid response, short time-to-market, and security in the data provided by the hardware as well as integrity of the hardware itself.

Scopus access Wok access