Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Insights into the Dynamics of Coupled VO2 Oscillators for ONNs
J. Núñez, J.M. Quintana, M.J. Avedillo, M. Jiménez, A. Todri-Sanial, E. Corti, S. Karg and B. Linares-Barranco
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, first online, 2021
IEEE    DOI: 10.1109/TCSII.2021.3085133    ISSN: 1549-7747    » doi
The collective behavior of many coupled oscillator systems is currently being explored for the implementation of different non-conventional computing paradigms. In particular, VO2 based nano-oscillators have been proposed to implement oscillatory neural networks that can serve as associative memories, useful in pattern recognition applications. Although the dynamics of a pair of coupled oscillators have already been extensively analyzed, in this paper, the topic is addressed more practically. Firstly, for the application mentioned above, each oscillator needs to be initialized in a given phase to represent the input pattern. We demonstrate the impact of this initialization mechanism on the final phase relationship of the oscillators. Secondly, such oscillatory networks are based on frequency synchronization, in which the impact of variability is critical. We carried out a comprehensive mathematical analysis of a pair of coupled oscillators taking into account both issues, which is a first step towards the design of the oscillatory neural networks for associative memory applications.

Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions
J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, J. Martin-Martinez, R. Castro-Lopez, E. Roca, F.V.Fernandez and M. Nafria
Journal Paper - Solid-State Electronics, vol. 185, article 108037, 2021
ELSEVIER    DOI: 10.1016/j.sse.2021.108037    ISSN: 0038-1101    » doi
In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and to understand the effects of these variability sources, an extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models and simulation tools needed to achieve reliable integrated circuits. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at nominal and accelerated aging conditions. To this end, a versatile transistor array chip and a flexible measurement setup have been used to reduce the required testing time to attainable values.

Cognitive Radio Circuits and Systems - Application to Digitizers
H. Aboushady, A. Sayed, L.A. Camuñas-Mesa and J.M. de la Rosa
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
This paper gives an overview of Cognitive-Radio (CR) circuits and systems, that will enable the implementation of new technology paradigms such as software-defined electronics and Artificial Intelligence (AI) managed Internet-of-Things (IoT). A survey of the state of the art, trends and design challenges is presented from a top-down perspective - from system-level to circuit and chip implementation. As an application, special emphasis is put on analog/digital interfaces as one of the key building blocks in CR-based devices. Cutting-edge architectures - mostly based on ΣΔ Modulators (ΣΔMs) - are discussed, as well as the best candidate circuit strategies to implement CR-based digitizers in deep nanometer CMOS.

Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices
C. Mohan, L.A. Camuñas-Mesa, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired neuromorphic systems. Large-scale neuromorphic hardware platforms are being developed with increasing number of neurons and synapses, having a critical bottleneck in the online learning capabilities. Spike-timing-dependent plasticity (STDP) is a widely used learning mechanism inspired by biology which updates the synaptic weight as a function of the temporal correlation between pre- and post-synaptic spikes. In this work, we demonstrate experimentally that binary stochastic STDP learning can be obtained from a memristor when the appropriate pulses are applied at both sides of the device.

Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization roadblock
M. Nafria, J. Diaz-Fortuny, P. Saraza-Canflanca, J. Martin-Martinez, E. Roca, R. Castro-Lopez, R. Rodriguez, P. Martin-Lloret, A. Toro-Frias, D. Mateo, E. Barajas, X. Aragones and F.V. Fernandez
Conference - IEEE Latin America Electron Devices Conference LAEDC 2021
The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.

HardBlock: Demonstrator of physically binding an IoT device to a non-fungible token in Ethereum blockchain
J. Arcenegui, R. Arjona and I. Baturone
Conference - Design, Automation and Test in Europe DATE 2021
Nowadays, blockchain is a growing technology in the Internet of Thing (IoT) ecosystem. In this work, we show a demonstrator of an IoT device bound to a Non-Fungible Token (NFT) based on the ERC-721 standard of Ethereum blockchain. The advantages of our solution is that IoT devices can be controlled securely by events from the blockchain and authenticated users, besides being able to carry out blockchain transactions. The IoT device generates its own Blockchain Account (BCA) using a secret seed firstly generated by a True Random Number Generator (TRNG) and then reconstructed by a Physical Unclonable Function (PUF). A Pycom Wipy 3.0 board with the ESP32 microcontroller is employed as IoT device. The internal SRAM of the microcontroller acts as PUF and TRNG. The SRAM is controlled by a firmware developed in ESP-IDF. A smart contract developed in Solidity using Remix IDE creates the token. Kovan testnet and a Graphical User Interface programmed in Python are employed to show the results.

A Quantum-Resistant and Fast Secure Boot for IoT Devices using Hash-Based Signatures and SRAM PUFs
R. Román and I. Baturone
Conference - EAI International Conference on Safety and Security in Internet of Things SaSeIoT 2021
Abstract not available

20-ps Resolution Clock Distribution Network for a Fast-Timing Single-Photon Detector
N. Egidos, R. Ballabriga, F. Bandi, M. Campbell, D. Gascon, S. Gomez, J.M. Fernandez-Tenllado, X. Llopart, R. Manera, J. Mauricio, D. Sanchez, A. Sanmukh and E. Santin
Journal Paper - IEEE Transactions on Nuclear Science, vol. 68, no. 4, pp. 434-446, 2021
IEEE    DOI: 10.1109/TNS.2021.3057581    ISSN: 0018-9499    » doi
The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64 x 64 pixels over an area of 2.4 x 2.4 cm2 using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution.

Secure Combination of IoT and Blockchain by Physically Binding IoT Devices to Smart Non-Fungible Tokens using PUFs
J. Arcenegui, R. Arjona, R. Román and I. Baturone
Journal Paper - Sensors, vol. 21, no. 9, article 3119, 2021
MDPI    DOI: 10.3390/s21093119    ISSN: 1424-8220    » doi
Non-fungible tokens (NFTs) are widely used in blockchain to represent unique and non-interchangeable assets. Current NFTs allow representing assets by a unique identifier, as a possession of an owner. The novelty introduced in this paper is the proposal of smart NFTs to represent IoT devices, which are physical smart assets. Hence, they are also identified as the utility of a user, they have a blockchain account (BCA) address to participate actively in the blockchain transactions, they can establish secure communication channels with owners and users, and they operate dynamically with several modes associated with their token states. A smart NFT is physically bound to its IoT device thanks to the use of a physical unclonable function (PUF) that allows recovering its private key and, then, its BCA address. The link between tokens and devices is difficult to break and can be traced during their lifetime, because devices execute a secure boot and carry out mutual authentication processes with new owners and users that could add new software. Hence, devices prove their trusted hardware and software. A whole demonstration of the proposal developed with ESP32-based IoT devices and Ethereum blockchain is presented, using the SRAM of the ESP32 microcontroller as the PUF.

Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm
E. Camacho-Ruiz, S. Sánchez-Solano, P. Brox and M.C. Martínez-Rodríguez
Journal Paper - ACM Journal on Emerging Technologies in Computing Systems, vol. 17, no. 3, article 35, 2021
ACM    DOI: 10.1145/3445979    ISSN: 1550-4832    » doi
Post-quantum cryptographic algorithms have emerged to secure communication channels between electronic devices faced with the advent of quantum computers. The performance of post-quantum cryptographic algorithms on embedded systems has to be evaluated to achieve a good trade-off between required resources (area) and timing. This work presents two optimized implementations to speed up the NTRUEncrypt algorithm on a system-on-chip. The strategy is based on accelerating the most time-consuming operation that is the truncated polynomial multiplication. Hardware dedicated modules for multiplication are designed by exploiting the presence of consecutive zeros in the coefficients of the blinding polynomial. The results are validated on a PYNQ-Z2 platform that includes a Zynq-7000 SoC from Xilinx and supports a Python-based programming environment. The optimized version that exploits the presence of double, triple, and quadruple consecutive zeros offers the best performance in timing, in addition to considerably reducing the possibility of an information leakage against an eventual attack on the device, making it practically negligible.

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