Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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High-Speed and Low-Cost Implementation of Explicit Model Predictive Controllers
A. Gersnoviez, M. Brox and I. Baturone
Journal Paper - IEEE Transactions on Control Systems Technology, first online, 2017
IEEE    DOI: 10.1109/TCST.2017.2775187    ISSN: 1063-6536    » doi
This paper presents a new form of piecewise-affine (PWA) solution, referred to as PWA hierarchical (PWAH), to approximate the explicit model predictive control (MPC) law, achieving a very rapid control response with the use of very few computational and memory resources. This is possible because PWAH controllers consist of single-input single-output PWA modules connected in cascade so that the parameters needed to define them increase linearly instead of exponentially with the input dimension of the control problem. PWAH controllers are not universal approximators but several explicit MPC controllers can be efficiently approximated by them. A methodology to design PWAH controllers is presented and validated with application examples already solved by MPC approaches. The designed PWAH controllers implemented in field-programmable gate arrays provide the highest control speed using the fewest resources compared with the other digital implementations reported in the literature.

Bulk-based DC offset calibration for Low-power Memristor Array Read-Out System
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, L. Perniola, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
Memristors in neuromorphic circuits typically need to drive currents of many mA because their Low Resistance State (LRS) is in the order of a few kΩ and many devices need to be activated simultaneously which results in high power consumptions. Reducing read-out pulses amplitudes below the typical 0.1V is not trivial, as offset voltages of read-out circuits start to affect the results. This paper presents a three-stage cascaded calibration to compensate for the resting offset voltage of crossbar lines generated in the amplifiers driving memristive devices in memristor array read-out systems. The proposed calibration technique is based on adjusting the bulk voltage of the input differential pairs by means of a switchable cascade of resistor ladders. As a result, the calibrated offset voltage can be further reduced with the number of stages in the cascade, leading to a calibration voltage step below 0.1mV -only limited in practice by mismatch and electrical noise. The circuit has been designed in 130nm CMOS technology, and its operation has been verified with oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in neuromorphic circuits. Layout-extracted simulations considering PVT variations are considered to validate the presented calibration technique.

Design Automation of ΣΔ Converters: A Review of Modeling, Synthesis and Optimization Techniques
J.M. de la Rosa
Conference - Electron Devices and Solid-State Circuits EDSSC 2017
This work presents an overview of the state of the art and recent advances on CAD tools for the design automation and optimization of ΣΔ converters. System-level modeling and simulation strategies are outlined, putting emphasis on how they can be combined with heuristic techniques and know-how to maximize the performance of data conversion based on Modulators.

Design automation methodologies for AMS circuits
S. Sapatnekar, J. Gu, R. Castro, H. Li, M. Cho, Z. Zhang, F. Koushanfar, K. Yang and J. Rajendran
Conference - Int. Workshop on Design Automation for Analog and Mixed-Signal Circuits 2017
Growing digitization of integrated circuits has contributed to making system-on-chips ever more complex. Yet, a substantial portion of a chip consists of analog and mixed-signal (AMS) circuits that provide critical functionality like signal conversion. Over the past several decades, aggressive scaling of IC technologies, as well as advancing the integration of heterogeneous physical domains on chip, substantially complicates the design of AMS components. On the one hand, their modeling and design becomes extremely complex. On the other hand, their interplay with the rest of the system-on-chip challenges design, verification and test. The new technology trends bring enormous challenges and opportunities for AMS design automation. This is reflected by an increase in research activity on AMS CAD worldwide. The purpose of this workshop is to bring together academic and industrial researchers from both design and CAD communities to report recent advances and motivate new research topics and directions in this area.

Efficient Computation of Yield and Lifetime for Analog ICs under Process Variabiliy and Aging
A. Toro-Frías, P. Martin-Lloret, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability (i.e., spatial or process variability) but also the degradation due to time-dependent variability (i.e., aging). While process variability has been extensively treated, solutions to cope with aging-related problems are, nowadays, not yet mature enough, especially in the field of analog circuit simulation. Nevertheless, considerable efforts are currently being made to develop new simulation tools and simulation methodologies to evaluate the impact of reliability effects. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.

Bioimpedance real-time characterization of neointimal tissue inside stents
D. Rivas-Marchena, A. Olmo, G. Huertas, A. Yúfera, J. A. Miguel and M. Martinez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
It is hereby presented a new approach to monitor restenosis in arteries fitted with a stent during an angioplasty. The growth of neointimal tissue is followed up by measuring its bioimpedance with Electrical Impedance Spectroscopy (EIS). Besides, a mathematical model is derived to analytically describe the neointima´s histological composition from its bioimpedance. The model is validated by finite-element analysis (FEA) with COMSOL Multiphysics ®. Satisfactory correlation between the analytical model and the FEA simulation is achieved for most of the characterization range, detecting some deviations introduced by the thin "double layer" that separates the neointima and the blood. It is shown how to apply conformal transformations to obtain bioimpedance models for stack-layered tissues over coplanar electrodes. Particularly, this is applied to characterize the neointima in real-time. This technique is either suitable as a main mechanism of restenosis follow-up or it can be combined with proposed blood-pressure-measuring intelligent stents to auto-calibrate the sensibility loss caused by the adherence of the tissue on the micro-electro-mechanical sensors (MEMS).

Using Physical Unclonable Functions for Internet-of-Thing Security Cameras
R. Arjona, M.A. Prada-Delgado, J. Arcenegui and I. Baturone
Conference - EAI International Conference on Safety and Security in Internet of Things SaSeloT 2017
This paper proposes a low-cost solution to develop IoT security cameras. Integrity and confidentiality of the image data is achieved by using the cryptographic modules that implement symmetric key-based techniques which are usually available in the hardware of the IoT cameras. The novelty of this proposal is that the secret key required is not stored but reconstructed from public data and from the start-up values of a SRAM in the camera hardware acting as a PUF (Physical Unclonable Function), so that the physical authenticity of the camera is also ensured. The variability of the start-up values of the SRAM is also exploited to change the IV (initialization vector) in the encryption algorithm, thus increasing security. All the steps to be carried out by the IoT camera at enrollment and normal operation can be included in a simple firmware to be executed by the camera. In addition, this firmware can be trustworthy updated. There is no need to include specific hardware (such as TPMs) but only an SRAM is needed which could be powered down and up by firmware.

Unified Hardware-Based Description for SAR ADCs with Redundancy
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
This paper presents an analysis and review of digital redundancy techniques in Successive-Approximation-Register (SAR) ADCs for correction of comparator errors during the SAR search algorithm. The use of redundancy provides safety margin for dealing with incomplete settling in the DAC network, improving conversion speed and power, as well as relaxing switch sizes and comparator design. Techniques like binaryscaled, radix-based or arbitrary weighing capacitors with redundant bits are discussed using a unified nomenclature and modeling. The proposed unified description is closely related to the hardware realization eliminating the gap between theoretical and physical implementations, and allowing a clear identification of pros and cons of different approaches. For illustration purpose, several examples are modeled and simulated using the proposed description.

A Sub-μVrms Chopper-Stabilized Local Field Potential Amplifier
N. Pérez-Prieto, J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
This paper describes a low-noise, low-power and fully differential amplifier intended for sensing neural signals. In order to reduce 1/f noise, the amplifier is chopper-stabilized. To palliate the up-modulated dc offset due to chopper-stabilization, an integrator with programmable duty-cycled resistors is implemented. A switched-capacitor common-mode feedback and a low pass filter, carried out using subthreshold-source-follower biquad, guarantee lower power consumption and lower distortion on the circuit. Transistor-level simulations were realized in a prototype designed in a 0.18 μm AMS CMOS technology with a 1V supply showing a low power consumption (1.67 μW) and a noise floor of 0.8 μVrms over a bandwidth from 1 to 200 Hz.

Statistical characterization of reliability effects in nanometer CMOS using a versatile transistor array IC
J. Díaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca, F.V. Fernández, E. Barajas-Ojeda, X. Aragones and D. Mateo-Peña
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
In this work, an experimental framework for the characterization of various reliability effects in modern CMOS technologies is described. The main element in this framework is a versatile transistor array chip, designed to accurately characterize process variability, Random Telegraph Noise and BTI/HCI related time dependent variability effects. The measurement setup, the other element in the framework, has been designed to take full advantage of the array architecture, which allows parallel testing of its 3136 MOS transistors, thereby reducing considerably the total measurement time. Thanks to a control toolbox and a user-friendly GUI, the setup also facilitates the programming of any of the required characterization tests.

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