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Visual Inference for IoT Systems: A Practical Approach
D. Velasco-Montero, J. Fernández-Berni and A. Rodríguez-Vázquez
Book · 145 p, 2022
SPRINGER    ISBN: 978-3-030-90903-1    
resumen      link      

This book presents a systematic approach to the implementation of Internet of Things (IoT) devices achieving visual inference through deep neural networks. Practical aspects are covered, with a focus on providing guidelines to optimally select hardware and software components as well as network architectures according to prescribed application requirements.
The monograph includes a remarkable set of experimental results and functional procedures supporting the theoretical concepts and methodologies introduced. A case study on animal recognition based on smart camera traps is also presented and thoroughly analyzed. In this case study, different system alternatives are explored and a particular realization is completely developed.
Illustrations, numerous plots from simulations and experiments, and supporting information in the form of charts and tables make Visual Inference and IoT Systems: A Practical Approach a clear and detailed guide to the topic. It will be of interest to researchers, industrial practitioners, and graduate students in the fields of computer vision and IoT.

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA
F.E. Potestad-Ordonez, E. Tena-Sanchez, J.M. Mora-Gutierrez, M. Valencia-Barrero and C.J. Jimenez-Fernandez
Journal Paper · IEEE Access, vol. 9, pp 168444-168454, 2021
IEEE    ISSN: 2169-3536
resumen      doi      

Attacks on cryptocircuits are becoming increasingly sophisticated, requiring designers to include more and more countermeasures in the design to protect it against malicious attacks. Fault Injection Attacks and Differential Fault Analysis have proven to be very dangerous as they are able to retrieve the secret information contained in cryptocircuits. In this sense, Trivium cipher has been shown to be vulnerable to this type of attack. This paper presents four different fault detection schemes to protect Trivium stream cipher implementations against fault injection attacks and differential fault analysis. These countermeasures are based on the introduction of hardware redundancy and signature analysis to detect fault injections during encryption or decryption operations. This prevents the attacker from having access to the faulty key stream and performing differential fault analysis. In order to verify the correct operation and the effectiveness of the presented schemes, an experimental system of non-invasive active attacks using the clock signal in FPGA has been designed. This system allows to know the fault coverage for both multiple and single faults. In addition, the results of area consumption, frequency degradation, and fault detection latency for FPGA and ASIC implementations are presented. The results show that all proposed countermeasures are able to provide a fault coverage above 79% and one of them reaches a coverage of 99.99%. It has been tested that the number of cycles for fault detection is always lower than the number of cycles needed to apply the differential fault analysis reported in the literature for the Trivium cipher.

A Reduced-scale Cortical Network with Izhikevich's Neurons on SpiNNaker
C. Chiplunkar, N. Gautam, I. Mediratta,A. Gait, S. Thomas, A. Rowley, T. Serrano-Gotarredona and B. Sen-Bhattacharya
Conference · IEEE International Joint Conference on Neural Networks IJCNN 2021
resumen     

Following the initial implementation of a full-scale spiking neural network (SNN) of the cortical microcircuit on NEST, the work was replicated to simulate on SpiNNaker, the Juelich CPU cluster, and the Sussex GPU cluster, in order to compare the performances on the different platforms. All of these researches use the Leaky Integrate and Fire (LIF) model as the basic unit of spiking neurons. In comparison, Izhikevich's spiking neuron models (IZK) can mimic a larger variety of known cortical neuronal dynamics. In spite of this versatility, the IZK neuron is easy to implement and computes fast. In this work, we implement the above-mentioned cortical micro-circuit at a reduced-scale and using IZK neurons on SpiNNaker. This is aligned with our ongoing research on a reduced-scale thalamocortical circuit of vision with changing IZK neuron dynamics on SpiNNaker. We validate our SNN with the LIF-based full-scale cortical microcircuit by providing Poisson noise inputs, and measuring objectively the outputs in terms of spike rate, irregularity and synchrony. Our reduced-scale SNN shows similar dynamics to the full-scale SNN and operates within the Asynchronous Irregular regime defined by set bounds on the three quantitative attributes. Next, we test our SNN with inputs from a Dynamic Vision Sensor- (DVS-)based electronic retina (e-retina) that converted a simple periodic environmental input to spike trains. With current parameter settings, the model output identifies the low-frequency, but not the high frequency periodic inputs.

A Neuromorphic CMOS Circuit with Self-Repairing Capability
E. Rahiminejad, F. Azad, A. Parvizi-Fard, M. Amiri and B. Linares-Barranco
Journal Paper · IEEE Transactions on Neural Networks and Learning Systems, first online, 2021
IEEE    ISSN: 2162-237X
resumen      doi      

Neurophysiological observations confirm that the brain not only is able to detect the impaired synapses (in brain damage) but also it is relatively capable of repairing faulty synapses. It has been shown that retrograde signaling by astrocytes leads to the modulation of synaptic transmission and thus bidirectional collaboration of astrocyte with nearby neurons is an important aspect of self-repairing mechanism. Specifically, the retrograde signaling via astrocyte can increase the transmission probability of the healthy synapses linked to the neuron. Motivated by these findings, in the present research, a CMOS neuromorphic circuit with self-repairing capabilities is proposed based on astrocyte signaling. In this way, the computational model of self-repairing process is hired as a basis for designing a novel analog integrated circuit in the 180-nm CMOS technology. It is illustrated that the proposed analog circuit is able to successfully recompense the damaged synapses by appropriately modifying the voltage signals of the remaining healthy synapses in the wide range of frequency. The proposed circuit occupies 7500- µm² silicon area and its power consumption is about 65.4 µW. This neuromorphic fault-tolerant circuit can be considered as a key candidate for future silicon neuronal systems and implementation of neurorobotic and neuro-inspired circuits.

Design of Readout Channels for Direct-ToF LiDAR
M. Parsakordasiabi, A. Rodríguez-Vázquez and R. Carmona-Galán
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2021
resumen     

Direct-time-of-flight (d-ToF) readout channels are required to be precise, high speed, and linear while preserving low resources for multi-channel applications. Although meeting these requirements seems to be difficult, they are highly demanded in many applications like light detection and ranging (LiDAR) sensors. This thesis project is dedicated to the design of a high-linearity high-measurement throughput low-resources FPGA-based time-to-digital converters (TDCs). We are working on the reduction of the dead-time by using a toggling input stage and a dual-mode counter-based encoder. In addition, the linearity is improved by using a dual-mode bin-width calibrator and a robust encoder.

Outgoing Editorial
J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 12, pp 3477-3477, 2021
IEEE    ISSN: 1549-7747
resumen      doi      pdf

Abstract not available

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles using TFETs
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A.J. Acosta
Journal Paper · IEEE Embedded Systems Letters, first online, 2021
IEEE    ISSN: 1943-0663
resumen      doi      

The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. The paper deals with the optimized design of DPA-resilient hiding-based techniques, using Tunnel Field-Effect Transistors (TFETs). Specifically, proposed TFET implementations of Dual-Precharge-Logic primitives optimizing their computation tree in three different ways, are applied to the design of PRIDE Sbox-4, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals have shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction (x25), compared to their CMOS-based counterparts in 65nm, which is a significant advance in the development of secure circuits with TFETs.

Experimental FIA Methodology using Clock and Control Signal Modifications under Power Supply and Temperature Variations
F.E. Potestad-Ordóñez, E. Tena-Sánchez, J.M. Mora-Gutierrez, M. Valencia-Barrero and C.J. Jiménez-Fernández
Journal Paper · Sensors, vol. 21, no. 22, article 7596, 2021
MDPI    ISSN: 1424-8220
resumen      doi      

The security of cryptocircuits is determined not only for their mathematical formulation, but for their physical implementation. The so-called fault injection attacks, where an attacker inserts faults during the operation of the cipher to obtain a malfunction to reveal secret information, pose a serious threat for security. These attacks are also used by designers as a vehicle to detect security flaws and then protect the circuits against these kinds of attacks. In this paper, two different attack methodologies are presented based on inserting faults through the clock signal or the control signal. The optimization of the attacks is evaluated under supply voltage and temperature variation, experimentally determining the feasibility through the evaluation of different Trivium versions in 90 nm ASIC technology implementations, also considering different routing alternatives. The results show that it is possible to inject effective faults with both methodologies, improving fault efficiency if the power supply voltage decreases, which requires only half the frequency of the short pulse inserted into the clock signal to obtain a fault. The clock signal modification methodology can be extended to other NLFSR-based cryptocircuits and the control signal-based methodology can be applied to both block and stream ciphers.

A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System
N. Perez-Prieto, A. Rodriguez-Vazquez, M. Alvarez-Dolado and M. Delgado-Restituto
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 15, no. 5, pp 960-977, 2021
IEEE    ISSN: 1932-4545
resumen      doi      

This paper presents a high dynamic range, lowpower, low-noise mixed-signal front-end for the recording of local field potentials or electroencephalographic signals with invasive neural implants. It features time-multiplexing of 32 channels at the electrode interface for area saving and offers the ability to spatially delta encode signals to take advantage of the large correlations between nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information, thus effectively increasing the dynamic range of the system while avoiding the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro and shows an integrated input-referred noise in the 0.5200 Hz band of 1.4 Vrms for a spot noise of about 85 nV/Hz. The system draws 1.5 W per channel from 1.2 V supply and obtains 71 dB + 26 dB (with artifact compression) dynamic range, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios.

The role of intra-clutch variation of magpie clutches in foreign egg rejection depends on the egg trait considered
M. Molina-Morales, J. Gómez, G. Liñan, M. Precioso, J.G. Martinez and J.M. Avilés
Journal Paper · Frontiers in Ecology and Evolution, vol. 9, article 702637, 2021
FRONTIERS    ISSN: 2296-701X
resumen      pdf

The existence of a coevolutionary process between avian brood parasites and their hosts predicts a lower intra-clutch variation in egg appearance of host eggs among rejecters as this would favour egg discrimination of parasite eggs by hosts once parasitic egg mimicry had evolved. So far empirical tests of this prediction have ignored the fact that different aspects of host egg phenotypes may differ in the relative role of environmental versus genetic determination, and hence that the role of intra-clutch variation in egg rejection within a population cannot be invariant. Here, we estimated whether the intra-clutch variation in several aspects of host eggshell features is consistently associated to rejection of parasitic foreign eggs across years in a magpie host population parasitized by great spotted cuckoos. We innovatively estimated spottiness by means of the fractal dimension of eggs, which considers the homogeneity of spot pattern complexity in eggshells. Our results show that low intra-clutch variation in the blue-green coloration at the middle area of the eggs associated with a high chance of rejection, but only in one of the three years we conducted the study. In addition, females that rejected foreign eggs presented more homogenous spot patterns in their clutches as estimated by their fractal dimension than females that accepted experimental eggs, independently of the year of study. Finally, intra-clutch variation in egg volume of host eggs was not associated to rejection. Analyses at the individual level revealed that the relative role of genetic versus environmental factors determination egg phenotype would be feature-specific in magpies, females having a characteristic spottiness, but not colour or volume, pattern. Our work stresses the importance of considering a holistic approach including several aspects of variation in host egg phenotype (size, colour, and homogeneity of spot pattern), as some aspects might be more susceptible to selection through egg rejection than others, presumably because they are less influenced by variation in the environmental conditions. Moreover, our study highlights the importance of replication in studies on the adaptive value of host traits in egg rejection.
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