Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Behavioral and Physical Unclonable Functions (BPUFs): SRAM Example
M.A. Prada-Delgado and I. Baturone
Journal Paper - IEEE Access, vol. 9, pp 23751-23763, 2021
IEEE    DOI: 10.1109/ACCESS.2021.3055493    ISSN: 2169-3536    » doi
Physical Unclonable Functions (PUFs) have gained a great interest for their capability to identify devices uniquely and to be a lightweight primitive in cryptographic protocols. However, several reported attacks have shown that virtual copies (mathematical clones) as well as physical clones of PUFs are possible, so that they cannot be considered as tamper-resistant or tamper-evident, as claimed. The solution presented in this article is to extend the PUFs reported until now, which are only physical, to make them Behavioral and Physical Unclonable Functions (BPUFs). Given a challenge, BPUFs provide not only a physical but also a behavioral distinctive response caused by manufacturing process variations. Hence, BPUFs are more difficult to attack than PUFs since physical and behavioral responses associated to challenges have to be predicted or cloned. Behavioral responses that are obtained from several measurements of the physical responses taken at several sample times are proposed. In this way, the behavioral responses can detect if the physical responses are manipulated. The analysis done for current PUFs is extended to allow for more versatility in the responses that can be considered in BPUFs. Particularly, Jaccard instead of Hamming distances are proposed to evaluate the similarity of behavioral responses. As example to validate the proposed solution, BPUFs based on Static Random-Access Memories (SRAM BPUFs), with one physical and one behavioral responses to given challenges, were analyzed experimentally using integrated circuits fabricated in a 90-nm CMOS technology. If an attacker succeeds in cloning the physical responses as reported, but does not attack the way to obtain the behavioral responses, the attacker fails on SRAM BPUFs. The highest probability to succeed in cloning the behavioral responses with a brute-force attack was estimated from experimental results as $1.5 \cdot 10^{-34}$ , considering the influence of changes in the operating conditions (power supply voltage, temperature, and aging).

Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper - Microelectronics Reliability, vol 118, article 114049, 2021
ELSEVIER    DOI: 10.1016/j.microrel.2021.114049    ISSN: 0026-2714    » doi
The utilization of power-up values in SRAM cells to generate PUF responses for chip identification is a subject of intense study. The cells used for this purpose must be stable, i.e., the cell should always power-up to the same value (either ‘0’ or ‘1’). Otherwise, they would not be suitable for the identification. Some methods have been presented that aim at increasing the reliability of SRAM PUFs by identifying the strongest cells, i.e., the cells that more consistently power-up to the same value. However, these methods present some drawbacks, in terms of either their practical realization or their actual effectiveness in selecting the strongest cells at different scenarios, such as temperature variations or when the circuits have suffered aging-related degradation. In this work, the experimental results obtained for a new method to classify the cells according to their power-up strength are presented and discussed. The method overcomes some of the drawbacks in previously reported methods. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation and temperature variations, which ultimately translates into the construction of reliable SRAM-based PUFs.

Design of High-Efficiency SPADs for LiDAR Applications in 110nm CIS Technology
I. Vornicu, J.M. López-Martínez, F.N. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - IEEE Sensors Journal, vol. 21, no. 4, pp 4776-4785, 2021
IEEE    DOI: 10.1109/JSEN.2020.3032106    ISSN: 1530-437X    » doi
Single photon avalanche diodes (SPADs) featuring a high detection rate of near-IR photons are much desired for outdoor LiDAR based on direct time-of-flight (ToF). This article presents the complete design flow of a SPAD detector for LiDAR. First, the selection of the emitter wavelength is discussed, considering the maximum allowed power underlying eye safety regulations, solar irradiance, and reflected signal power. Then, the choice of the SPAD structure is discussed based on the TCAD simulation of quantum efficiency and crosstalk. Next, the proposed P-well/Deep N-well SPAD is explained. The electro-optical characterization of the detectors is presented as well. The performance of the time-of-flight image sensors is determined by the characteristics of the individual SPADs. To fully characterize this technology, devices with various sizes, shapes, and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is 18 V. The proposed structure has a 0.4 Hz/µ m2 dark count rate and 0.5% afterpulsing. The FWHM (total) jitter and photon detection probability at 850nm wavelength are of 92 ps and 10%. All figures have been measured at 3 V excess voltage. Finally, the performance of the SPAD detector is analyzed by evaluating the signal-to-noise ratio at different acquisition times. Distance ranging measurements have been performed, achieving a depth resolution of 1 cm up to 6.3 m range.

A Low-Resources TDC for Multi-Channel Direct ToF Readout based on a 28-nm FPGA
M. Parsakordasiabi, I. Vornicu, A. Rodríguez-Vázquez and R. Carmona-Galán
Journal Paper - Sensors, vol. 21, no. 1, article 308, 2021
MDPI    DOI: 10.3390/s21010308    ISSN: 1424-8220    » doi
In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [-0.953, 1.185] LSB, and an integral non-linearity (INL) within [-2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

Editorial: A Year Ahead Full of New Initiatives
J.M. de la Rosa
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 1, pp 4-4, 2021
IEEE    DOI: 10.1109/TCSII.2020.3041170    ISSN: 1549-7747    » doi
First of all, I hope that you, your families and all yours remain healthy and safe. The thoughts of the Editorial Board (EB) of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS (TCAS-II) and all the staff from IEEE are with those who are facing health problems and have suffered the consequences of the COVID-19 pandemic. The first year of my term as Editor-in-Chief (EiC) of IEEE TCAS-II has run under this terrible situation which has changed the lifestyle of all of us. We have seen how almost all social and professional events, including of course most IEEE conferences, have been either cancelled or running virtual, what has precluded us from enjoying together with our friends and colleagues as we had always done. The New Year 2021 comes full of hope for humankind with the development of several vaccines and more effective drugs to fight against the coronavirus SARS-Cov-2, and I am firmly convinced that sooner than later we will be able to recover our way of living.

An efficient transformer modeling approach for mm-wave circuit design
F. Passos, E. Roca, J. Sieiro, R. Castro-Lopez and F.V. Fernandez
Journal Paper - AEU - International Journal of Electronics and Communications, vol. 128, article 153496, 2021
ELSEVIER    DOI: 10.1016/j.aeue.2020.153496    ISSN: 1434-8411    » doi
In this paper, a Gaussian-process surrogate modeling methodology is used to accurately and efficiently model transformers, which are still a bottleneck in radio-frequency and millimeter-wave circuit design. The proposed model is useful for a wide range of frequencies from DC up to the millimeter-wave range (over 100 GHz). The technique is statistically validated against full-wave electromagnetic simulations. The efficient model evaluation enables its exploitation in iterative user-driven design approaches, as well as automated design exploration involving thousands of simulations. As experimental results, the model is used in several scenarios, such as the design of an inter-stage amplifier operating at 60 GHz, where the model assisted in the simulation of the transformers and baluns used, and the design of individual transformers and a matching network.

Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique
R. Feitoza, M.J. Barragan, A. Gines and S. Mir
Conference - IEEE International New Circuits and Systems Conference NEWCAS 2020
DOI: 10.1109/NEWCAS49341.2020.9159839    » doi
This work presents a reduced-code strategy for the static linearity self-testing of V-cm-based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the application of these techniques for the V-cm-based SAR ADC topology and present a practical BIST implementation based on an embedded incremental ADC. Electrical simulation results at transistor level are presented to validate the feasibility of the proposed on-chip reduced-code static linearity test.

Photon-Detection Timing-Jitter Model in Verilog-A
J.M. López-Martínez, R. Carmona-Galán and A. Rodríguez-Váquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
Single-photon avalanche diodes can be employed to register the arrival of an individual photon. They are biased beyond breakdown voltage, and thus the electron-hole pairs generated by any incident photon is accelerated by the strong electric field triggering an avalanche current. In recent years, there have been attempts to model its characteristics in Verilog-A HDL. However, none of them have modelled its photon-detection timing jitter. This paper explains the mechanism of avalanche triggering and proposes a first approach to model it in Verilog-A. Comparison with experimental data and data reported in literature validates the model.

Limitation of SPADs quantum efficiency due to the dopants concentration gradient
J.M. López-Martínez, R. Carmona-Galán and A. Rodríguez-Váquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
Single-photon avalanche diodes are highly sensitive devices capable of registering the arrival of an individual photon. They are biased beyond breakdown voltage, and thus the electron-hole pairs generated by any incident photon is accelerated by the strong electric field triggering an avalanche current. This paper examines the role of the dopants concentration gradient in the gathering of photons in these devices, and how it can be engineered to maximize quantum efficiency and explain his role to minimize undesirable effects like crosstalk.

Cellular-Neural-Network Focal-Plane Processor as Pre-Processor for ConvNet Inference
L.C. Gontard, R. Carmona-Galán and A. Rodríguez-Váquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
Cellular Neural Networks (CNN) can be embodied in the form of a focal-plane image processor. They represent a computing paradigm with evident advantages in terms of energy and resources. Their operation relies in the strong parallelization of the processing chain thanks to a distributed allocation of computing resources. In this way, image sensing and ultra-fast processing can be embedded in a single chip. This makes them good candidates for portable and/or distributed applications in fields like autonomous robots or smart cities. With the irruption of visual features learning through convolutional neural networks (ConvNets), several works attempt to implement this functionality within the CNN framework. In this paper we carry out some experiments on the implementation of ConvNets with CNN hardware in the form of a focal-plane image processor. It is shown that ultra-fast inference can be implemented, using as an example a LeNet-based ConvNet architecture.

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