Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop
R. Martins, N. Lourenço, F. Passos, R. Povoa, A. Canelas, E. Roca, R. Castro-López, J. Sieiro, F.V. Fernández and N. Horta
Conference - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, first online, 2018
In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid non-systematic iterations between sizing and layout design steps, a multi-objective optimization-based layout-aware sizing approach with pre-optimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multi-net router with pre-optimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely-used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

Concurrent focal-plane generation of compressed samples from time-encoded pixel values
M. Trevisi, H.C. Bandala, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Design Automation and Test in Europe DATE 2018
Compressive sampling allows wrapping the relevant content of an image in a reduced set of data. It exploits the sparsity of natural images. This principle can be employed to deliver images over a network under a restricted data rate and still receive enough meaningful information. An efficient implementation of this principle lies in the generation of the compressed samples right at the imager. Otherwise, i. e. digitizing the complete image and then composing the compressed samples in the digital plane, the required memory and processing resources can seriously compromise the budget of an autonomous camera node. In this paper we present the design of a pixel architecture that encodes light intensity into time, followed by a global strategy to pseudo-randomly combine pixel values and generate, on-chip and on-line, the compressed samples.

Performance Analysis of Real-Time DNN Inference on Raspberry Pi
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A.Rodríguez-Vázquez
Conference - SPIE Real-Time Image and Video Processing 2018
Deep Neural Networks (DNNs) have emerged as the reference processing architecture for the implementation of multiple computer vision tasks. They achieve much higher accuracy than traditional algorithms based on shallow learning. However, it comes at the cost of a substantial increase of computational resources. This constitutes a challenge for embedded vision systems performing edge inference as opposed to cloud processing. In such a demanding scenario, several open-source frameworks have been developed, e.g. Ca e, OpenCV, TensorFlow, Theano, Torch or MXNet. All of these tools enable the deployment of various state-of-the-art DNN models for inference, though each one relies on particular optimization libraries and techniques resulting in di erent performance behavior. In this paper, we present a comparative study of some of these frameworks in terms of power consumption, throughput and precision for some of the most popular Convolutional Neural Networks (CNN) models. The benchmarking system is Raspberry Pi 3 Model B, a low-cost embedded platform with limited resources. We highlight the advantages and limitations associated with the practical use of the analyzed frameworks. Some guidelines are provided for suitable selection of a speci c tool according to prescribed application requirements.

Weighted Time Lag Plot Defect Parameter Extraction and GPU-based BTI Modeling for BTI Variability
V.M. van Santen, J. Diaz-Fortuny, H. Amrouch, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez, J. Henkel and M. Nafria
Conference - IEEE International Reliability Physics Symposium IRPS 2018
Abstract not avaliable

A Noise and RTN-Removal Smart Method for the Parameter Extraction of CMOS Aging Compact Models
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
Conference - Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2018
Abstract not avaliable

Guest Editorial. Special Issue on the 2018 IEEE International Symposium on Circuits and Systems
José M. de la Rosa
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, p 531, 2018
IEEE    DOI: 10.1109/TCSII.2018.2826298    ISSN: 1549-7747    » doi
This special issue of IEEE Transactions on Circuits and Systems-Part II: Express Briefs (TCAS-II) represents a new co-publication initiative of the IEEE Circuits and Systems Society (CASS) to publish a selection of the best papers accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS), held in Florence, Italy, on May 27-30, 2018. As TCAS-II only publishes 5-page briefs, and hence both conference and journal (revised) versions of these works would largely overlap, the papers included in this issue that you are holding represent the only record published in IEEE Xplore and they will not appear in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), which will however contain DOI links to the corresponding TCAS-II papers. With this initiative, CASS joins other forward-looking IEEE Societies, namely, the IEEE Robotics and Automation Society and IEEE Control Systems Society, which have developed a similar process for presenting papers submitted to the IEEE Robotics and Automation Letters or to the IEEE Control Systems Letters at ICRA, CASE, or IROS and to CDC, respectively. In a world where the role of a conference is shifting more and more to a networking event and a scientific discussion opportunity, and in which the importance of conference publications is vanishing (except for some specific fields), we consider this opportunity an important step forward for the CASS community.

Impact of TFET Reverse Currents Into Circuit Operation: A Case Study
J. Nuñez
Conference - Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2018
Tunnel FET transistors (TFETs) are one of the most promising candidates to replace CMOS transistors for future integrated circuits. However TFET-based circuit design can exhibit significant limitations due to their reverse conduction currents caused by the direct bias of the intrinsic diode of these transistors. In this paper we analyze in depth this issue through the design of charge pump (DC-DC step up converters) circuits for energy harvesting applications. The proposed solution mitigates the impact of reverse conduction currents and, thus, improves power conversion efficiencies (PCE) compared to previous designs.

A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper - Soft Computing, first online, 2018
SPRINGER    DOI: 10.1007/s00500-018-3150-9    ISSN: 1432-7643    » doi
The knowledge-intensive radiofrequency circuit design and the scarce design automation support play against the increasingly stringent time-to-market demands. Optimization algorithms are starting to play a crucial role; however, their effectiveness is dramatically limited by the accuracy of the evaluation functions of objectives and constraints. Accurate performance evaluation of radiofrequency passive elements, e.g., inductors, is provided by electromagnetic simulators, but their computational cost makes their use within iterative optimization loops unaffordable. Surrogate modeling strategies, e.g., Kriging, support vector machines, artificial neural networks, etc., arise as a promising modeling alternative. However, their limited accuracy in this kind of applications has prevented a widespread use. In this paper, inductor performance properties are exploited to develop a two-step surrogate modeling strategy in order to evaluate the behavior of inductors with high efficiency and accuracy. An automated design flow for radiofrequency circuits using this surrogate modeling of passive components is presented. The methodology couples a circuit simulator with evolutionary computation algorithms such as particle swarm optimization, genetic algorithm or non-dominated sorting genetic algorithm (NSGA-II). This methodology ensures optimal performances within short computation times by avoiding electromagnetic simulations of inductors during the entire optimization process and using a surrogate model that has less than 1% error in inductance and quality factor when compared against electromagnetic simulations. Numerous real-life experiments of single-objective and multi-objective low-noise amplifier design demonstrate the accuracy and efficiency of the proposed strategies.

Embedding MATLAB Optimizers in SIMSIDES for the High-Level Design of ΣΔ Modulators
B. Cortés-Delgadillo, P.A. Rodríguez-Navas, L.I. Guerrero-Linares and J.M. de la Rosa
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, first online, 2018
IEEE    DOI: 10.1109/TCSII.2018.2820900    ISSN: 1549-7747    » doi
This brief shows how to combine SIMSIDES, a SIMULINK-based time-domain behavioral simulator, with different optimization engines available in MATLAB for the automated high-level design of ΣΔ modulators. To this purpose, an updated version of SIMSIDES has been developed, which includes a user-friendly interface that links the simulator with the optimizers, and guides designers through the main steps required to set the design variables, constraints and select the most suitable algorithm to maximize the performance of an arbitrary modulator topology for a given set of specifications. Several examples and results of the optimization procedure are shown to illustrate the benefits of the presented tool for the high-level synthesis of ΣΔ modulators.

Securing Minutia Cylinder Codes for Fingerprints through Physically Unclonable Functions: An Exploratory Study
R. Arjona, M.A. Prada-Delgado, I. Baturone and A. Ross
Conference - International Conference on Biometrics ICB 2018
A number of personal devices, such as smartphones, have incorporated fingerprint recognition solutions for user authentication purposes. This work proposes a dual-factor fingerprint matching scheme based on P-MCCs (Protected Minutia Cylinder-Codes) generated from fingerprint images and PUFs (Physically Unclonable Functions) generated from device SRAMs (Static Random Access Memories). Combining the fingerprint identifier with the device identifier results in a secure template satisfying the discriminability, irreversibility, revocability, and unlinkability properties, which are strongly desired for data privacy and security. Experiments convey the benefits of the proposed dual-factor authentication mechanism in enhancing the security of personal devices that utilize biometric authentication schemes.

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