Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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El IMSE-CNM en Digital.CSIC


 
Publicaciones recientes
In the quest of vision-sensors-on-chip: Pre-processing sensors for data reduction
A. Rodríguez-Vázquez
Conference - IS&T International Symposium on Electronic Imaging 2017
[abstract]
Abstract not available

A CMOS Digital SiPM With Focal-Plane Light-Spot Statistics for DOI Computation
I. Vornicu, F.N. Bandi and R. Carmona-Galán
Journal Paper - IEEE Sensors Journal, vol. 17, no. 3, pp 632-643, 2017
IEEE    DOI: 10.1109/JSEN.2016.2632200    ISSN: 1530-437X     » doi
[abstract]
Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to improve the quality of the positron emission tomography images affected by the parallax error. This paper contemplates the computation of DOI based on the standard deviation of the light distribution. The simulations have been carried out by GAMOS. The design of the proposed digital silicon photomultiplier (d-SiPM) with focal plane detection of the center of mass position and dispersion of the scintillation light is presented. The d-SiPM shares the same off-chip time-to-digital converter such that each pixel can be individually connected to it. A miniature d-SiPM 8×8 single-photon avalanche-diode (SPAD) array has been fabricated as a proof of concept. The SPADs along each row and column are connected through an OR combination technique. It has 256×256μm2 without peripherals circuits and pads. The fill factor is about 11%. The average dark count rate of the mini d-SiPM is of 240 kHz. The average photon detection efficiency is 5% at 480 nm wavelength, room temperature, and 0.9 V excess voltage. The dynamic range is of 96 dB. The sensor array features a time resolution of 212 ps. The photon-timing SNR is 81 dB. The focal plane statistics of the light-spot has been proved as well by measurements.

Black-Box Calibration for ADCs with Hard Nonlinear Errors using a Novel INL-Based Additive Code: A Pipeline ADC Case Study
A.J. Ginés, E.J. Peralías and A. Rueda
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, first online, 2017
IEEE    DOI: 10.1109/TCSI.2017.2662085    ISSN: 1549-8328    » doi
[abstract]
This paper presents a digital nonlinearity calibration technique for ADCs with strong input-output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affecting the ADC's performance. As a solution to this problem, this paper proposes a novel INL-based calibration which incorporates information from the ADC's internal signals to provide a robust estimation of static nonlinear errors for multivalued ADCs. The method is fully generalizable and can be applied to any existing design as long as there is access to internal digital signals. In pipeline or subranging ADCs, this implies access to partial subcodes before digital correction; for algorithmic or SAR ADCs, conversion bit/bits per cycle are used. As a proof-of-concept demonstrator, the experimental results for a 1.2 V 23 mW 130 nm-CMOS pipeline ADC with a SINAD of 58.4 dBc (in nominal conditions without calibration) is considered. In a stressed situation with 0.95 V of supply, the ADC has SINAD values of 47.8 dBc and 56.1 dBc, respectively, before and after calibration (total power consumption, including the calibration logic, being 15.4 mW).

A CMOS Tracking System Approach for Cell Motility Assays
C. Martínez-Gómez, A. Olmo, G. Huertas, P. Pérez, A. Maldonado-Jacobi and A. Yufera
Conference - International Conference on Biomedical Electronics and Devices BIODEVICES 2017
[abstract]
This work proposes a method for studying and monitoring in real-time a single cell on a 2D electrode matrix, of great interest in cell motility assays and in the characterization of cancer cell metastasis. A CMOS system proposal for cell location based on occupation maps data generated from Electrical Cell-substrate Impedance Spectroscopy (ECIS) has been developed. From this cell model, obtained from experimental assays data, an algorithm based on analysis of the 8 nearest neighbors has been implemented, allowing the evaluation of the cell center of mass. The path followed by a cell, proposing a Brownian route, has been simulated with the proposed algorithm. The presented results show the success of the approach, with accuracy over 95% in the determination of any coordinate (x, y) from the expected center of mass.

System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
M. Delgado-Restituto, A. Rodriguez-Perez, A. Darie, C. Soto, E. Fernandez and A. Rodriguez-Vazquez
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, first online, 2017
IEEE    DOI: 10.1109/TBCAS.2016.2618319    ISSN: 1932-4545    » doi
[abstract]
This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction
M. Suárez, V.M. Brea, J. Fernández-Berni, R. Carmona-Galán, D. Cabello and A. Rodríguez-Vázquez
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp 483-495, 2017
IEEE    DOI: 10.1109/JSSC.2016.2610580    ISSN: 0018-9200    » doi
[abstract]
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale invariance, which permits having the same response regardless of the distance of the scene to the camera. The chip comprises 176 x 120 photosensors arranged into 88 x 60 processing elements (PEs). The Gaussian pyramid is generated with a double-Euler switched capacitor (SC) network. Every PE comprises four photodiodes, one 8 b single-slope analog-to-digital converter, one correlated double sampling circuit, and four state capacitors with their corresponding switches to implement the double-Euler SC network. Every PE occupies 44 x 44 μm^2. Measurements from the chip are presented to assess the accuracy of the generated Gaussian pyramid for visual tracking applications. Error levels are below 2% full-scale output, thus making the chip feasible for these applications. Also, energy cost is 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions of imager plus microprocessor unit.

SMASH ΔΣ modulator with adderless feed-forward loop filter
M. Honarparvar, J.M. de la Rosa, F. Nabki and M. Sawan
Journal Paper - IET Electronics Letters, first online, 2017
IET    DOI: 10.1049/el.2016.4733    ISSN: 0013-5194    » doi
[abstract]
A novel cascade ΔΣ modulator, which combines the benefits of SMASH topology and feed-forward loop filter, is presented in this letter. The proposed ΔΣ architecture is based on moving the power-hungry adder block from the quantizer input to the first integrator output. The proposed architecture shows a better OTA linearity and relaxed OTA DC-gain compared to conventional MASH and SMASH topologies. This feature makes the modulator topology more suitable than conventional MASH and SMASH topologies for low-voltage applications.

Novel Multiplierless Wideband Comb Compensator with High Compensation Capability
G. Jovanovic-Dolecek, R. Garcia-Baez, G. Molina-Salgado anf J.M. de la Rosa
Journal Paper - Circuits, Systems, and Signal Processing, vol. 36, no. 5, pp 2031-2049, 2017
SPRINGER    DOI: 10.1007/s00034-016-0398-0    ISSN: 0278-081X    » doi
[abstract]
This paper proposes a novel multiplierless comb compensation filter, which has the absolute passband deviation less than 0.1 dB in the wide passband. The compensator consists of a cascade of two simple filter sections, both operating at a low rate. The magnitude characteristics of the two-component filters are synthesized as sinewave functions, in which the main design parameters correspond to the amplitudes of sinewave functions. A systematic procedure is followed to select synthesis parameters, which depend only on the number of cascaded comb filters. In particular, they are independent of the decimation factor. Comparisons with comb compensators from the literature illustrate the benefits of the proposed design.

On the Use of Offset Calibration Techniques for Low-Power Memristor Arrays Read-Out
C. Mohan, T. Serrano-Gotarredona, J.M. de la Rosa and B. Linares-Barranco
Conference - International Conference on Memristive Materials, Devices & Systems MEMRISYS 2017
[abstract]
Neuromorphic RRAM circuits need typically to drive currents of many mA because the low resistance state is in the order of a few kΩ and many devices need to be activated simultaneously, thereby resulting in high power consumptions. Reducing read-out pulses amplitudes below the typical 0.1V is not trivial, as offset voltages of read-out circuits start to affect the results. This paper presents a calibration circuit to compensate for the resting offset voltage of crossbar lines generated in the amplifiers driving memristive devices in memristor array readout systems. The proposed calibration technique is based on adjusting the bulk voltage of the input differential pairs by means of a switchable cascade of resistor ladders. As a result, the calibrated offset voltage can be further reduced with the number of stages in the cascade, leading to a calibration voltage step below 0.1mV -only limited in practice by mismatch and electrical noise. The circuit has been designed in a 130-nm CMOS technology, and its operation has been verified with oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in neuromorphic circuits. Layout-extracted simulations considering PVT variations are shown to validate the presented calibration technique.

Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
A.J. Acosta, T. Addabbo and E. Tena-Sánchez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 145-169, 2017
JOHN WILEY & SONS    DOI: 10.1002/cta.2296    ISSN: 0098-9886    » doi
[abstract]
We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators. In detail, we discuss the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography, and hash functions, discussing some important security issues in electronic crypto-devices, related to side-channel attacks (SCAs), fault injection attacks, and the corresponding design countermeasures that can be taken. Finally, we present an overview about the hardware implementation of true random number generators, discussing the chief electronic sources of randomness and the types of post-processing techniques used to improve the statistical characteristics of the generated random sequences.

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