Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Guest Editorial Special Issue on the 2019 IEEE International Symposium on Circuits and Systems
J.M. de la Rosa and Y. Nishio
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no.5, pp 717-717, 2019
IEEE    DOI: 10.1109/TCSII.2019.2909179    ISSN: 1549-7747    » doi
[abstract]
This special issue of the IEEE Transactions on Circuits and Systems-Part II: Express Briefs ( TCAS-II ) follows the successful co-publication initiative started last year by the IEEE Circuits and Systems Society (CASS) to publish a selection of the best papers accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS), held this year in Sapporo, Japan, on May 26-29. As TCAS-II only publishes five-page briefs, and hence both conference and journal versions of selected works would be largely overlapped, the papers included in this issue represent the only record published in IEEE Xplore and they will not appear in the Proceedings of IEEE ISCAS , which will however contain DOI links to the corresponding TCAS-II papers. Similar to other IEEE societies, IEEE-CASS intends to shift the role of IEEE conferences toward networking events as well as a scientific discussion opportunity, rather than putting the emphasis on the conference paper publication itself.

Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez
Conference - Design Automation and Test in Europe DATE 2019
[abstract]
Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and timeefficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability.

New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F. V.Fernandez
Conference - Design Automation and Test in Europe DATE 2019
[abstract]
Bias Temperature Instability has become a critical issue for circuit reliability. This phenomenon has been found to have a stochastic and discrete nature in nanometerscale CMOS technologies. To account for this random nature, massive experimental characterization is necessary so that the extracted model parameters are accurate enough. However, there is a lack of automated analysis tools for the extraction of the BTI parameters from the extensive amount of generated data in those massive characterization tests. In this paper, a novel algorithm that allows the precise and fully automated parameter extraction from experimental BTI recovery current traces is presented. This algorithm is based on the Maximum Likelihood Estimation principles, and is able to extract, in a robust and exact manner, the threshold voltage shifts and emission times associated to oxide trap emissions during BTI recovery, required to properly model the phenomenon.

A new time efficient methodology for the massive characterization of RTN in CMOS devices
G. Pedreira, J. Martin-Martinez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
Conference - IEEE International Reliability Physics Symposium IRPS 2019
[abstract]
Abstract not avaliable

A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
Journal Paper - Solid-State Electronics, first online, 2019
ELSEVIER    DOI: 10.1016/j.sse.2019.03.045    ISSN: 0038-1101    » doi
[abstract]
In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.

Flexible Setup for the Measurement of CMOS Time-Dependent Variability with Array-Based Integrated Circuits
J. Diaz-Fortuny, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, F.V. Fernandez and M. Nafria
Journal Paper - IEEE Transactions on Instrumentation and Measurement, first online, 2019
IEEE    DOI: 10.1109/TIM.2019.2906415    ISSN: 0018-9456    » doi
[abstract]
This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically time-consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals.

A Sub- µW Reconfigurable Front-End for Invasive Neural Recording
J.L. Valtierra, R. Fiorelli, M. Delgado-Restituto and A. Rodriguez-Vazquez
Conference - IEEE Latin American Symposium on Circuits and Systems LASCAS 2019
[abstract]
This paper presents a sub-microwatt ac-coupled neural amplifier for the purpose of neural signal sensing. A proposed reconfigurable topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180nm CMOS process draws 803nW from a 1V source. The measured input-referred spot-noise at 150Hz is 130nV / Hz while the integrated noise in the 200Hz-5kHz band is 3.6µV rms.

Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization
A. Yousefzadeh, S. Hosseini, P. Holanda, S. Leroux, T. Werner, T. Serrano-Gotarredona and B. Linares-Barranco, B. Dhoedt and P. Simoens
Conference - IEEE International Conference on Artificial Intelligence Circuits and Systems AICAS 2019
[abstract]
Artificial Neural Networks (ANNs) show great performance in several data analysis tasks including visual and auditory applications. However, direct implementation of these algorithms without considering the sparsity of data requires high processing power, consume vast amounts of energy and suffer from scalability issues. Inspired by biology, one of the methods which can reduce power consumption and allow scalability in the implementation of neural networks is asynchronous processing and communication by means of action potentials, so-called spikes. In this work, we use the wellknown sigma-delta quantization method and introduce an easy and straightforward solution to convert an Artificial Neural Network to a Spiking Neural Network which can be implemented asynchronously in a neuromorphic platform. Briefly, we used asynchronous spikes to communicate the quantized output activations of the neurons. Despite the fact that our proposed mechanism is simple and applicable to a wide range of different ANNs, it outperforms the state-of-the-art implementations from the accuracy and energy consumption point of view. All source code for this project is available upon request for the academic purpose.

A Digital Neuromorphic Realization of the 2-D Wilson Neuron Model
M. Nouri, M. Hayati, T. Serrano-Gotarredona and D. Abbot
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 1, 2019
IEEE    DOI: 10.1109/TCSII.2018.2852598    ISSN: 1549-7747    » doi
[abstract]
This brief presents a piecewise linear approximation of the nonlinear Wilson (NW) neuron model for the realization of an efficient digital circuit implementation. The accuracy of the proposed piecewise Wilson (PW) model is examined by calculating time domain signal shaping errors. Furthermore, bifurcation analyses demonstrate that the approximation follows the same bifurcation pattern as the NW model. As a proof of concept, both models are hardware synthesized and implemented on field programmable gate arrays, demonstrating that the PW model has a range of neuronal behaviors similar to the NW model with considerably higher computational performance and a lower hardware overhead. This approach can be used in hardware-based large scale biological neural network simulations and behavioral studies. The mean normalized root mean square error and maximum absolute error of the PW model are 6.32% and 0.31%, respectively, as compared to the NW model.

Compressive Imaging using RIP-compliant CMOS Imager Architecture and Landweber Reconstruction
M. Trevisi, A. Akbari, M. Trocan, Á. Rodríguez-Vázquez and R. Carmona-Galán
Journal Paper - IEEE Transactions on Circuits and Systems for Video Technology, first online, 2019
IEEE    DOI: 10.1109/TCSVT.2019.2892178    ISSN: 1051-8215    » doi
[abstract]
In this paper we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in compressive sensing CMOS image sensors (CS-CIS) are recursive pseudo-random binary matrices. We have proved that the restricted isometry property (RIP) of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random numbers generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behaviour that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a block-based CS smoothed-projected Landweber (BCS-SPL) reconstruction algorithm. By means of single value decomposition (SVD) we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.

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