Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Phase Synchronization Operator for on-chip Brain Functional Connectivity Computation
M. Delgado-Restituto, J.B. Romaine and A. Rodriguez-Vazquez
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, first online, 2019
IEEE    DOI: 10.1109/TBCAS.2019.2931799    ISSN: 1932-4545    » doi
This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters and adders. The processor, fabricated in a 0.18μm CMOS process, only occupies and consumes 15nW from a 0.5V supply voltage at a signal input rate of 1024S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.

Characterization-Based Modeling of Retriggering and Afterpulsing for Passively Quenched CMOS SPADs
M. Moreno-Garcia, L. Pancheri, M. Perenzonr, R. del Rio, O. Guerra-Vinuesa and A. Rodriguez-Vazquez
Journal Paper - IEEE Sensor Journal, vol. 19, no. 14, pp 5700-5709, 2019
IEEE    DOI: 10.1109/JSEN.2019.2903937    ISSN: 1530-437X    » doi
The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the co-integration of additional electronics for the implementation of complex digital systems on chip. Due to their simplicity, a way to reduce the area occupied by the integrated electronics is the use of passive quenching circuits (PQCs) instead of active (AQCs) or mixed (MQCs) ones. However, the recharge phase in PQCs is slower, so the device can be retriggered before this phase ends. This paper studies the phenomena of afterpulsing and retriggering, depending on the characteristics of the SPADs and the working conditions. In order to do that, a test chip containing SPADs of different size has been characterized in several operating environments. A mathematical model has been proposed for fitting afterpulsing phenomenon. It is shown that retriggering can be also described in terms of this model, suggesting that it is linked to carriers trapped in the shallow levels of the semiconductor and that should be taken into account when considering the total amount of afterpulsing events.

Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC)
A. Rodriguez-Vazquez, K. Sengupta and S. Rusu
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp 1827-1829, 2019
IEEE    DOI: 10.1109/JSSC.2019.2919403    ISSN: 0018-9200    » doi
This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of papers selected from those presented at the 48th ESSCIRC Conference, held at Technische Universität Dresden, Dresden, Germany, during September 3-6, 2018.

Yield recovery of mm-wave power amplifiers using variable decoupling cells and one-shot statistical calibration
F. Cilici, M.J. Barragan, S. Mir, E. Lauga-Larroze, S. Bourdel and G. Leger
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

A sub-μVRMS chopper front-end for ECOG recording
N. Pérez-Prieto, J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path to reduce noise and avoid the implementation of a ripple rejection loop. The prototype was designed in 0.18μm CMOS technology with a 1V supply. Post-layout simulations were carried out showing a power consumption below 2μW and an integrated input-referred noise of 0.75μVrms, with a noise floor below 50 nV/Hz, over a bandwidth from 1 to 200Hz, for a noise efficiency factor of 2.7.

Artifact-aware analogue/mixed-signal front-ends for neural recording applications
N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog front-ends for neural recording applications. These techniques are employed for handling Common-Mode (CM) Differential-Mode (DM) artifacts and include techniques such as Average Template Subtraction, Channel Blanking or Blind Adaptive Stimulation Artifact Rejection (ASAR), among others. Additionally, a new technique for DM artifacts compression is proposed. It allows to compress these artifacts to the requirements of the analog front-end and, afterwards, it allows to reconstruct the whole artifact or largely suppress it.

A current attenuator for efficient memristive crossbars read-out
C. Mohan, J.M. de la Rosa, E. Vianello, L. Perniola, C. Reita, B. Linares-Barranco and T. Serrano-Gotarredona
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
This paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that drive integrate-and-fire neurons, which subsequently allows to reduce the size of integrating capacitors by several orders of magnitude, making IC integration possible. The proposed circuit uses a linear switch to divide the inference current and scale it down by a factor of about 104. The proposed attenuator has been designed in 130nm CMOS technology. Simulation results considering noise, process and temperature variations are shown to validate the presented approach.

Bulk-input VCO-based sigma-delta ADCs with enhanced linearity in 28-nm FD-SOI CMOS
J. Ahmadi-Farsani and J.M. de la Rosa
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
This paper investigates the use of the transistor threshold-voltage tuning feature available in 28-nm Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology in order to improve the performance of Voltage-Controlled Oscillators (VCOs) with application in Analog-to-Digital Converters (ADCs). Circuit techniques that exploit the benefits of the enhanced body-effect biasing tunnability are applied to the proposed VCO in order to improve its linearity, frequency range and robustness to technology-process variations with respect to conventional ring oscillators. The proposed circuit is applied to the design of a second-order ΣΔ ADC clocked at a configurable rate of 1-to-2 GHz. The ADC uses a multi-phase VCO-based front-end integrator as the only analog circuit, while the rest of its building blocks are digital circuits. Transistor-level simulations show that the presented techniques improve the linearity with respect to conventional VCO-based ΣΔMs, featuring 10-bit effective resolution within a 10-MHz signal bandwidth, with an estimated power consumption of 230μW.

TOF estimation based on compressed real-time histogram builder for SPAD image sensors
I. Vornicu, A. Darie, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
This paper presents a FPGA implementation of a novel depth map estimation algorithm for direct time-of-flight CMOS image sensors (dToF-CISs) based on single-photon avalanche-diodes (SPADs). Conventional ToF computation algorithms rely on complete ToF histograms. The next generation of high speed dToF-CIS is expected to have wide dynamic range and high depth resolution. Applications such as 3D imaging based on dToF-CISs require pixel-level ToF histograms which have to be stored by huge fully-random access memory (RAM) modules. The proposed shifted inter-frame histogram (SiFH) algorithm has the same accuracy but requires a memory footprint 128 times smaller than the conventional algorithm. Thus a much larger number of pixels can be resolved using limited block RAM resources of FPGAs. Moreover the overall frame rate is also remarkably improved compared to the scanning method. The proof of concept of the SiFH algorithm on 15 bits has been implemented on Spartan-3E. An automated testbench was developed to confirm that no ambiguity errors occur along the entire dynamic range.

Electrical pulse stimulation of skeletal myoblasts cell cultures with simulated action potentials
P. Villanueva, S. Pereira, A. Olmo, P. Pérez, Y. Yuste, A. Yúfera and F. de la Portilla
Journal Paper - Journal of Tissue Engineering and Regenerative Medicine, vol. 13, no. 7, pp 1265-1269, 2019
JOHN WILEY & SONS    DOI: 10.1002/term.2869    ISSN: 1932-6254    » doi
Electrical pulse stimulation has an important effect on skeletal muscle development and maturation. However, the methodology for controlling these stimulation parameters to develop in vitro functional skeletal muscle tissues remains to be established. In this work, we have studied the effect of simulated action potentials on the growth and differentiation of skeletal myoblast cell cultures. A circuit simulating action potentials of 0.15 and 0.3 V/mm, at a frequency of 1 Hz and with a 4-ms pulse width, is proposed. Results show an important improvement of the growth rate and differentiation of myoblasts at a voltage of 0.15 V/mm. Parameters such as electrodes geometry or type of signals must be considered in the development of in vitro skeletal muscle.

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