IMSE-CNM

Silicon Physical Unclonable Functions (PUFs) have emerged as a promising solution for generating cryptographic keys in low-cost resource-constrained devices. A PUF is expected to be reliable, meaning that its response bits should remain consistent each time the corresponding challenges are queried. Unfortunately, the stability of these challenge-response pairs (CRPs) can be seriously eroded by environmental factors like temperature variations and the aging of the integrated circuits implementing the PUF. Several approaches, including bit masking, bit selection techniques, and error-correcting codes, have been proposed to obtain a reliable PUF operation in the face of temperature variations. As for aging, a new kind of aging-resilient silicon PUF has been reported that uses the time-varying phenomenon known as Random Telegraph Noise (RTN) as the underlying entropy source. Although this type of PUF preserves its reliability well when aged, it is not immune to the impact of temperature variations. The work presented here shows that it is possible to improve the thermal reliability of RTN-based PUFs with a proper combination of (a) a novel optimization-based bit selection technique, that is also applicable to other types of PUFs based on differential measurements; and (b) a temperature-aware tuning of the entropy-harvesting function.

Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and pase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOSspintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.

The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4 configurable logic blocks (CLBs) to accommodate the RO bank.

In alignment with the ethos of openness and democracy inherent in the RISC-V architecture, our research endeavors have been directed towards the utilization of open-source tools for the implementation of a simple but didactic RISC-V processor denoted as ASTIRV32I. The paper discusses the design strategies, memory mapping, physical verification procedures, and performance evaluation of the ASTIRV32I processor. Furthermore, it highlights the successful validation of the implemented design through the execution of fundamental algorithms, exemplifying the practicality and viability of the RISC-V-based processor design and serving as a proof-of-concept for open-source FPGA design.