Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Contratos asignados al Instituto de Microelectrónica de Sevilla en la convocatoria para la contratación de joven personal investigador, en el marco del Sistema Nacional de Garantía Juvenil y del Programa Operativo de Empleo Juvenil (Fase 3).
Plazo de presentación: del día 12 de febrero hasta el 25 de febrero de 2019.   [+info 1] [+info 2]
[15 febrero: corrección de errores, incluyendo ampliación de plazas]
La Universidad de Sevilla ha convocado plazas de voluntariado para cooperación internacional al desarrollo para el proyecto "Transferencia a la Universidad Tecnológica de La Habana de tecnologías avanzadas de diseño de sistemas empotrados sobre hardware reconfigurable".   [+info]
Plazo de presentación: hasta el 27 de febrero de 2019.
♦ Seminario IMSE-Forum
Metodología de marco lógico. Aplicación de la metodología de marco lógico como herramienta de planificación en la redacción de proyectos coherentes y viables, y recomendaciones para el desarrollo de ideas de proyectos.
Carmen Sánchez Ferrer, Project Manager del proyecto ACHIEVE-ITN (CSIC)
31 Enero 2019
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14 Enero 2019

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Últimas publicaciones
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder  »
This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

Journal Paper - International Journal of Circuit Theory and Applications, first online, 2019 JOHN WILEY & SONS
DOI: 10.1002/cta.2594    ISSN: 0098-9886    » doi
A.J. Ginés, E. Peralías, C. Aledo and A. Rueda
Assessing AMS-RF test quality by defect simulation  »
In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on practical cases of study that it is beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality. The computational burden of defect and fault simulations is taken into account and accurate statistical estimates of defect and fault escapes are provided to allow safe early stopping of the simulations.

Journal Paper - IEEE Transactions on Device and Materials Reliability, first online, 2019 IEEE
DOI: 10.1109/TDMR.2019.2894534    ISSN: 1530-4388    » doi
V. Gutierrez, A. Gines and G. Leger
A Multilevel Bottom-up Optimization Methodology for the Automated Synthesis of RF Systems  »
In recent years there has been a growing interest in electronic design automation methodologies for the optimizationbased design of radiofrequency circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle radiofrequency systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this work, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multi-objective optimization algorithms are used to design an entire radiofrequency system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.

Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, first online, 2019 IEEE
DOI: 10.1109/TCAD.2018.2890528    ISSN: 0278-0070    » doi
F. Passos, E. Roca, J. Sieiro, R. Fiorelli, R. Castro-López, J.M. López-Villegas and F.V. Fernández
On the implementation of asynchronous sun sensors  »
Abstract not avaliable

Conference - IS&T International Symposium on Electronic Imaging 2019
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Compact Real-Time Inter-Frame Histogram Builder for 15Bits High-Speed ToF-Imagers based on Single-Photon Detection  »
Time-of-flight image sensors based on single-photon detection, i.e. SPADs, require some filtering of pixel readings. Accurate depth measurements are only possible if the jitter of the detector is mitigated. Moreover, the time stamp needs to be effectively separated from uncorrelated noise such as dark counts and background illumination. A powerful tool for this is building a histogram of a number of pixel readings. Future generation of ToF imagers are seeking to increase spatial and temporal resolution along with the dynamic range and frame rate. Under these circumstances, storing the complete histogram for every pixel becomes practically impossible. Considering that most of the information contained by the histogram represents noise, we propose a highly efficient method to store just the relevant data required for ToF computation. This method makes use of the shifted inter-frame histogram (SifH). It requires a memory as low as 128 times smaller than storing the complete histogram if the pixel values are coded on up to 15 bits. Moreover, a fixed 28 words memory is enough to process histograms containing up to 215 bins. In exchange, the overall frame rate only decreases to one half. The hardware implementation of this algorithm is presented. Its remarkable robustness for a low SNR of the ToF estimation is demonstrated by Matlab simulations and FPGA implementation using input data from a SPAD camera prototype.

Journal Paper - IEEE Sensors Journal, vol. 19, no. 6, pp 2181-2190, 2019 IEEE
DOI: 10.1109/JSEN.2018.2885960    ISSN: 1530-437X    » doi
I. Vornicu, A. Darie, R. Carmona-Galan and A. Rodriguez-Vazquez

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