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♦ Visits to the IMSE
IES San José de la Rinconada
January 11, 2018
♦ Master's Dissertation defense
- Estudio de arquitecturas de ecualización digital embebida en receptores para comunicaciones de Gbps.
Alvaro Díaz García
-Diseño de un circuito conversor para la recolección de energía con dispositivos MEMS piezoeléctricos.
Marcos Duque Duque
- Estudio de convertidor ADC para aplicaciones de espectrometría de bioimpedancias.
Diego Lozano Fernández
- Diseño de filtros balanceados de microondas con doble banda pasante en tecnología microstrip para aplicaciones WLAN.
Pedro J. Ugarte Parrado
December 13, 2017
♦ Visits to the IMSE
IES Profesor Tierno Galván
December 12, 2017
♦ Visits to the IMSE
IES Alixar
November 29, 2017
Researchers at the IMSE-CNM Rosario Arjona, Miguel Angel Prada, Javier Arcenegui and Iluminada Baturone have been recipient of the EAI International Conference on Safety and Security in Internet of Things (SaSeIoT 2017) Best Paper Award.
November 6, 2017

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Recent publications
High-Speed and Low-Cost Implementation of Explicit Model Predictive Controllers  »
This paper presents a new form of piecewise-affine (PWA) solution, referred to as PWA hierarchical (PWAH), to approximate the explicit model predictive control (MPC) law, achieving a very rapid control response with the use of very few computational and memory resources. This is possible because PWAH controllers consist of single-input single-output PWA modules connected in cascade so that the parameters needed to define them increase linearly instead of exponentially with the input dimension of the control problem. PWAH controllers are not universal approximators but several explicit MPC controllers can be efficiently approximated by them. A methodology to design PWAH controllers is presented and validated with application examples already solved by MPC approaches. The designed PWAH controllers implemented in field-programmable gate arrays provide the highest control speed using the fewest resources compared with the other digital implementations reported in the literature.

Journal Paper - IEEE Transactions on Control Systems Technology, first online, 2017 IEEE
DOI: 10.1109/TCST.2017.2775187    ISSN: 1063-6536    » doi
A. Gersnoviez, M. Brox and I. Baturone
Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors  »
Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper, we are covering the modeling, design, and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64x64-pixel array. It has been fabricated in a 0.18 mu m standard CMOS technology. Occupation area is 28x29 mu m(2) and power consumption is 1.17 mW at 850 MHz. The measured gain of the VCRO is of 477 MHz/V with a frequency tuning range of 53%. Moreover, it features a linearity of 99.4% over a wide range of control frequencies, namely, from 400 to 850 MHz. The phase noise is of -102 dBc/Hz at 2 MHz offset frequency from 850 MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147 ps with a rms DNL/INL of 0.13/1.7LSB.

Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 11, pp 2821-2834, 2017 IEEE
DOI: 10.1109/TCSI.2017.2706324    ISSN: 1549-8328    » doi
I. Vornicu, R. Carmona-Galan and Rodriguez-Vazquez
Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion  »
Object tracking is a major problem for many computer vision applications, but it continues to be computationally expensive. The use of bio-inspired neuromorphic event-driven dynamic vision sensors (DVSs) has heralded new methods for vision processing, exploiting reduced amount of data and very precise timing resolutions. Previous studies have shown these neural spiking sensors to be well suited to implementing single-sensor object tracking systems, although they experience difficulties when solving ambiguities caused by object occlusion. DVSs have also performed well in 3-D reconstruction in which event matching techniques are applied in stereo setups. In this paper, we propose a new event-driven stereo object tracking algorithm that simultaneously integrates 3-D reconstruction and cluster tracking, introducing feedback information in both tasks to improve their respective performances. This algorithm, inspired by human vision, identifies objects and learns their position and size in order to solve ambiguities. This strategy has been validated in four different experiments where the 3-D positions of two objects were tracked in a stereo setup even when occlusion occurred. The objects studied in the experiments were: 1) two swinging pens, the distance between which during movement was measured with an error of less than 0.5%; 2) a pen and a box, to confirm the correctness of the results obtained with a more complex object; 3) two straws attached to a fan and rotating at 6 revolutions per second, to demonstrate the high-speed capabilities of this approach; and 4) two people walking in a real-world environment.

Journal Paper - IEEE Transactions on Neural Networks and Learning Systems, first online, 2017 IEEE
DOI: 10.1109/TNNLS.2017.2759326    ISSN: 2162-237X    » doi
L.A. Camunas-Mesa, T. Serrano-Gotarredona, S. Ieng, R. Benosman and B. Linares-Barranco
Digital Implementation of the Two-Compartmental Pinsky-Rinzel Pyramidal Neuron Model  »
It is believed that brain-like computing system can be achieved by the fusion of electronics and neuroscience. In this way, the optimized digital hardware implementation of neurons, primary units of nervous system, play a vital role in neuromorphic applications. Moreover, one of the main features of pyramidal neurons in cortical areas is bursting activities that has a critical role in synaptic plasticity. The Pinsky-Rinzel model is a nonlinear two-compartmental model for CA3 pyramidal cell that is widely used in neuroscience. In this paper, a modified Pinsky-Rinzel pyramidal model is proposed by replacing its complex nonlinear equations with piecewise linear approximation. Next, a digital circuit is designed for the simplified model to be able to implement on a low-cost digital hardware, such as field-programmable gate array (FPGA). Both original and proposed models are simulated in MATLAB and next digital circuit simulated in Vivado is compared to show that obtained results are in good agreement. Finally, the results of physical implementation on FPGA are also illustrated. The presented circuit advances preceding designs with regards to the ability to replicate essential characteristics of different firing responses including bursting and spiking in the compartmental model. This new circuit has various applications in neuromorphic engineering, such as developing new neuroinspired chips.

Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, first online, 2017 IEEE
DOI: 10.1109/TBCAS.2017.2753541    ISSN: 1932-4545    » doi
E. Rahimian, S. Zabihi, M. Amiri and B. Linares-Barranco
Vulnerability Analysis of Trivium FPGA Implementations  »
Today, the large amount of information ex-changed among various devices as well as the growth of the Internet of Things (IoT) demand the development of devices that ensure secure communications, preventing malicious agents from tapping sensitive data. Indeed, information security is one of the key challenges to address within the IoT field. Due to the strong resource constraints in some IoT applications, cryptographic algorithms affording lightweight implementations have been proposed. They constitute the so-called lightweight cryptography. A prominent example is the Trivium stream cipher, one of the finalists of the eSTREAM project. Although cryptographic algorithms are certainly simpler, one of their most critical vulnerability sources in terms of hardware implementations is side channel attacks. In this paper, it is studied the vulnerability of field-programmable gate array (FPGA) implementations of Trivium stream ciphers against fault attacks. The design and implementation of a system that alters the clock signal and checks the outcome is also described. A comparison between real and simulated fault injections is carried out in order to examine their veracity. The vulnerability of different versions of the Trivium cipher and their routing dependences has been tested in two different FPGA families. The results show that all versions of the Trivium cipher are vulnerable to fault attacks, although some versions are more vulnerable than others.

Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp 3380-3389, 2017 IEEE
DOI: 10.1109/TVLSI.2017.2751151    ISSN: 1063-8210    » doi
F.E. Potestad-Ordonez, C.J. Jimenez-Fernandez and M. Valencia-Barrero

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