IMSE-CNM

This work presents an FPGA-based edge-event timing front-end for time-resolved sensing and event-driven measurement scenarios. The proposed design is intended as a detector-independent timing subsystem whose architectural choices are motivated by constraints that are common in single-photon avalanche diode (SPAD)-based and other asynchronous time-resolved sensing workflows, including event trustworthiness, dead-time sensitivity, and constrained downstream readout. Rather than treating the implementation as an isolated interpolation macro, this work evaluates it as an experimentally observable timing subsystem that combines carry-chain-based fine interpolation, coarse-fine timestamp formation, explicit event-quality assessment, dead-time-aware handling, and lightweight host-visible export. The experimental validation is organized around two complementary modes. An internal ILA-based mode is used to verify coherent front-end behavior under MHz-range short-pulse excitation, while a UART-based campaign identifies practical host-visible operating regions through baseline, repeatability, pulse-width, safe-versus-aggressive, and intermediate frequency-sweep experiments. The results identify a safe export-compatible operating point, a more exploratory high-rate regime, and an experimentally interpretable transition between them that, while not strictly monotonic in all metrics, does not exhibit catastrophic degradation across the explored frequency range. Taken together, the measurements indicate that the proposed architecture is best understood not as a best-case standalone time-to-digital (TDC) benchmark but as an experimentally characterized timing front-end whose practical behavior can be interpreted across complementary internal and export-visible operating regimes.

We present a neuromorphic circuit cell that integrates a volatile VO2 neuron with a non-volatile HfO2 memristive synapse, enabling autonomous local plasticity in a compact, CMOS-compatible building block. Unlike conventional neuromorphic implementations where neurons and synapses are separated and coordinated by peripheral circuitry, the HfO2 memristor is embedded directly in the leak path of a VO2 integrate-and-fire neuron. As a result, the neuron's spike dynamics directly modulate the synaptic conductance, which in turn reshapes neuronal excitability. Using experimentally calibrated Verilog-A models and electrical simulations, we demonstrate stable firing-rate adaptation, long-term conductance evolution driven by neuronal activity, and compatibility with standard 1T1R programming schemes. This unified neuron-synapse cell forms a device-circuit primitive where volatile and non-volatile dynamics are co-designed at the cell level, enabling scalable local plasticity without peripheral control circuitry.

In increasingly interconnected systems, security has become a critical concern. In this context, delay-based Physical Unclonable Functions (PUFs), such as Ring Oscillator (RO) PUFs, have emerged as key hardware security primitives by providing unique, unpredictable, and reliable responses, addressing security challenges related to key storage and device authentication. To ensure robustness, RO-PUF designs traditionally resort to analog-driven implementation flows, which suffer from high design overhead and limit scalability across technology nodes. We present a configurable RO-PUF design integrated following a standard-cell-based, fully digital semi-custom-design methodology, significantly reducing design effort while enabling portability across planar CMOS technologies. The proposed architecture integrates fully on-chip Helper Data Algorithm (HDA) combined with a lightweight Error Correction Code (ECC) to support key generation, obfuscation, and recovery. Furthermore, it was fabricated in TSMC 65 nm technology and extensively characterized across diverse operating conditions, including process, voltage, and temperature (PVT) variations, achieving state-of-the-art metrics.

In the current situation of the Internet of Things (IoT) with its billions of interconnected devices, security in this low-resource environment is paramount. A Physical Unclonable Function (PUF) is a very useful cryptographic primitive which allows us to extract unique information from a particular device in a non-reproducible way. This allows us to use a PUF in cryptography for authentication or secret-key generation. Ring Oscillators (ROs) and Transient Effect Ring Oscillators (TEROs) are oscillating structures used in both FPGAs and ASICs to build PUFs. In this paper we present an FPGA implementation of a PUF based on what we call the ’’TERORO’’ cell (TERO + RO), which is a hybrid structure that allows us to use the different functionalities of both RO and TERO in a single building block. We assess all the possible methods of extracting bits of information from the PUF based on TERORO cells. Finally, we tested the circuit and presented experimental results in terms of its uniqueness, uniformity, and reliability. In RO-counter mode, we obtain 49.74% uniqueness, 54.66% uniformity, and 97.81% reliability across devices, while TERO-based XOR mixing achieves 52.83% uniformity, 45.79% uniqueness, and 93.15% reliability. The FPGA footprint is 142 LUTs, 36 registers, and 82 slices.