Instituto de Microelectrónica de Sevilla

Recent publications

How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase
A. Todri-Sanial, S. Carapezzi, C. Delacour, M. Abernot, T. Gil, Elisabetta Corti, S.F. Karg, J. Nüñez, M. Jiménez, M.J. Avedillo and B. Linares-Barranco
Journal Paper · IEEE Transactions on Neural Networks and Learning Systems, first online, 2021
IEEE ISSN: 2162-237X
resumen doi

Brain-inspired computing employs devices and architectures that emulate biological functions for more adaptive and energy-efficient systems. Oscillatory neural networks (ONNs) are an alternative approach in emulating biological functions of the human brain and are suitable for solving large and complex associative problems. In this work, we investigate the dynamics of coupled oscillators to implement such ONNs. By harnessing the complex dynamics of coupled oscillatory systems, we forge a novel computation model--information is encoded in the phase of oscillations. Coupled interconnected oscillators can exhibit various behaviors due to the strength of the coupling. In this article, we present a novel method based on subharmonic injection locking (SHIL) for controlling the oscillatory states of coupled oscillators that allow them to lock in frequency with distinct phase differences. Circuit-level simulation results indicate SHIL effectiveness and its applicability to large-scale oscillatory networks for pattern recognition.

A Plethysmography Capacitive Sensor for Real-Time Monitoring of Volume Changes in Acute Heart Failure
E. Rando, P. Perez, S. Fernandez-Scagliusi, F.J. Medrano, G. Huertas and A. Yufera
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 70, article 4005912, 2021
IEEE ISSN: 0018-9456
resumen doi

A small, wearable, low-weight, and low-power-consumption device for plethysmography capacitive sensing is proposed herein. The device allows carrying out real-time monitoring of leg volume changes in patients suffering from heart failure (HF) conditions. The dynamic of fluid overload in patients with acute HF serves as a prognosis marker for this type of severe disease and, consequently, these patients can benefit from a wearable monitoring system to measure their body volume evolution during and after hospitalization. Our approach is based on contactless capacitive wearable structures implemented by two different sensor realizations located in the ankle: 180°-parallel capacitor plates (two modes of operations are compared, with the patient’s body connected to ground and to the average voltage between plates) and planar-parallel capacitor plates whose overlapped surface varies with the volume of the patient’s leg. Both realizations exhibit good sensitivity to leg volume changes. The acquisition of capacitance values is performed via a simple circuit that achieves notable performance in simulated volume analysis. A preliminary pilot clinical prototype is described as well.

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs
A. Canelas, F. Passos, N. Lourenço, R. Martins, E. Roca, R. Castro-Lopez, N. Horta and F.V. Fernandez
Journal Paper · IEEE Access, vol. 9, pp 124152-124164, 2021
IEEE ISSN: 2169-3536
resumen doi

This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances’ calculation aims for the highest possible accuracy. A surrogate model calculates the performances for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical simulator calculates circuit- and system-level performances. Yield is calculated using Monte-Carlo (MC) analysis with the foundry-provided models without any model approximation. The computation of the circuit yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational requirements during the optimization. The yield of the elements not accurately evaluated is assigned using their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the methodology proposed in this work is compared against other methodologies that do not consider yield throughout the system’s complete hierarchy, demonstrating that it is necessary to consider it over the entire hierarchy to achieve robust optimal designs.

A Configurable RO-PUF for Securing Embedded Systems Implemented on Programmable Devices
M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Brox and S. Sánchez-Solano
Journal Paper · Electronics, vol. 10, no. 16, article 1957, 2021
MDPI ISSN: 2079-9292
resumen doi pdf

Improving the security of electronic devices that support innovative critical services (digital administrative services, e-health, e-shopping, and on-line banking) is essential to lay the foundations of a secure digital society. Security schemes based on Physical Unclonable Functions (PUFs) take advantage of intrinsic characteristics of the hardware for the online generation of unique digital identifiers and cryptographic keys that allow to ensure the protection of the devices against counterfeiting and to preserve data privacy. This paper tackles the design of a configurable Ring Oscillator (RO) PUF that encompasses several strategies to provide an efficient solution in terms of area, timing response, and performance. RO-PUF implementation on programmable logic devices is conceived to minimize the use of available resources, while operating speed can be optimized by properly selecting the size of the elements used to obtain the PUF response. The work also describes the interface added to the PUF to facilitate its incorporation as hardware Intellectual Property (IP)-modules into embedded systems. The performance of the RO-PUF is proven with an extensive battery of tests, which are executed to analyze the influence of different test strategies on the PUF quality indexes. The configurability of the proposed RO-PUF allows establishing the most suitable ‘cost/performance/security-level’ trade-off for a certain application.

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