News


Empowering female talent in science
Empowering female talent in science: a public outreach event at IES Alminar

At IMSE, we carry out various activities to highlight the role of female researchers at our center.
February 13, 2025

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100th anniversary first FET patent
The IMSE hosts a conference to commemorate the centenary of the first FET patent

We are pleased to announce a seminar presented by Fernando Guarín, titled "100th Anniversary of the Transistor and an Overview of the Semiconductor Industry Today."
January 20, 2025

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ChipNation 2024 IMSE
CHIPNATION 2024: IMSE explores opportunities and challenges of neuromorphic technology

IMSE Full Professor of Research Bernabé Linares-Barranco participated as panelist in CHIPNATION 2024, the congress on microelectronics organized by "Asociación Española de la Industria de Semiconductores" – AESEMI, on 2-3 of December 2024 in Valencia.
December 12, 2024

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Buscanidos App IMSE
Buscanidos: play and contribute to the conservation of the Kentish Plover

Since October, the Museo Casa de la Ciencia in Seville has hosted the innovative interactive application Buscanidos, developed by Gustavo Liñán-Cembrano, a researcher at the Instituto de Microelectrónica de Sevilla (IMSE-CNM).
December 4, 2024

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MathWorks drives advanced modeling and design at IMSE
MathWorks drives advanced modeling and design at IMSE

Technicians from MathWorks, a U.S.-based corporation specializing in mathematical computing software, visited IMSE to deliver theoretical and practical workshops on MATLAB.
December 2, 2024

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IMSE participation at European Commission's Science Fair
The IMSE will participate for the second consecutive year in the European Commission's Science Fair

"Science is Wonderful!", the international science fair organized by the European Commission, will take place in Brussels on March 12, 13, and 14, 2025. For the second consecutive year, the event will feature a team of researchers from the Instituto de Microelectrónica de Sevilla (IMSE-CNM).
November 12, 2024

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PREVIOUS EVENTS & NEWS

New Director of the IMSE-CNM


IMSE researcher Teresa Serrano Gotarredona has been appointed as the new Director of the Instituto de Microelectrónica de Sevilla.

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Education at IMSE


- Doctoral Studies
- Master Studies
- Degree Studies
- Final Degree Projects
- Internships

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Recent publications


Exploiting the acousto-optic effect for developing secure digital identifiers
D. Martín-Sánchez and P. Brox
Conference · Moscone South, Room 302 (Level 3), San Francisco, Estados Unidos, 28 Enero 2025
abstract     

Cybersecurity is rooted in hardware to achieve high security. Physical unclonable functions (PUFs) are cryptographic primitives that implement one-way functions to generate cryptographic keys on-demand. Current approaches implement PUFs using microelectronic circuits that exploit the random manufacturing variabilities. Other alternatives exploit optical principles to offer higher security. However, their reliability is compromised by environmental effects and integrated systems are still to be realized. Here a novel approach is proposed to enhance reliability and potentially enable integration in digital security systems. The proposed method uses the acousto-optical effect to interrogate optical PUFs, avoiding precision alignment of moving parts and bulky equipment. This way of interrogating the PUF can also be miniaturized in a photonic integrated circuit. The experimental results demonstrate the feasibility of this approach and the potential for generating a large number of truly random cryptographic keys.

Open Source API for a Hardware Root-of-Trust
E. Camacho-Ruiz, L.F. Rojas-Muñoz, A. Karmakar, P. Navarro-Torrero, P. Brox and M.C. Martínez-Rodríguez
Conference · XVIII Reunión Española de Criptología y Seguridad de la Información, 23-25 octubre 2024, León (España)
abstract     

This paper presents an API designed for a hardware-based Root of Trust that provides a suite of essential cryptographic and security functions based on hardware cryptographic IP cores. The high-level abstraction of the API enables software developers to create secure applications within secure computing systems by leveraging the benefits of hardware IP cores. The hardware IP cores that support the API are compliant with international standards, ensuring robust security and reliability. The API development adheres to the open-source science policies and is published online under a public license. Additionally, the portability of the API across multiple platforms ensures wide compatibility and accessibility, enabling seamless integration and reproducibility.

Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems
P. Navarro-Torrero, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
abstract      doi      

This paper presents the design and implementation of a Karatsuba multiplier to accelerate digital signature schemes on embedded systems. The Karatsuba algorithm is integrated into hardware accelerators for RSA and EdDSA, representing a fundamental component of contemporary, state-of-the-art implementations. A hardware/software co-design methodology is employed, implementing the architectures on a System-onChip platform that combines programmable logic with an ARM processor. The results showcase enhanced resource consumption and timing performance for both signature generation and verification, confirming the superiority of EdDSA over RSA when utilizing the same Karatsuba multiplier core and coding techniques.

VLSI integration of a RO-based PUF into a 65 nm technology
P. Ortega-Castro, L.F. Rojas-Muñoz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
abstract      doi      

Ring Oscillator Physical Unclonable Functions (ROPUFs) take advantage of process variability during the manufacturing process to exploit the small differences in the RO oscillating frequencies and generate unique identifiers (ID). Its structure makes it suitable for, both, FPGA and ASIC applications. This paper presents a RO-PUF implementation using a semi-custom design methodology in TSMC 65 nm technology which has been validated through the entire design process, manufactured and experimentally characterized. Results show a good performance and robustness against temperature and voltage variations while obtaining up to three bits from each execution to generate digital IDs.

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What we do


Our main area of specialization is the design of CMOS analog and mixed-signal integrated circuits and their use in different application contexts such as wireless communications, data conversion, smart imagers & vision sensors, biomedical devices, cybersecurity, neuromorphic computing and space technologies.

The IMSE-CNM staff consists of approximately one hundred people, including scientists and support personnel. IMSE-CNM employees are involved in advancing scientific knowledge, designing high level scientific-technical solutions and in technology transfer.

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