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Materials and Devices Measurement Insights.
May 17, 2018
Dr. Ángel Rodríguez Vázquez, researcher at the IMSE-CNM and professor at the Universidad de Sevilla, has been one of the recipients of 1st Prize for the Transfer of Knowledge of the Universidad de Sevilla, in recognition of his excellent research through contracts with companies and institutions, as brilliant examples of public-private partnership. The awards ceremony took place in the Auditorium of the Universidad de Sevilla on May 3, 2018.    [+info]
Activities presented by the Instituto de Microelectrónica de Sevilla at the 16th Science Fair.
May 3-5, 2018
♦ Doctoral Thesis defense
A Multilevel Approach for the Systematic Design of Radiofrequency Integrated Circuits.
Fabio Moreira de Passos
April 13, 2018
♦ Doctoral Thesis defense
Digital Design for Neuromorphic Bio-Inspired Vision Processing.
Amirreza Yousefzadeh
April 4, 2018
♦ Visits to the IMSE
IES Heliópolis
March 22, 2018

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Recent publications
Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop  »
In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid non-systematic iterations between sizing and layout design steps, a multi-objective optimization-based layout-aware sizing approach with pre-optimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multi-net router with pre-optimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely-used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

Conference - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, first online, 2018
R. Martins, N. Lourenço, F. Passos, R. Povoa, A. Canelas, E. Roca, R. Castro-López, J. Sieiro, F.V. Fernández and N. Horta
Concurrent focal-plane generation of compressed samples from time-encoded pixel values  »
Compressive sampling allows wrapping the relevant content of an image in a reduced set of data. It exploits the sparsity of natural images. This principle can be employed to deliver images over a network under a restricted data rate and still receive enough meaningful information. An efficient implementation of this principle lies in the generation of the compressed samples right at the imager. Otherwise, i. e. digitizing the complete image and then composing the compressed samples in the digital plane, the required memory and processing resources can seriously compromise the budget of an autonomous camera node. In this paper we present the design of a pixel architecture that encodes light intensity into time, followed by a global strategy to pseudo-randomly combine pixel values and generate, on-chip and on-line, the compressed samples.

Conference - Design Automation and Test in Europe DATE 2018
M. Trevisi, H.C. Bandala, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Performance Analysis of Real-Time DNN Inference on Raspberry Pi  »
Deep Neural Networks (DNNs) have emerged as the reference processing architecture for the implementation of multiple computer vision tasks. They achieve much higher accuracy than traditional algorithms based on shallow learning. However, it comes at the cost of a substantial increase of computational resources. This constitutes a challenge for embedded vision systems performing edge inference as opposed to cloud processing. In such a demanding scenario, several open-source frameworks have been developed, e.g. Ca e, OpenCV, TensorFlow, Theano, Torch or MXNet. All of these tools enable the deployment of various state-of-the-art DNN models for inference, though each one relies on particular optimization libraries and techniques resulting in di erent performance behavior. In this paper, we present a comparative study of some of these frameworks in terms of power consumption, throughput and precision for some of the most popular Convolutional Neural Networks (CNN) models. The benchmarking system is Raspberry Pi 3 Model B, a low-cost embedded platform with limited resources. We highlight the advantages and limitations associated with the practical use of the analyzed frameworks. Some guidelines are provided for suitable selection of a speci c tool according to prescribed application requirements.

Conference - SPIE Real-Time Image and Video Processing 2018
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A.Rodríguez-Vázquez
Weighted Time Lag Plot Defect Parameter Extraction and GPU-based BTI Modeling for BTI Variability  »
Abstract not avaliable

Conference - IEEE International Reliability Physics Symposium IRPS 2018
V.M. van Santen, J. Diaz-Fortuny, H. Amrouch, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez, J. Henkel and M. Nafria
A Noise and RTN-Removal Smart Method for the Parameter Extraction of CMOS Aging Compact Models  »
Abstract not avaliable

Conference - Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2018
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria

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Monday, 21 May 2018
Last update: 08.05.2018

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