Instituto de Microelectrónica de Sevilla

Recent publications

Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4
M. Abernot, T. Gil, E. Kurylin, T. Hardelin, A. Magueresse,T. Gonos, M. Jiménez-Través, M.J. Avedillo de Juan and A. Todri-Sanial
Conference · IEEE International Joint Conference on Neural Networks IJCNN 2022
resumen

Neuromorphic computing aims to emulate biological neural functions to overcome the memory bottleneck challenges with the current Von Neumann computing paradigm by enabling efficient and low-power computations. In recent years, there has been a tremendous engineering effort to bring neuromorphic computing for processing at the edge. Oscillatory Neural Networks (ONNs) are braininspired neural networks made of oscillators to mimic neuronal brain waves, typically visible on Electroencephalograms (EEG). ONNs provide massive parallelism using coupled oscillators and low power computation using oscillator phase dynamics. In this paper, we present for the first time how to use ONNs to perform obstacle avoidance on a mobile robot. Digitally implemented ONNs on FPGA are used and configured for obstacle avoidance inside the industrial surveillance robot E4 from the company, A.I.Mergence. We show that ONNs can perform real-time obstacle avoidance based on the sensory data from proximity sensors embedded on the E4 robot. The highly parallel architecture of ONNs not only allows fast real-time computation for obstacle avoidance applications but also opens up a novel computing paradigm for edge AI to enable low power and real-time sensing to action computing.

Special Session on RF/5G Test
W.R. Eisenstadt, M. Roos, D. Morris, J.L. Gonzalez-Jimenez, C. Mounet, M.J. Barragan, G. Leger, F. Cilici, E. Lauga-Larroze, S. Mir, S. Bourdel, M. Margalef-Rovira, I. Alaji, H. Ghanem, G. Ducournau and C. Gaquiere
Conference · IEEE European Test Symposium ETS 2022
resumen

Abstract not available

A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · Sensors, vol. 22, no. 17, article 6429, 2022
MDPI ISSN: 1424-8220
resumen doi

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm(2). Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode-tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology's nominal supply, (2) residual charge-without passive discharging phase-was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

Hardware/Software Co-Design of a Circle Detection System based on Evolutionary Computing
L.F. Rojas-Munoz, H. Rostro-Gonzalez, C.H. Garcia-Capulin and S. Sanchez-Solano
Journal Paper · Electronics, vol. 11, no. 17, article 2686, 2022
MDPI ISSN: 2079-9292
resumen doi

In recent years, the strategy of co-designing Hardware/Software (HW/SW) systems has been widely adopted to exploit the synergy between both approaches thanks to technological advances that have led to more powerful devices providing an increasingly better cost-benefit trade-off. This paper presents an HW/SW system for the detection of multiple circles in digital images based on a genetic algorithm. It is implemented on an Ultra96-v2 development board, which contains a Xilinx Zynq UltraScale+ MPSoC device and supports a Linux operating system that facilitates application development. The design is powered by developing an interactive computing environment by means of the Jupyter Notebook platform, in which different programming languages coexist. The specific advantages of each of these languages have been used to describe the hardware component that accelerates the evolutionary computation for circle detection (VHDL), to execute SW-HW interaction functions, as well as the pre- and post-processing of the images (ANSI-C) and to code, evaluate, and document the system execution process (Python). As a result, a computationally efficient application was obtained, with high accuracy in the detection of circles in synthetic and real images, and with a high degree of reconfigurability that provides the user with the necessary tools to incorporate it in a specific area of interest.

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