Visual Inference for IoT Systems: A Practical Approach
D. Velasco-Montero, J. Fernández-Berni and A. Rodríguez-Vázquez
Book · 145 p, 2022
SPRINGER ISBN: 978-3-030-90903-1
This book presents a systematic approach to the implementation of Internet of Things (IoT) devices achieving visual inference through deep neural networks. Practical aspects are covered, with a focus on providing guidelines to optimally select hardware and software components as well as network architectures according to prescribed application requirements.
The monograph includes a remarkable set of experimental results and functional procedures supporting the theoretical concepts and methodologies introduced. A case study on animal recognition based on smart camera traps is also presented and thoroughly analyzed. In this case study, different system alternatives are explored and a particular realization is completely developed.
Illustrations, numerous plots from simulations and experiments, and supporting information in the form of charts and tables make Visual Inference and IoT Systems: A Practical Approach a clear and detailed guide to the topic. It will be of interest to researchers, industrial practitioners, and graduate students in the fields of computer vision and IoT.
Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA
F.E. Potestad-Ordonez, E. Tena-Sanchez, J.M. Mora-Gutierrez, M. Valencia-Barrero and C.J. Jimenez-Fernandez
Journal Paper · IEEE Access, vol. 9, pp 168444-168454, 2021
IEEE ISSN: 2169-3536
Attacks on cryptocircuits are becoming increasingly sophisticated, requiring designers to include more and more countermeasures in the design to protect it against malicious attacks. Fault Injection Attacks and Differential Fault Analysis have proven to be very dangerous as they are able to retrieve the secret information contained in cryptocircuits. In this sense, Trivium cipher has been shown to be vulnerable to this type of attack. This paper presents four different fault detection schemes to protect Trivium stream cipher implementations against fault injection attacks and differential fault analysis. These countermeasures are based on the introduction of hardware redundancy and signature analysis to detect fault injections during encryption or decryption operations. This prevents the attacker from having access to the faulty key stream and performing differential fault analysis. In order to verify the correct operation and the effectiveness of the presented schemes, an experimental system of non-invasive active attacks using the clock signal in FPGA has been designed. This system allows to know the fault coverage for both multiple and single faults. In addition, the results of area consumption, frequency degradation, and fault detection latency for FPGA and ASIC implementations are presented. The results show that all proposed countermeasures are able to provide a fault coverage above 79% and one of them reaches a coverage of 99.99%. It has been tested that the number of cycles for fault detection is always lower than the number of cycles needed to apply the differential fault analysis reported in the literature for the Trivium cipher.
A Reduced-scale Cortical Network with Izhikevich's Neurons on SpiNNaker
C. Chiplunkar, N. Gautam, I. Mediratta,A. Gait, S. Thomas, A. Rowley, T. Serrano-Gotarredona and B. Sen-Bhattacharya
Conference · IEEE International Joint Conference on Neural Networks IJCNN 2021
Following the initial implementation of a full-scale spiking neural network (SNN) of the cortical microcircuit on NEST, the work was replicated to simulate on SpiNNaker, the Juelich CPU cluster, and the Sussex GPU cluster, in order to compare the performances on the different platforms. All of these researches use the Leaky Integrate and Fire (LIF) model as the basic unit of spiking neurons. In comparison, Izhikevich's spiking neuron models (IZK) can mimic a larger variety of known cortical neuronal dynamics. In spite of this versatility, the IZK neuron is easy to implement and computes fast. In this work, we implement the above-mentioned cortical micro-circuit at a reduced-scale and using IZK neurons on SpiNNaker. This is aligned with our ongoing research on a reduced-scale thalamocortical circuit of vision with changing IZK neuron dynamics on SpiNNaker. We validate our SNN with the LIF-based full-scale cortical microcircuit by providing Poisson noise inputs, and measuring objectively the outputs in terms of spike rate, irregularity and synchrony. Our reduced-scale SNN shows similar dynamics to the full-scale SNN and operates within the Asynchronous Irregular regime defined by set bounds on the three quantitative attributes. Next, we test our SNN with inputs from a Dynamic Vision Sensor- (DVS-)based electronic retina (e-retina) that converted a simple periodic environmental input to spike trains. With current parameter settings, the model output identifies the low-frequency, but not the high frequency periodic inputs.
A Neuromorphic CMOS Circuit with Self-Repairing Capability
E. Rahiminejad, F. Azad, A. Parvizi-Fard, M. Amiri and B. Linares-Barranco
Journal Paper · IEEE Transactions on Neural Networks and Learning Systems, first online, 2021
IEEE ISSN: 2162-237X
Neurophysiological observations confirm that the brain not only is able to detect the impaired synapses (in brain damage) but also it is relatively capable of repairing faulty synapses. It has been shown that retrograde signaling by astrocytes leads to the modulation of synaptic transmission and thus bidirectional collaboration of astrocyte with nearby neurons is an important aspect of self-repairing mechanism. Specifically, the retrograde signaling via astrocyte can increase the transmission probability of the healthy synapses linked to the neuron. Motivated by these findings, in the present research, a CMOS neuromorphic circuit with self-repairing capabilities is proposed based on astrocyte signaling. In this way, the computational model of self-repairing process is hired as a basis for designing a novel analog integrated circuit in the 180-nm CMOS technology. It is illustrated that the proposed analog circuit is able to successfully recompense the damaged synapses by appropriately modifying the voltage signals of the remaining healthy synapses in the wide range of frequency. The proposed circuit occupies 7500- µm² silicon area and its power consumption is about 65.4 µW. This neuromorphic fault-tolerant circuit can be considered as a key candidate for future silicon neuronal systems and implementation of neurorobotic and neuro-inspired circuits.