The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a single-photon avalanche-diode (SPAD) array with an in-pixel time-to-digital converter (TDC) must contemplate system-level aspects that affect its overall performance. This paper provides a detailed analysis of the impact of process parameters, voltage supply, and temperature (PVT) variations on the time bin of the TDC array. Moreover, the design and characterization of a global compensation loop is presented. It is based on a phase locked loop (PLL) that is integrated on-chip. The main building block of the PLL is a voltage-controlled ring-oscillator (VCRO) that is identical to the ones employed for the in-pixel TDCs. The reference voltage that drives the master VCRO is distributed to the voltage control inputs of the slave VCROs such that their multiphase outputs become invariant to PVT changes. These outputs act as time interpolators for the TDCs. Therefore the compensation scheme prevents the time bin of the TDCs from drifting over time due to the aforementioned factors. Moreover, the same scheme is used to program different time resolutions of the direct time-of-flight (ToF) imager aimed at 3D ranging or depth map imaging. Experimental results that validate the analysis are provided as well. The compensation loop proves to be remarkably effective. The spreading of the TDCs time bin is lowered from: (i) 20% down to 2.4% while the temperature ranges from 0 °C to 100 °C; (ii) 27% down to 0.27%, when the voltage supply changes within ±10% of the nominal value; (iii) 5.2 ps to 2 ps standard deviation over 30 sample chips, due to process parameters´ variation.

Journal Paper - Sensors, vol. 17, no. 5, 1072, 2017 MDPI
DOI: 10.3390/s17051072    ISSN: 1424-8220    » doi

We report a high dynamic range (HDR) image sensor with a linear response that overcomes some of the limitations of sensors with pixels with self-reset operation. It operates similar to an active pixel sensor, but its pixels have a novel asynchronous event-based overflow detection mechanism. Whenever the pixel voltages at the integration capacitance reach a programmable threshold, the pixels self-reset and send out asynchronously an event indicating this. At the end of the integration period, the voltage at the integration capacitance is digitized and readout. Combining this information with the number of events fired by each pixel, it is possible to render linear HDR images. Event operation is transparent to the final user. There is no limitation for the number of self-resets of each pixel. The output data format is compatible with frame-based devices. The sensor was fabricated in the AMS 0.18-μm HV technology. A detailed system description and experimental results are provided in this paper. The sensor can render images with an intra-scene dynamic range of up to 130 dB with linear outputs. The pixels' pitch is 25 μm and the sensor power consumption is 58.6 mW.

Journal Paper - IEEE Journal of Solid-State Circuits, first online, 2017 IEEE
DOI: 10.1109/JSSC.2017.2679058    ISSN: 0018-9200    » doi

A tunnel field-effect transistor (TFET)-based pixel circuit for well capacity adjustment that does not require subthreshold operation on the part of the reset transistor is presented. In CMOS, this subthreshold operation leads to temporal noise, distortion and fixed pattern noise, becoming a primary limiting performance factor. In the proposed circuit, the asymmetric conduction associated with TFETs is exploited. This property, arising from the inherent physical structure of the device, provides the selective well adjustments during photo-integration which are demanded for achieving high dynamic range. A GaN-based heterojunction TFET has been designed according to the specific requirements for this application.

Journal Paper - Electronics Letters, vol.53, no. 9, pp 622-624, 2017 IEEE
DOI: 10.1049/el.2016.4548    ISSN: 0013-5194     » doi

Piecewise linear one-dimensional maps have been proposed as the basis for low-power analog and mixed-signal true random number generators (TRNGs). Recent research has moved towards conceiving maps that operate robustly under the consideration of parameter variations. In this paper, we introduce an oscillator circuit mapping a low-complexity map known as the skew-tent. This oscillator is employed as the basis for a TRNG scheme. Simulation results in TSMC 0.18 μm validate the chaotic oscillator and the randomness of the TRNG scheme is verified with the NIST test suite 800-22.

Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 305-315, 2017 JOHN WILEY & SONS
DOI: 10.1002/cta.2305    ISSN: 0098-9886    » doi

Abstract not avaliable

Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 143-144, 2017 JOHN WILEY & SONS
DOI: 10.1002/cta.2302    ISSN: 0098-9886    » doi