News


IMSE researcher dataset
An IMSE researcher among the authors of one of the largest Digital CSIC datasets

Gustavo Liñán-Cembrano, IMSE researcher, is listed as the main researcher and has been responsible for the technological part of a dataset with nearly one million images.
July 10, 2024

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UIMP Summer course
Registration open for the UIMP summer course "Data in research: challenges and opportunities"

The training will take place on August 26, 27 and 28 in the Península de la Magdalena, Santander.
July 5, 2024

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Danilo Dermarchi visit
Danilo Demarchi visits the IMSE to discuss innovation in agri-food systems

The Italian professor offered a colloquium about the modernization of the links in the food chain, placing special emphasis on the role of Artificial Intelligence.
July 1, 2024

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Workshop Red DEDOSS
The IMSE, present at the DEDOSS Network workshop in Cáceres

The event brought together researchers from different Schools and Universities, who exchanged ideas and proposals on the use of computers in different research fields.
June 27, 2024

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MSCA-PF 2024 IMSE
We are waiting for you: apply now for a Marie Sklodowska-Curie Fellowship 2024

Would you like to do research on any of ours lines at the Instituto de Microelectrónica de Sevilla (IMSE-CNM)? We are looking for highly motivated post-doctotal researchers with outstanding academic records to apply for the MSCA-PF 2024.

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IMSE ASPIRA MaX award
The IMSE, awarded the ASPIRA MaX CSIC distinction of excellence

On this occasion, 40 new Josefa Barba badges were awarded to the Institutes and Centers (ICUs) of the CSIC, including the Instituto de Microelectrónica de Sevilla IMSE-CNM).
June 14, 2024

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PREVIOUS EVENTS & NEWS

New Director of the IMSE-CNM


IMSE researcher Teresa Serrano Gotarredona has been appointed as the new Director of the Instituto de Microelectrónica de Sevilla.

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Education at IMSE


- Doctoral Studies
- Master Studies
- Degree Studies
- Final Degree Projects
- Internships

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Recent publications


Exploiting randomly distributed pores in photonic structures for security applications to create hardware-based digital identity
D. Martín-Sánchez and P. Brox
Conference · NanoSpain Conf 2024, Tarragona, España
abstract     

In the 2024 edition, the conference will strength collaborations with the COST network Netpore in the field of porous semiconductors and oxides. The intersection of nanoSpain2024 and the thematic network COST will encourage collaborative dialogues and the initiation of potential partnerships between researchers and industry professionals. More info at https://www.nanospainconf.org/2024

A CMOS-compatible oscillation-based VO2 Ising machine solver
O. Maher, M. Jiménez, C. Delacour, N. Harnack, J. Núñez, M.J. Avedillo, B. Linares-Barranco, A. Todri-Sanial, G. Indiveri and S. Karg
Journal Paper · Nature Communications vol. 15, article 3334, 2024
NATURE    ISSN: 2041-1723
abstract      doi      

Phase-encoded oscillating neural networks offer compelling advantages over metal-oxide-semiconductor-based technology for tackling complex optimization problems, with promising potential for ultralow power consumption and exceptionally rapid computational performance. In this work, we investigate the ability of these networks to solve optimization problems belonging to the nondeterministic polynomial time complexity class using nanoscale vanadium-dioxide-based oscillators integrated onto a Silicon platform. Specifically, we demonstrate how the dynamic behavior of coupled vanadium dioxide devices can effectively solve combinatorial optimization problems, including Graph Coloring, Max-cut, and Max-3SAT problems. The electrical mappings of these problems are derived from the equivalent Ising Hamiltonian formulation to design circuits with up to nine crossbar vanadium dioxide oscillators. Using sub-harmonic injection locking techniques, we binarize the solution space provided by the oscillators and demonstrate that graphs with high connection density (μ > 0.4) converge more easily towards the optimal solution due to the small spectral radius of the problema’s equivalent adjacency matrix. Our findings indicate that these systems achieve stability within 25 oscillation cycles and exhibit power efficiency and potential for scaling that surpasses available commercial options and other technologies under study. These results pave the way for accelerated parallel computing enabled by large-scale networks of interconnected oscillators.

Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
abstract      doi      

This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.

A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing
M. Srivastava, A. Ferro, A. Sidun, P. Cantillon-Murphy, Daniel O’Hare, K. O’Donoghue and J.M. de la Rosa
Journal Paper · IEEE Open Journal of Circuits and Systems (Volume 5), 2024
IEEE    ISSN: 2644-1225
abstract      doi      

This work presents a small-area 2nd-order continuous-time ΔΣ Modulator (CTΔΣM) with a single low dropout regulator (LDO) serving as both the power supply for the CTΔΣM and reference voltage buffer. The CTΔΣM is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and Vref for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CTΔΣM consumes 300 μW of power when clocked at 10.24 MHz. The CTΔΣM achieves a state-of-the-art area of 0.07 mm.

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IMSE corporate video


What we do


Our main area of specialization is the design of CMOS analog and mixed-signal integrated circuits and their use in different application contexts such as wireless communications, data conversion, smart imagers & vision sensors, biomedical devices, cybersecurity, neuromorphic computing and space technologies.

The IMSE-CNM staff consists of approximately one hundred people, including scientists and support personnel. IMSE-CNM employees are involved in advancing scientific knowledge, designing high level scientific-technical solutions and in technology transfer.

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