Spanish National Research Council · University of Seville
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The company Digilent Inc, in collaboration with the Seville Institute of Microelectronics and the Escuela Politécnica Superior of the Universidad de Sevilla will give the following workshops in June.
- Accelerate real-time high definition video processing designs with Digilent Zybo Z7, a Zynq-7000 AP SoC Platform and Xilinx Vivado HLS.
- Hands-on experimentation using Digilent Analog Discovery 2. Complete analog & digital circuits in or out of the lab.
June 17-18, 2019
♦ Mac Van Valkenburg Award 2019
Dr. Ángel Rodríguez Vázquez, researcher at the IMSE-CNM and professor at the Universidad de Sevilla, has been recipient of the Mac Van Valkenburg Award for fundamental contributions to mixed-signal chip architectures for smart imaging, vision and 2-D data processing. The award is based on the quality and significance of contribution, and continuity of technical leadership.. The awards ceremony will take place in the ISCAS 2019 Conference on May 28, 2019.
Activities presented by the Instituto de Microelectrónica de Sevilla at the 17th Science Fair.   [imágenes]
May 16-18, 2019
The President of the CSIC Dª Rosa Menéndez López, accompanied by the Delegate of the CSIC in Andalusia Dª Margarita Paneque Sosa, has visited the Instituto de Microelectrónica de Sevilla, in the scope of the visits that is carrying out to the centers of the CSIC distributed throughout the national territory.
April 25, 2019

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Recent publications
Guest Editorial Special Issue on the 2019 IEEE International Symposium on Circuits and Systems  »
This special issue of the IEEE Transactions on Circuits and Systems-Part II: Express Briefs ( TCAS-II ) follows the successful co-publication initiative started last year by the IEEE Circuits and Systems Society (CASS) to publish a selection of the best papers accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS), held this year in Sapporo, Japan, on May 26-29. As TCAS-II only publishes five-page briefs, and hence both conference and journal versions of selected works would be largely overlapped, the papers included in this issue represent the only record published in IEEE Xplore and they will not appear in the Proceedings of IEEE ISCAS , which will however contain DOI links to the corresponding TCAS-II papers. Similar to other IEEE societies, IEEE-CASS intends to shift the role of IEEE conferences toward networking events as well as a scientific discussion opportunity, rather than putting the emphasis on the conference paper publication itself.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no.5, pp 717-717, 2019 IEEE
DOI: 10.1109/TCSII.2019.2909179    ISSN: 1549-7747    » doi
J.M. de la Rosa and Y. Nishio
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator  »
Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and timeefficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability.

Conference - Design Automation and Test in Europe DATE 2019
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors  »
Bias Temperature Instability has become a critical issue for circuit reliability. This phenomenon has been found to have a stochastic and discrete nature in nanometerscale CMOS technologies. To account for this random nature, massive experimental characterization is necessary so that the extracted model parameters are accurate enough. However, there is a lack of automated analysis tools for the extraction of the BTI parameters from the extensive amount of generated data in those massive characterization tests. In this paper, a novel algorithm that allows the precise and fully automated parameter extraction from experimental BTI recovery current traces is presented. This algorithm is based on the Maximum Likelihood Estimation principles, and is able to extract, in a robust and exact manner, the threshold voltage shifts and emission times associated to oxide trap emissions during BTI recovery, required to properly model the phenomenon.

Conference - Design Automation and Test in Europe DATE 2019
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F. V.Fernandez
A new time efficient methodology for the massive characterization of RTN in CMOS devices  »
Abstract not avaliable

Conference - IEEE International Reliability Physics Symposium IRPS 2019
G. Pedreira, J. Martin-Martinez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models  »
In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.

Journal Paper - Solid-State Electronics, first online, 2019 ELSEVIER
DOI: 10.1016/j.sse.2019.03.045    ISSN: 0038-1101    » doi
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria

IMSE-related sites
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Tuesday, 21 May 2019
Last update: 21.05.2019

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