Publications | Instituto de Microelectrónica de Sevilla

Found results matching for:

Author: José M. de la Rosa Utrera
Year: Since 2002

Journal Papers

On the Use of Open-Source EDA Tools for Teaching and Learning Microelectronics
I. Galán-Benítez, R. Carmona-Galán and J.M. de la Rosa
Journal Paper · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
abstract doi

This work proposes the use of open-source Electronic Design Automation (EDA) tools as a didactic instrument in undergraduate and master courses dealing with the design of analog, mixed-signal and digital Integrated Circuits (ICs). The aim is to make it easier for students to get familiar with the whole IC design flow within a real-word application framework, without being limited by licenses or financial barriers imposed by commercial proprietary Computer-Aided Design (CAD) tools. An overview of main tools, design environments and technology processes is given based on the exploratory study carried out within the framework of two master theses. These tools can be easily installed and employed by students to design and verify analog, mixed-signal and digital circuits and Systems-on-Chip (SoC) prototypes. As a case study, a RISC-V processor architecture has been synthesized down to layout level by a master student, to demonstrate the capabilities of these open-source tools to teach and learn microelectronics11This work was supported in part by Grants PID2019-103876RB-I00, PID2021-128009OB-C31, PID2022-138078OB-I00, and PDC2023-145808-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future and by ERDF A way of making Europe..

Live Demonstration: Using ANNs to Predict the Evolution of Spectrum Occupancy
G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
abstract doi

This demo shows how to use Artificial Neural Networks (ANNs) to identify and predict the evolution of vacant portions or frequency holes of the radio spectrum with application in Software-Defined-Radio (SDR) and Cognitive-Radio (CR) systems. To this purpose, different kinds of ANNs - including Convolutional Neural Networks (CNNs), Long Short-Term Memory (LSTM) networks and hybrid combinations of them - are trained and tested with experimental datasets taken from measurements of the frequency spectrum. Trained ANNs are embedded in an IoT device based on a Rasperry Pi and connected with a SDR board to detect the activity of Radio-Frequency (RF) signals around the frequency band of 2.4GHz, shared by several wireless standards such as Bluetooth and WiFi. This hardware demonstrator operates in real time and is able to detect in advance which portions of this frequency band will be less occupied, thus showing their potential application in SDR/CR terminals. ISCAS Track: Analog Signal Processing.

Live Demonstration: Automated Design of Analog and Mixed-Signal Circuits Using Neural Networks
G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
abstract doi

This demo shows how to use Artificial Neural Networks (ANNs) for the optimization and automated design of analog and mixed-signal circuits. A step-by-step procedure is demonstrated to explain the key and practical aspects to consider in this approach, such as dataset preparation, ANNs modeling, training, and optimization of network hyperparameters. Two case studies at different abstraction levels are presented. The first one is the system-level sizing of Sigma-Delta Modulators (ΣΔMs), where ANNs are combined with behavioral simulations to generate valid circuit-level design variables for a given set of specifications. The second example combines ANNs with electrical simulators to optimize the circuit-level design of operational transconductance amplifiers. The methods and tools shown in the demo can be used for the optimization of any arbitrary analog and mixed-signal integrated circuits and systems 1 .ISCAS Track: Analog Signal Processing.

A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing
M. Srivastava, A. Ferro, A. Sidun, P. Cantillon-Murphy, Daniel O’Hare, K. O’Donoghue and J.M. de la Rosa
Journal Paper · IEEE Open Journal of Circuits and Systems (Volume 5), 2024
abstract doi

This work presents a small-area 2nd-order continuous-time ΔΣ Modulator (CTΔΣM) with a single low dropout regulator (LDO) serving as both the power supply for the CTΔΣM and reference voltage buffer. The CTΔΣM is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and Vref for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CTΔΣM consumes 300 μW of power when clocked at 10.24 MHz. The CTΔΣM achieves a state-of-the-art area of 0.07 mm.

A Control-Bounded Quadrature Leapfrog ADC
H. Malmberg, F. Feyling and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, 2024
abstract doi

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated. A band-pass analog-to-digital converter is considered as an application and case study. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations on several filter orders, center frequencies, and oversampling ratios. Additionally, we consider an op-amp circuit realization where the effects of first-order op-amp non-idealities are shown. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.

On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators
P. Díaz-Lobo, G. Liñán-Cembrano and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
abstract doi

This paper presents a high-level synthesis methodology for Sigma-Delta Modulators (ΣΔ Ms) that combines behavioral modeling and simulation for performance evaluation, and Artificial Neural Networks (ANNs) to generate high-level designs variables for the required specifications. To this end, comprehensive datasets made up of design variables and performance metrics, generated from accurate behavioral simulations of different kinds of ΣΔ Ms, are used to allow the ANN to learn the complex relationships between design-variables and specifications. Several representative case studies are considered, including single-loop and cascade architectures with single-bit and multi-bit quantization, as well as both Switched-Capacitor (SC) and Continuous-Time (CT) circuit techniques. The proposed solution works in two steps. First, for a given set of specifications, a trained classifier proposes one of the available ΣΔ M architectures in the dataset. Second, for the proposed architecture, a Regression-type Neural Network (RNN) infers the design variables required to produce the requested specifications. A comparison with other optimization methods - such as genetic algorithms and gradient descent - is discussed, demonstrating that the presented approach yields to more efficient design solutions in terms of performance metrics and CPU time.

On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators
J. Gorji, S. Pavan and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
abstract doi

This paper presents a new architecture for bandpass delta-sigma modulators (BP-ΔΣMs) featuring finite impulse response (FIR) filters in the feedback path. The effectiveness of FIR feedback in lowpass delta-sigma modulators (LP-ΔΣMs) has been well-established in improving loop-filter linearity and robustness to clock jitter. Building upon these findings, we explore the application of bandpass FIR filters in single-bit BP-ΔΣMs. By contrast to conventional BP-ΔΣMs, the proposed technique significantly reduces out-of-band quantization error contents in the feedback signal. This approach is applicable to both discrete-time and continuous-time implementations. Further, we show that performance does not improve by increasing the number of FIR taps beyond a certain point. However, we can enhance filtering performance by employing non-equal coefficients within the filter. To validate the efficacy of the presented approach, the paper includes electrical simulation of a 4th-order active-RC BP-ΔΣM.

Combining Software-Defined Radio Learning Modules and Neural Networks for Teaching Communication Systems Courses
L.A. Camuñas-Mesa and J.M. de la Rosa
Journal Paper · Information, vol. 14, no. 11, article 599, 2023
abstract doi

The paradigm known as Cognitive Radio (CR) proposes a continuous sensing of the electromagnetic spectrum in order to dynamically modify transmission parameters, making intelligent use of the environment by taking advantage of different techniques such as Neural Networks. This paradigm is becoming especially relevant due to the congestion in the spectrum produced by increasing numbers of IoT (Internet of Things) devices. Nowadays, many different Software-Defined Radio (SDR) platforms provide tools to implement CR systems in a teaching laboratory environment. Within the framework of a ’Communication Systems’ course, this paper presents a methodology for learning the fundamentals of radio transmitters and receivers in combination with Convolutional Neural Networks (CNNs).

Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief,
G. Liñán-Cembrano, N. Lourenço, N. Horta and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
abstract doi

This tutorial brief shows how Artificial Neural Networks (ANNs) can be used for the optimization and automated design of analog and mixed-signal circuits. A survey of conventional and computational-intelligence design methods is given as a motivation towards using ANNs as optimization engines. A step-by-step procedure is described explaining the key aspects to consider in our approach, such as dataset preparation, ANNs modeling, training, and optimization of network hyperparameters. As an application, two case studies at different hierarchy levels are presented. The first one is the system-level sizing of Sigma-Delta Modulators (ΣMs), where ANNs are combined with behavioral simulations to generate valid circuit-level design variables for a given set of specifications. The second example combines ANNs with electrical simulators to optimize the circuit-level design of operational transconductance amplifiers. The results validate the presented approach and show its benefits with respect to prior art on synthesis methods of analog and mixed-signal circuits and systems.

High-Level Design of Sigma-Delta Modulators using Artificial Neural Networks
P. Díaz-Lobo and J.M. de la Rosa
Journal Paper · IEEE International Symposium on Circuits and Systems ISCAS 2023
abstract doi

This paper analyses the use of Artificial Neural Networks (ANNs) for the high-level synthesis and design of Sigma-Delta Modulators (ΣΔMs) . The presented methodology is based on training ANNs to identify optimum design patterns, so that they can learn to predict the best set of design variables for a given set of specifications. This strategy has been successfully applied in prior works to design basic analog building blocks, and it is explored in this work to automate the high-level sizing of ΣΔMs . Several ΣΔM case studies, which include both single-loop and cascade topologies as well as Switched-Capacitor (SC) and Continuous-Time (CT) circuit techniques are shown. The effect of ANN hyperparameters - such as the number of layers, neurons per layer, batch size, number of epochs, etc. - is analyzed in order to find out the best ANN architecture that finds an optimum design with less computational resources. A comparison with other optimization methods - such as genetic algorithms and gradient descent - is shown, demonstrating that the presented approach yields to more efficient design solutions in terms of performance metrics, power consumption and CPU time 1 1 This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future, and by ’’Junta de Andalucía’’ under Grant P20-00599.

Bandpass ΔΣ Modulators with FIR Feedback
J. Gorji, S. Pavan and J.M. de la Rosa
Journal Paper · IEEE International Symposium on Circuits and Systems ISCAS 2023
abstract doi

This paper investigates finite impulse response (FIR) feedback in bandpass delta-sigma modulators (BP- ΔΣMs ). FIR feedback in lowpass delta-sigma modulators (LP- ΔΣMs ) improves loop filter linearity and reduces the sensitivity of the modulator to clock jitter. We show that similar benefits can be obtained in a BP- ΔΣM if the FIR filter in the feedback path is made a bandpass one 1 1 This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future, and by ’’Junta de Andalucía’’ under Grant P20-00599 and in part by the Center of Excellence in RF, Analog and Mixed-Signal ICs (CERAMIC), IIT Madras..

Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems
P.I. Enwere, E. Cervantes-Requena, L.A. Camuñas-Mesa and J.M. de la Rosa
Journal Paper · Integration, vol. 93, 2023
abstract doi

This paper analyzes the use of Artificial Neural Networks (ANNs) to identify and predict the evolution of vacant portions or frequency holes of the radio spectrum in Cognitive Radio (CR) systems. The operating frequency of CR transceivers can be modified over the air according to the information provided by the ANN in order to establish the communication in the least occupied band. To this end, ANNs are trained with time-series datasets sensed from the electromagnetic environment. Several network architectures are considered in the study, including Convolutional Neural Networks (CNNs), Long Short-Term Memory (LSTM) networks and hybrid combinations of them. These ANNs are modeled and compared in terms of their complexity, speed and accuracy of the prediction. Both simulations and experimental results are shown to validate the approach presented in this work.

A 12-bit Low-input Capacitance SAR ADCwith a Rail-to-Rail Comparator
N. Shahpari, M. Habibi, P. Malcovati and J.M. de la Rosa
Journal Paper · IEEE Access, 2023
abstract doi

The input capacitance of the SAR ADC is considered as a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance SAR based on separated DAC and sample-and-hold blocks (SB) structure is proposed. The SB structure suffers from variation of the input common-mode voltage of the comparator causing nonlinear input-referred offset and kickback noise. Here, a closed loop low-power rail-to-rail offset cancellation technique for the comparator based on the body voltage tuning is proposed. In order to stabilize the closed loop structure, the open loop gain is controlled by adapting the gain of the preamplifier. Using this structure, the rail-to-rail offset is kept lower than 110 μV and the overall power of the comparator is 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at the input the comparator to decrease the common-mode dependent kickback noise error to less than 1 LSB. The bootstrapped switch’s controlling signal is also modified to achieve less than 1 LSB error and 18.9% less power consumption. The proposed ADC is designed in standard 180 nm CMOS technology with a 1.8 V supply voltage and shrinking the input capacitance to 2 pF, which leads to 41 nW power consumption in the input voltage supply. Electrical simulations including PVT, Monte-Carlo, and post-layout parasitic extraction were run to ensure the effectiveness of the approach. The ADC features an ENOB of 11.1-bit and the sampling rate of 1 MHz with a power consumption of 117.9 μW including the input power supply which are competitive with the state-of-the-art, and demonstrate the virtue of the proposed approach.

Band-Pass Sigma-Delta Modulation: The Path towards RF-to-Digital Conversion in Software-Defined Radio
J.M. de la Rosa
Journal Paper · Chips, vol. 2 no. 1, articles 44-69, 2023
abstract doi

This paper reviews the state of the art on bandpass sigma-delta modulators (BP-sigma-deltaMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-sigma-deltaM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals.

Ultra-High-Resistance Pseudo-Resistors with Small Variations in a Wide Symmetrical Input Voltage Swing
F. Karami-Horestani and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs
abstract doi

This paper presents a new strategy and circuit configuration composed of serially-connected PMOS devices operating in the subthreshold region for implementing ultra-highvalue resistors required in very low-frequency active-RC filters and bio-amplifiers. Depending on the application, signal bandwidth for instance in bio-amplifiers may vary from a few mHz up to a maximum of 10 kHz. Three different resistor structures are proposed to achieve ultra-high resistance. While ranging in the order of several TY, the proposed ultra-high-resistance pseudoresistors occupy a small on-chip silicon area, which is one of the main issues in the design of analog front-end circuits in ultra-low power implantable biomedical microsystems. In addition, these ultra-high-value resistors lead to the use of a small capacitance to create a very small cut-off frequency. Therefore, the large area to implement capacitances is also considerably reduced. The proposed resistor structures have very small variations about 7% and 12% in a wide input voltage range (-0.5 V +0.5 V), thus significantly improving the total harmonic distortion of bioamplifiers and the analog front-end of the system. Simulation results of different circuits designed in a 180nm CMOS technology, are shown to demonstrate the advantages of the proposed ultra-high-resistance pseudo-resistors.

AI-Assisted Sigma-Delta Converters — Application to Cognitive Radio
J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 22, no. 1, pp 10-39, 2022
abstract doi

This brief discusses the use of Artificial Intelligence (AI) to manage the operation and improve the performance of Analog-to-Digital Converters (ADCs) based on Sigma-Delta Modulators (ΣΔMs). The reconfigurable nature of ΣΔMs can be enhanced by AI algorithms in order to adapt the specifications of ADCs to diverse input signal requirements, environment interferences, noise levels, battery status, etc. A high degree of programmability is required, which demands for scaling-friendly, mostly-digital analog circuit techniques as well as suitable topologies of Artificial Neural Networks (ANNs) to implement the AI engine. Moreover, the practical implementation of AI-assisted ΣΔMs requires to adopt diverse design strategies -from the ΣΔM architecture itself to AI modules and circuit building blocks -which are overviewed in this brief. As an application and case study, an ANN-assisted ADC for Software-Defined Radio (SDR) and Cognitive Radio (CR) is considered. The system is based on the use of a widely-tunable Band-Pass (BP)- ΣΔM, and an ANN is used to predict the occupancy of frequency bands and modify the notch frequency of the BP-ΣΔM accordingly.

AI-Managed Cognitive Radio Digitizers
J.M. de la Rosa
Journal Paper · IEEE Circuits and Systems Magazine, vol. 22, no. 1, pp 10-39, 2022
abstract doi

Embedding Artificial Intelligence (AI) in integrated circuits is one of the technology pillars of the so-called digital transformation . Nowadays, the vast majority of electronic devices benefits from digital signal processing to implement more and more functionalities, which can be further enhanced by the action of AI algorithms and artefacts. Moreover, as the analog/digital interfaces are moving closer and closer to the point where the information is either acquired or transmitted, the so-called AI-managed data converters are becoming key building blocks in an increasingly number of interconnected cyberphysical systems -made up of both software and hardware components. Software Defined Radio (SDR) and Cognitive Radio (CR) systems intended for 5G/6G communications are good examples which can benefit from an early digitization managed by AI engines.
In this context, this paper presents an overview of circuits and systems techniques for AI-managed analog/digital interfaces with application in SDR/CR mobile telecom systems. Some design trends and challenges are discussed, going from new communications and computing paradigms for AIoT devices and networks, to digital-based/scaling-friendly analog circuit techniques for an efficient digitization. The state of the art on Analog-to-Digital Converters (ADCs) is surveyed, putting emphasis on highly-programmable Sigma-Delta Modulators (ΣΔMs) as one of the best ADC candidates for SDR/CR transceivers. Some chip examples are shown to illustrate their potential application in AI-enhanced CR end-devices.

Outgoing Editorial
J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 12, pp 3477-3477, 2021
abstract doi pdf

Abstract not available

Reducing the Nonlinearity and Harmonic Distortion in FD-SOI CMOS Current-Starved Inverters and VCROs
P.I. Okorie, J. Ahmadi-Farsani and J.M.de la Rosa
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 142, article 153992, 2021
abstract doi pdf

This paper demonstrates experimentally how to reduce the nonlinearity of some analog and mixed-signal circuits by using the enhanced body effect provided by Fully-Depleted Silicon on Insulator (FD-SOI) CMOS technology. A current-starved CMOS inverter and a Voltage-Controlled Ring Oscillator (VCRO) are considered as case studies. The inverter is configured as a simple amplifier stage in which the harmonic distortion can be reduced and even removed by the combined action of the control voltages applied at the gate and bulk terminals of the current-source transistors. This current-starved inverter is used as the basic building block of a VCRO, where a more linear voltage-to-frequency characteristic can be achieved if the bulk terminal is used as the control voltage of the oscillator. The circuits under study have been designed and fabricated in a 28-nm FD-SOI technology and experimental results are shown to validate the presented approach.

Thermography for the differential diagnosis of vascular malformations
J.A. Leñero-Bardallo, C. Serrano, B. Acha, J.A. Pérez-Carrasco and J. Bernabeu-Wittel
Journal Paper · Clinical and Experimental Dermatology, vol. 46, no. 2, pp 314-318, 2021
abstract doi pdf

Vascular malformations classification may pose a diagnostic challenge for physicians. In the early stages, they are diagnosed clinically mainly by visual inspection. For a deeper analysis, Doppler ultrasonography is the preferred technique to determine the haemodynamic behaviour of the anomaly. However, this imaging method is not always available and it requires trained operators to acquire and interpret the images. There is a lack of portable and user-friendly systems that may help physicians in the assessment of vascular malformations. We propose a new diagnostic procedure, more affordable and easier to use, based on a portable thermal camera. This technique provides information about temperature, which has been found to be correlated with the flow rate of the lesion. In our study, > 60 vascular malformations of previously diagnosed patients were analysed with a thermal camera to classify them into low-flow and high-flow malformations. The value was 1 for both sensitivity and specificity of this technique.

Neuromorphic Low-power Inference on Memristive Crossbars with On-chip Offset Calibration
C. Mohan, L.A. Camuñas-Mesa, J.M. de la Rosa, E. Vianello, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · IEEE Access, vol. 9, pp 38043-38061, 2021
abstract doi pdf

Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired neuromorphic circuits. One drawback of OxRAM based neuromorphic systems is the relatively low ON resistance of OxRAM synapses (in the range of just a few kilo-ohms). This requires relatively large currents (many micro amperes per synapse), and therefore imposes strong driving capability demands on peripheral circuitry, limiting scalability and low power operation. After learning, however, a read inference can be made low-power by applying very small amplitude read pulses, which require much smaller driving currents per synapse. Here we propose and experimentally demonstrate a technique to reduce the amplitude of read inference pulses in monolithic neuromorphic CMOS OxRAM-synaptic crossbar systems. Unfortunately, applying tiny read pulses is non-trivial due to the presence of random DC offset voltages. To overcome this, we propose finely calibrating DC offset voltages using a bulk-based three-stage on-chip calibration technique. In this work, we demonstrate spiking pattern recognition using STDP learning on a small 4x4 proof-of-concept memristive crossbar, where on-chip offset calibration is implemented and inference pulse amplitude could be made as small as 2mV. A chip with pre-synaptic calibrated input neuron drivers and a 4x4 1T1R synapse crossbar was designed and fabricated in the CEA-LETI MAD200 technology, which uses monolithic integration of OxRAMs above ST130nm CMOS. Custom-made PCBs hosting the post-synaptic circuits and control FPGAs were used to test the chip in different experiments, including synapse characterization, template matching, and pattern recognition using STDP learning, and to demonstrate the use of on-chip offset-calibrated low-power amplifiers. According to our experiments, the minimum possible inference pulse amplitude is limited by offset voltage drifts and noise. We conclude the paper with some suggestions for future work in this direction.

Editorial: A Year Ahead Full of New Initiatives
J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 1, pp 4-4, 2021
abstract doi

First of all, I hope that you, your families and all yours remain healthy and safe. The thoughts of the Editorial Board (EB) of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS (TCAS-II) and all the staff from IEEE are with those who are facing health problems and have suffered the consequences of the COVID-19 pandemic. The first year of my term as Editor-in-Chief (EiC) of IEEE TCAS-II has run under this terrible situation which has changed the lifestyle of all of us. We have seen how almost all social and professional events, including of course most IEEE conferences, have been either cancelled or running virtual, what has precluded us from enjoying together with our friends and colleagues as we had always done. The New Year 2021 comes full of hope for humankind with the development of several vaccines and more effective drugs to fight against the coronavirus SARS-Cov-2, and I am firmly convinced that sooner than later we will be able to recover our way of living.

Design of Wideband Comb Compensator based on Magnitude Response using Two Sinusoidals and Particle Swarm Optimization
G.J. Dolecek and J.M.de la Rosa
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 130, article 153570, 2021
abstract doi

This paper presents the particle swarm optimization-based design of a wideband comb compensator with a sinewave magnitude response. First, the magnitude response of the compensator is presented as a sum of two sinewave functions, where the amplitudes of sinusoidal functions are the design parameters. Next, a particle swarm optimization is applied to find the design parameters which result in a minimum of the absolute value of passband deviation of the compensated comb, for a given set of comb parameters. The resulted comb compensator has two multipliers and six adders. Next, the design parameters are expressed as a sum of powers of two, in order to get a multiplierless design. In order to demonstrate the advantages of the proposed designs, both multiplier, and multiplierless designs, are compared with the state-of-the-art.

A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-based CT MASH ΣΔ Modulator
M. Honarparvar, J.M. de la Rosa and M. Sawan
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 9, pp 1519-1523, 2020
abstract doi

We present in this paper a novel multi-stage noise-shaping (MASH) 3-1 continuous-time (CT) delta-sigma modulator (ΣΔM) with gated ring oscillator based quantizers (GROQs) in both stages of the cascade. The use of GROQs increases the linearity performance with respect to the conventional voltage controlled oscillator based quantizers (VCOQs) and allows a more robust extraction of the front-end stage quantization error in the time domain, thus making the proposed architecture more suitable to implement high-order expandable scaling-friendly MASH ΣΔMs, in which the back-end stages are implemented by mostly-digital GRO-based time-to-digital converters (TDCs). The circuit has been fabricated in a 65-nm CMOS technology with 1-V supply voltage, and it operates at 640-MHz sampling frequency to digitize 10-MHz signals. To the best of the authors’ knowledge, this is the first reported experimental validation of a GRO-based CT MASH ΣΔM, featuring a 79.8-dB signal to noise ratio (SNR) at -2.2-dBFS, a 77.3-dB signal to (noise + distortion) ratio (SNDR) at -4-dBFS and a dynamic range (DR) of 81.7 dB, with a power consumption of 12-mW. These metrics demonstrate state-of-the-art performance with a DR-based Schreier FOM of 170.9 dB.

Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits - Application to Voltage- Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs
J. Ahmadi-Farsani, V. Zúñiga-González, T. Serrano-Gotarredona, B. Linares-Barranco and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67 ,no. 10, pp 3297-3308, 2020
abstract doi

This paper investigates the use of the body terminal of MOS transistors to improve the linearity of some key circuits used to implement analog and mixed-signal circuits integrated in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) CMOS processes. This effect is analyzed in basic analog building blocks - such as switches, simple-stage transconductors and Voltage-Controlled Ring Oscillators (VCROs). Approximated expressions are derived for the nonlinear characteristics and harmonic distortion of some of these circuits. As an application, transistor-level simulations of two VCRO-based ΣΔ modulators designed in a 28-nm FD-SOI CMOS technology are shown in order to demonstrate the benefits of the presented techniques.

Incoming Editorial
J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no.1, pp 1-3, 2020
abstract doi

Dear Readers, It is a great honor and privilege for me to start my two-year term of duty as Editor-in-Chief (EiC) of IEEE Transactions on Circuits and Systems - Part II: Express Briefs (TCAS-II) and I am very thankful to the IEEE Circuits and Systems Society (CASS) for giving me this opportunity. During the last four years, I have been very fortunate to work as Deputy Editor-in-Chief (DEiC) of TCAS-II together with Professor C.K. Michael Tse, who has set the bar very high for me! I would like to begin this first issue of TCAS-II in 2020 by expressing my most sincere and warm gratitude to Professor Tse for his great job, dedication, and guidance during all this time working together. I learned a lot from him. Thank you so much, Michael!

Guest Editorial Special Issue on the 2019 ISICAS: A CAS Journal Track Symposium
J.M. de la Rosa, E. Bonizzoni and F. Maloberti
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 10, pp 1607-1607, 2019
abstract doi

This special issue of the IEEE Transactions on Circuits and Systems - Part II: Express Briefs (TCAS-II) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS), held in Venice, Italy, on 29-30 August 2019. This is the second edition of this journal track symposium as part of the initiative of the IEEE Circuits and Systems Society (CASS), started in 2018. The symposium is focused on original works reporting hybrid, System-in-Package (SiP) or System-on-Chip (SoC) implementations of circuits and systems with state-of-the-art experimental results.

Guest Editorial Special Issue on the 2019 IEEE International Symposium on Circuits and Systems
J.M. de la Rosa and Y. Nishio
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no.5, pp 717-717, 2019
abstract doi

This special issue of the IEEE Transactions on Circuits and Systems-Part II: Express Briefs ( TCAS-II ) follows the successful co-publication initiative started last year by the IEEE Circuits and Systems Society (CASS) to publish a selection of the best papers accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS), held this year in Sapporo, Japan, on May 26-29. As TCAS-II only publishes five-page briefs, and hence both conference and journal versions of selected works would be largely overlapped, the papers included in this issue represent the only record published in IEEE Xplore and they will not appear in the Proceedings of IEEE ISCAS , which will however contain DOI links to the corresponding TCAS-II papers. Similar to other IEEE societies, IEEE-CASS intends to shift the role of IEEE conferences toward networking events as well as a scientific discussion opportunity, rather than putting the emphasis on the conference paper publication itself.

Guest Editorial Special Issue on the 2018 ISICAS: A CAS Journal Track Symposium
J.M. de la Rosa, E. Bonizzoni and F. Maloberti
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 10, pp 1289-1289, 2018
abstract doi

This special issue of the IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS), held in Taormina, Italy, on 2-3 September 2018. This is the first edition of this symposium and a new initiative of the IEEE Circuits and Systems Society (CASS), which includes a selection of original works in very diverse areas of integrated circuits and systems, describing integrated implementations with experimental results. In contrast to conventional symposia and conferences, ISICAS is a Journal Track Symposium which does not produce proceedings. Instead, the works presented at the conference are published in two journal special issues. One of them is the issue that you are holding and the other one is a special issue of the IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I). The technical program of the conference is therefore made up of those papers which has been accepted for publication in these special issues of TCAS-I and TCAS-II.

Methodology to improve the model of series inductance in CMOS integrated inductors
E.F. Gutierrez-Frias, L.A. García-Lugo, E.C. Becerra-Alvarez, J.J. Raygoza-Panduro, J.M. de la Rosa and E.B. Ortega-Rosales
Journal Paper · Journal of Electrical Engineering, vol. 69, no. 3, pp 250-254, 2018
abstract doi pdf

This paper presents a systematic optimization methodology to achieve an accurate estimation of series inductance of inductors implemented in standard CMOS technologies. Proposed method is based on an optimization procedure which aims to obtain adjustment factors associated to main physical inductor characteristics, allowing to estimate more accurate series inductance values that can be used in design stage. Experimental measurements of diverse square inductor geometries are shown and compared with previous approaches in order to demonstrate and validate presented approach.

A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation
S. Asghar, S. Saadat Afridi, A. Pillai, A. Schuler, J.M. de la Rosa and I. O'Connell
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp 3628-3638, 2018
abstract doi

A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 Vpp-d (± 1.33 VREF). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-µm CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.

A 0.9-V 100-μW Feedforward Adder-Less Inverter-based MASH ΔΣ Modulator with 91-dB Dynamic Range and 20-kHz Bandwidth
M. Honarparvar, J.M. de la Rosa and M. Sawan
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp 3675-3687, 2018
abstract doi

A 0.9-V ΔΣ modulator integrated into a 0.18-μm 2 CMOS technology for digitizing signals in low-power devices is presented in this paper. To do so, a cascade (multistage noise shaping) architecture based on an adder-less feedforward structure is proposed. The proposed modulator has a unity signal transfer function in both stages of the modulator in order to reduce the integrator´s output swings. To mitigate the failure of slow process corner in the weak inversion as well as to further diminish the power consumption of the presented modulator, a fully differential self- and bulk-biased inverter based operational transconductance amplifier is proposed. Experimental results are shown to demonstrate the efficiency of the proposed ΔΣ converter, showing state-of-the-art performance, by featuring 88.7-dB signal-to-noise ratio, 86.4-dB signal-to-noise plus distortion ratio, and 91-dB dynamic range within a signal bandwidth of 20 kHz, with a power dissipation of 103.4 μW when the circuit is clocked at 5.12 MHz.

Calibration of offset via bulk for low-power HfO2 based 1T1R memristive crossbar read-out system
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, L. Periniolla, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · Microelectronic Engineering, vol. 198, pp 35-47, 2018
abstract doi

Neuromorphic RRAM circuits typically need currents of several mA when many binary memristive devices are activated at the same time. This is due to the low resistance state of these devices, which increases the power consumption and limits the scalability. To overcome this limitation, it is vital to investigate how to minimize the amplitude of the read-out inference pulses sent through the crossbar lines. However, the amplitude of such inference voltage pulses will become limited by the offset voltage of read-out circuits. This paper presents a three-stage calibration circuit to compensate for offset voltage in the wordlines of a memristor-array read-out system. The proposed calibration scheme is based on adjusting the bulk voltage of one of the input differential pair MOSFETs by means of a switchable cascade of resistor ladders. This renders the possibility to obtain calibration voltage steps less than 0.1mV by cascading a few number of stages, whose results are only limited by mismatch, temperature, electrical noise and other fabrication defects. The system is built using HfO₂-based binary memristive synaptic devices on top of a 130-nm CMOS technology. Layout-extracted simulations considering technology corners, PVT variations and electrical noise are shown to validate the presented calibration scheme.

Guest Editorial: Special Issue on the 2018 IEEE International Symposium on Circuits and Systems
José M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, p 531, 2018
abstract doi

This special issue of IEEE Transactions on Circuits and Systems-Part II: Express Briefs (TCAS-II) represents a new co-publication initiative of the IEEE Circuits and Systems Society (CASS) to publish a selection of the best papers accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS), held in Florence, Italy, on May 27-30, 2018. As TCAS-II only publishes 5-page briefs, and hence both conference and journal (revised) versions of these works would largely overlap, the papers included in this issue that you are holding represent the only record published in IEEE Xplore and they will not appear in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), which will however contain DOI links to the corresponding TCAS-II papers. With this initiative, CASS joins other forward-looking IEEE Societies, namely, the IEEE Robotics and Automation Society and IEEE Control Systems Society, which have developed a similar process for presenting papers submitted to the IEEE Robotics and Automation Letters or to the IEEE Control Systems Letters at ICRA, CASE, or IROS and to CDC, respectively. In a world where the role of a conference is shifting more and more to a networking event and a scientific discussion opportunity, and in which the importance of conference publications is vanishing (except for some specific fields), we consider this opportunity an important step forward for the CASS community.

Embedding MATLAB Optimizers in SIMSIDES for the High-Level Design of ΣΔ Modulators
B. Cortés-Delgadillo, P.A. Rodríguez-Navas, L.I. Guerrero-Linares and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp 547-551, 2018
abstract doi pdf

This brief shows how to combine SIMSIDES, a SIMULINK-based time-domain behavioral simulator, with different optimization engines available in MATLAB for the automated high-level design of ΣΔ modulators. To this purpose, an updated version of SIMSIDES has been developed, which includes a user-friendly interface that links the simulator with the optimizers, and guides designers through the main steps required to set the design variables, constraints and select the most suitable algorithm to maximize the performance of an arbitrary modulator topology for a given set of specifications. Several examples and results of the optimization procedure are shown to illustrate the benefits of the presented tool for the high-level synthesis of ΣΔ modulators.

SMASH ΔΣ modulator with adderless feed-forward loop filter
M. Honarparvar, J.M. de la Rosa, F. Nabki and M. Sawan
Journal Paper · Electronics Letters, vol. 53, no. 8, pp 532-534, 2017
abstract doi

A novel cascade ΔΣ modulator, which combines the benefits of SMASH topology and feed-forward loop filter, is presented in this letter. The proposed ΔΣ architecture is based on moving the power-hungry adder block from the quantizer input to the first integrator output. The proposed architecture shows a better OTA linearity and relaxed OTA DC-gain compared to conventional MASH and SMASH topologies. This feature makes the modulator topology more suitable than conventional MASH and SMASH topologies for low-voltage applications.

Novel Multiplierless Wideband Comb Compensator with High Compensation Capability
G. Jovanovic-Dolecek, R. Garcia-Baez, G. Molina-Salgado anf J.M. de la Rosa
Journal Paper · Circuits, Systems, and Signal Processing, vol. 36, no. 5, pp 2031-2049, 2017
abstract doi pdf

This paper proposes a novel multiplierless comb compensation filter, which has the absolute passband deviation less than 0.1 dB in the wide passband. The compensator consists of a cascade of two simple filter sections, both operating at a low rate. The magnitude characteristics of the two-component filters are synthesized as sinewave functions, in which the main design parameters correspond to the amplitudes of sinewave functions. A systematic procedure is followed to select synthesis parameters, which depend only on the number of cascaded comb filters. In particular, they are independent of the decimation factor. Comparisons with comb compensators from the literature illustrate the benefits of the proposed design.

Special Issue: highlights from the IEEE Latin American Symposium on Circuits and Systems LASCAS 2015
J.M. de la Rosa, C. Galup-Montoro, F. Silveira and A. Arnaud
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 89, no. 3, pp 507-509, 2016
abstract doi

We are very pleased to present to the readers of the Springer Journal on Analog Integrated Circuits and Signal Processing (ALOG) a selection of extended papers from the 6th edition of the IEEE Latin America Symposium on Circuits and Systems (LASCAS 2015). The symposium, a forum for discussion of the latest technical novelties on circuits and systems topics, took place in Montevideo-Uruguay, organized by the local IEEE-CAS chapter. LASCAS is an annual meeting that brings together researchers, industry, engineers, students interested in circuits and systems across a wide spectrum of scientific and technological fields: VLSI, analog and digital signal processing, biomedical circuits and systems, multimedia systems, nanoelectronics, neural networks, communications circuits, CAD, power electronic circuits, sensors, among others. The conference is a great opportunity for colleagues operating in very different areas of industrial, scientific, and technological endeavor to come together and create the basis for renewed collaboration.

Low power two-stage comb decimation structures for high decimation factors
G. Molina-Salgado, G. Jovanovic-Dolecek and J.M. de la Rosa
Journal Paper · Analog Integrated Circuits and Signal Processing, vol.88, no. 2, pp 245-254, 2016
abstract doi

This paper presents power and area analysis of two-stage comb-based decimation structures for high decimation factors. The first stage is either in a recursive form cascaded-integrator-comb (CIC) or in a non-recursive form, while the second stage is in a recursive form. The proposed structures are compared with a single CIC structure. We demonstrated how to choose the decimation factor of the first stage in order to get simultaneously the highest possible power reduction and the lowest possible area increase, in a comparison with a single CIC structure. Additionally, the modified two-stage structure with an increased attenuation and a reduced power consumption is presented. Analysis is supported by MATLAB simulations and validated by the VHDL implementations.

Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014)
J.M. de la Rosa, P. Chiang and L.T. Clark
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 62, no. 8, pp. 1897-1898, 2015
abstract doi

The papers in this special section consists of expanded versions of six papers presented at the Custom Integrated Circuits Conference (CICC), held in San Jose, CA, USA, in September 2014.

Next-Generation Delta-Sigma Converters: Trends and Perspectives
J.M. de la Rosa, R. Schreier, K.-P. Pun and S. Pavan
Journal Paper · IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 5, no. 4, 2015
abstract doi

This paper presents an overview of emerging circuits and systems techniques which are at the forefront of the state of the art in ΣΔ modulators, pushing their performance forward and giving rise to new generations of data converters. Among others, those strategies involving the development of new applications and paradigms —like RF/GHz-range ΣΔ digitisation, digital-assisted embedded loop filters, time-to-digital conversion and hybrid ΣΔ/Nyquist-rate architectures— are discussed, as well as the implications and design challenges derived from their integration in deep nanometer CMOS technologies. The envisioned ΣΔ techniques are presented in a systematic way around the main analog building blocks embedded in a ΣΔ modulator, i.e., the loop filter and the quantizer. Analysing the trends in the design of these blocks allows us to offer perspectives on how ΣΔ converters will evolve in the next years.

A fast readout electronic system for accurate spatial detection in ion beam tracking for the next generation of particle accelerators
A. Garzón-Camacho, B. Fernández, M.A.G. Álvarez, J. Ceballos and J.M. de la Rosa
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 64 , no. 2, pp 318-327, 2015
abstract doi pdf

This paper presents the design, implementation, and measurements of a complete electronic frontend intended for high-resolution spatial detection of ion beams at counting rates higher than 10⁶ particles per second (p/s). The readout system is made up of three main multichannel building blocks, namely, a transimpedance preamplifier, a signal-conditioning line receiver, and a charge-to-digital converter, as well as some off-the-shelf components. The preamplifier and the line receiver have been specifically designed and optimized to minimize the overlapping probability of ion beams tracking, at high counting rates, in low-pressure gaseous secondary electron detectors. Experimental results are shown, considering α particles sources and particles beams, featuring an adaptive shaping time frame of 170-230 ns with a peak signal-to-noise ratio of up to 25 dB. These performance metrics are competitive with the state of the art, demonstrating the suitability of the reported data acquisition and instrumentation system for precise and fast particle tracking detection.

Efficient hybrid continuous-time/discrete-time cascade ΣΔ modulators for wideband applications
J.G. García-Sánchez and J.M. de la Rosa
Journal Paper · Microelectronics Journal, vol. 45, no. 10, pp 1234-1246, 2014
abstract doi pdf

This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all ΣΔ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid ΣΔ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4-bit) cascade ΣΔ modulator is discussed to illustrate the potential benefits of the presented approach.

Guest Editorial: Special Section on the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013)
J.M. de la Rosa, J.W.M. Rogers and V. Chandra
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no.8, pp 2217-2218, 2014
abstract doi

Abstract not avaliable

LC-Based Bandpass Continuous-Time Sigma-Delta Modulators with Widely Tunable Notch Frequency
A. Morgado and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 5, pp 1442-1455, 2014
abstract doi

This paper analyses the use of bandpass continuous-time ΣΔ modulators with widely programmable notch frequency for the efficient digitization of radio-frequency signals in the next generation of software-defined-radio mobile systems. The modulator architectures under study are based on a fourth-order loop filter - implemented with two LC-based resonators - and a finite-impulsive-response feedback loop in order to increase their flexibility and degrees of freedom. Several topologies are studied, considering three different cases for the embedded digital-to-analog converter, namely: return-to-zero, non-return-to-zero and raised-cosine waveform. In all cases, a notch-aware synthesis methodology is presented, which takes into account the dependency of the loop-filter coefficients on the notch frequency and compensates for the dynamic range degradation due to the variation of the notch. The synthesized modulators are compared in terms of their sensitivity to main circuit error mechanisms and the estimated power consumption over a notch-frequency tuning range of 0.1fs to 0.4fs. Time-domain behavioral and macromodel electrical simulations validate this approach, demonstrating the feasibility of the presented methodology and architectures for the efficient and robust digitization of radio-frequency signals with a scalable resolution and programmable signal bandwidth.

Special Issue on Advances in sensing and communication circuits (ICECS 2012)
A. Rodríguez-Vázquez, J. Fernández-Berni and J.M. de la Rosa
Journal Paper · Analog Integrated Circuits and Signal Processing , vol. 77, no. 3, pp 315-317, 2013
abstract doi

Abstract not available

Design and experimental results of a preamplifier for particles tracking in secondary electron detectors
A. Garzón-Camacho, B. Fernández, Marcos A.G. Álvarez, J. Ceballos and J.M. de la Rosa
Journal Paper · Microelectronics Journal, vol. 44, pp 1-5, 2013
abstract doi pdf

This paper presents the design and experimental characterization of a preamplifier used in the electronic front-end of low-pressure gaseous secondary electron detectors. The circuit-implemented in a printed circuit board as a proof of concept has been designed to cope with the specifications of the readout electronics used in spatial (beam particle position) measurements. Experimental results show a transimpedance gain of 80 dBΩ, an overall voltage gain of 18 dB, a peak signal-to-noise ratio of 36.5 dB and a shaping time frame of 140-170 ns. These features improve the performance of previous reported approaches to the problem, and allow us to minimize the overlapping probability in secondary electron detections for radioactive ion beams tracking, achieving a counting rate higher than 10(6) particles per second.

Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback
J.M. Doresa, E.C. Becerra-Alvarez, M.A. Martinsa, J.M. de la Rosa and J.R. Fernandes
Journal Paper · Microelectronics Journal, vol. 43, no. 10, pp 714-720, 2012
abstract doi pdf

This paper presents a comparative study among different biasing circuits of inductorless low-area Low Noise Amplifier (LNAs) with feedback. This study intends to determine the most suitable biasing circuit to achieve the best LNA performance for wideband applications. The main performance metrics are analyzed and a comparison is carried out based on electrical simulations. To this purpose, two different CMOS technology processes are considered: 130 nm and 90 nm. In both cases, the supply voltage is 1.2 V. The best LNA designed in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (A v) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology designed in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are input-impedance matched and have a noise figure below 2.4 dB measured at 2.4 GHz. As a case study, the layout of the best-performance LNA circuit has been implemented in a 130 nm technology, achieving an area of 0.012 mm 2, which is near the size of a pad or an inductor. It is demonstrated that the bandwidth of this circuit can be notably increased by simply adding a small inductance in the feedback path.

High-efficiency cascade ΣΔ modulators for the next generation software-defined-radio mobile systems
A. Morgado, R. del Río and J.M. de la Rosa
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 61, no. 11, pp 2860-2869, 2012
abstract doi pdf

This paper overviews a number of ΣΔ modulation techniques to implement efficient analog-to-digital converters intended for low-voltage wideband multimode wireless telecom systems. The ΣΔ architectures under study combine different strategiesunity signal transfer function (USTF), resonation, loop-filter order reconfiguration, and concurrencyin order to increase performance while keeping high robustness against circuit errors. Practical considerations involving timing issuesderived from the combined use of different noise-shaping techniquesare analyzed in order to evaluate the feasibility of the proposed ΣΔ topologies. As an application, the design, circuit implementation, and experimental characterization of a flexible 1.2-V 90-nm CMOS sixth-order three-stage cascade SC ΣΔ modulator is presented. The modulator uses local resonation in the last two stages and USTF and programmable (either three or five levels) quantization in all stages. The chip reconfigures its loop-filter order (second, fourth, sixth order) and the clock frequency (from 40 to 240 MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental measurements show the flexibility of the proposed circuit, featuring a programmable noise shaping within a 100-kHz-10-MHz signal band, with adaptive power dissipation, thus demonstrating to be a suitable solution to digitize signals in future software-defined-radio mobile terminals. © 1963-2012 IEEE.

Multirate downsampling hybrid CT/DT cascade sigma-delta modulators
J.G. García-Sánchez and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 2, pp 285-294, 2012
abstract doi pdf

This paper presents a new concept of multirate cascade SIGMA DELTA modulators, in which the signal is downsampled across the cascade instead of being upsampled as done in conventional multirate architectures. This strategy is suited for hybrid continuous-time/discrete-time cascade SIGMA DELTA modulators, where only the front-end stage is implemented by continuous-time circuits, and the remaining back-end stages are realized using switched-capacitor circuits. The main drawback of this approach comes from the implicit aliasing error signal due to the downsampling process. However, as shown in this paper, this error can be completely canceled in the digital domain, with no additional analog hardware required. The combination of these features results in a new class of SIGMA DELTA modulators, which are potentially faster and more power efficient than conventional multirate architectures and more robust against circuit element tolerances than cascade single-rate continuous-time implementations for wideband applications. © 2012 IEEE.

Sigma-Delta modulators: tutorial overview, design guide, and state-of-the-art survey
J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 1, pp 1-21, 2011
abstract doi pdf

This paper presents a tutorial overview of sigma delta modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge Sigma Delta architectures, with emphasis on their application to the next generation of wireless telecom systems.

A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications
A. Morgado, R. del Río, J.M. de la Rosa, R. Castro-López and B. Pérez-Verdú
Journal Paper · Microelectronics Journal, vol. 41, no. 5, pp 277-290, 2010
abstract doi

This paper describes the design and experimental characterization of a 0.13 mu m CMOS switched-capacitor reconfigurable cascade Sigma Delta modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode EA prototype shows an overall performance that is competitive with the current state of the art.(1) (C) 2010 Elsevier Ltd. All rights reserved.

Design of an adaptive LNA for hand-held devices in a 1-V 90-nm standard RF CMOS technology: From circuit analysis to layout
E. Becerra-Alvarez, F. Sandoval-Ibarra and J.M. de la Rosa
Journal Paper · Journal of Applied Research and Technology, vol. 7, no. 1, pp 51-61, 2009
abstract pdf

This paper deals the design of a reconfigurable Low-Noise Amplifier (LNA) for the next generation of wireless hand-held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand-work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two-stage topology including inductive-source degeneration, MOS-varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b-g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF<1.77dB, S21>16dB, S11<-5.5dB, S22<-5.5 dB and IIP3>-3.3 dBm over the 1.85-2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1-V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.

Hybrid continuous-time/discrete-time cascade sigma delta modulator with adaptive inter-stage resonation
A. Morgado, J.M. de la Rosa and R. del Río
Journal Paper · Electronics Letters, vol. 45, no. 5, pp 251-252, 2009
abstract doi

A novel architecture of a hybrid continuous- time/discrete-time cascade Sigma Delta modulator that takes advantage of both circuit techniques, by including implicit anti-aliasing. filtering and reduced sampling requirements, while presenting high robustness to circuit non-idealities, is presented. These circuital features are combined with programmable resonation to optimally distribute the zeros of the noise transfer function. In addition, the unity signal transfer function is implemented in all the modulator stages in order to reduce the integrator's output swing. All these characteristics make the proposed architecture well suited to the implementation of reconfigurable A/D conversion in future generations of wireless telecom systems.

Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey
J.M. de la Rosa, R. Castro-López, A. Morgado, E.C. Becerra Alvarez, R. del Río, F.V. Fernández and B. Pérez-Verdú
Journal Paper · Microelectronics Journal, vol. 40, no. 1, pp 156-176, 2009
abstract doi

The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost.Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical.These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems. (C) 2008 Elsevier Ltd. All rights reserved.

Systematic top-down design of reconfigurable ΣΔ modulators for multi-standard transceivers
R. Castro-López, A. Morgado, O. Guerra, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and F. Fernández
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 58, no. 3, pp 227-241, 2009
abstract doi

This paper addresses the design techniques of reconfigurable analog-to-digital converters for multi-standard wireless communication terminals. While most multi-standard converters reported so far follow an ad hoc design approach, which do not guarantee either efficient silicon area occupation or power efficiency in the different operation modes, the methodology presented here formulates a systematic design flow that ensures that both factors are considered at all hierarchical levels. Expandible cascade modulators are considered as the starting point to further reconfigurability at the architectural level. From here on, and using a combination of accurate behavioral modeling, statistical optimization techniques, and device-level simulation, the proposed methodology handles the design complexity of a reconfigurable converter while ensuring adaptive power consumption and boosting hardware sharing. A case study is presented where a reconfigurable modulator is designed to operate under three communication standards, GSM, Bluetooth, and UMTS, in a 130 nm-CMOS technology.

Design of a 1-V 90-nm CMOS adaptive LNA for multi-standard wireless receivers
E.C Becerra-Alvarez, F. Sandoval-Ibarra and J.M. de la Rosa
Journal Paper · Revista Mexicana de Física, vol. 54, no. 4, pp 322-328, 2008
abstract pdf

This paper presents the design of a reconfigurable Low-Noise Amplifier (LNA) for the next generation of wireless hand-field devices. The circuit, based on a lumped-approach design and implemented in a 90nm standard RF CMOS technology, consists of a two-stage topology that combines inductive-source degeneration with MOS-varactor based tuning networks and programmable bias currents, in order to adapt its performance to different standard specifications with reduced number of inductors and minimum power dissipation. As an application, the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b-g). Simulation results, including technology parasitics, demonstrate correct operation of the LNA for these standards, featuring NF < 1.77dB, S-21 > 16dB, S-11 <-5-5dB, S-22 <-5.5 dB and IIP3 >-3.3 dBm over the 1.85-2.48 GHz band, with an adaptive power consumption between 25.3 mW and 53.3mW. The layout of the LNA occupies an area of 1.18 x 1.18 mu m(2).

Clock jitter error in multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform
R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · Microelectronics Journal, vol. 39, no. 1, pp 137-151, 2008
abstract doi pdf

This paper presents a detailed study of the clock jitter error in multi-bit continuous-time EA modulators with non-return-to-zero feedback waveform. It is demonstrated that jitter-induced noise power can be separated into two main components: one that depends on the modulator loop-filter transfer function and the other dependent on input signal parameters, i.e. amplitude and frequency. The latter component, not considered in previous approaches, allows us accurately to predict the resolution loss caused by jitter, showing effects not taken into account previously in literature despite the fact that they are especially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Closed-form expressions are derived for in-band error power and signal-to-noise ratio that can be used to optimize modulator performance in terms of jitter insensitivity. Time-domain simulations of several modulator topologies (both single-loop and cascade) intended for VDSL application demonstrate the validity of the presented approach. (c) 2007 Elsevier Ltd. All rights reserved.

Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK
A. Morgado, V.J. Rivas, R. del Río, R. Castro-López, F.V. Fernández and J.M. de la Rosa
Journal Paper · Integration, the VLSI Journal, vol. 41, no. 2, pp 269-280, 2008
abstract doi pdf

This paper presents a SIMULINK block set for the behavioral modeling and high-level simulation of RF receiver front-ends. The toolbox includes a library with the main RF circuit models that are needed to implement wireless receivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the following non-idealities: thermal noise, characterized by the noise figure and the signal-to-noise ratio, and non-linearity, represented by the input-referred second-order and third-order intercept points, IIP2 and IIP3, respectively. In addition to these general parameters, some block-specific errors have also been included, like oscillator phase noise and mixer offset. These models have been incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, which makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As an application of the capabilities of the presented toolbox, a multi-standard direct-conversion receiver intended for 4G telecom systems is modeled and simulated considering the building block requirements for the different standards. (C) 2007 Elsevier B.V. All rights reserved.

Resonation-based cascade ΣΔ modulator for broadband low-voltage A/D conversion
A. Morgado, R. del Río and J.M. de la Rosa
Journal Paper · Electronics Letters, vol. 44, no. 2, pp 97-99, 2008
abstract doi pdf

A novel cascade Sigma Delta modulator architecture is presented that employs inter-stage resonation to increase its effective resolution compared to traditional cascades while presenting very relaxed output swing requirements and, subsequently, high robustness to nonlinearities of the amplifiers. In addition, the use of loop filters based on forward-Euler integrators, instead of backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architecture very suited to wideband A/D conversion.

Systematic design of high-resolution high-frequency cascade continuous-time sigma-delta modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, E. Roca, A. Rodríguez Vázquez and F.V. Fernández
Journal Paper · ETRI Journal, vol. 30, no. 4, pp 535-545, 2008
abstract doi pdf

This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigma-delta (SIGMA DELTA) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT SIGMA DELTA modulator in a 1.2 V 130 nm CMOS technology.

Cascade ΣΔ modulator for low-voltage wideband applications
A. Morgado, R. del Río and J.M. de la Rosa
Journal Paper · Electronics Letters, vol. 43, no. 17, pp 910-911, 2007
abstract doi pdf

A new cascade SigmaDelta modulator architecture with unity signal transfer function is presented which avoids the need for digital filtering in the error cancellation logic. The combination of these two aspects makes it highly tolerant to noise leakages, very robust to nonlinearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioural simulations are presented that demonstrate the higher efficiency of the proposed topology compared to existing cascades intended for wideband applications.

A new cascade sigma delta modulator for low-voltage wideband applications
A. Morgado, R. del Río and J.M. de la Rosa
Journal Paper · Electronics Letters, vol. 43, no. 17, pp 910-911, 2007
abstract doi pdf

A new cascade EA modulator architecture with unity signal transfer function is presented, which avoids the need for digital filtering in the error cancellation logic. The combination of these two aspects makes it highly tolerant to noise leakages, very robust to nonlinearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioural simulations are presented that demonstrate the higher efficiency of the proposed topology compared to existing cascades intended for wideband applications.

A new high-level synthesis methodology of cascaded continuous-time sigma delta modulators
R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 8, pp 739-743, 2006
abstract doi pdf

This brief presents an efficient method for synthesizing cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. In addition to placing the zeroes of the loop filter in an optimum way, the proposed methodology leads to more efficient architectures in terms of circuitry complexity, power consumption and. robustness with respect to circuit errors.

An approach to the design of cascade sigma delta modulators for multistandard wireless transceivers
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · WSEAS Transactions on Circuits and Systems, vol. 4, no. 12, pp 1811-1818, 2005
abstract

This paper discusses issues concerning the design of reconfigurable cascade sigma-delta modulators for multistandard wireless transceivers. The use of an expandible cascade modulator is considered as the starting point to boost reconfigurability at the architectural level. Then, a top-down methodology is proposed to obtain the cascade candidates that better fulfil the requirements of each standard with adaptive power consumption, taking into account the complexity of the reconfiguration at both architecture- and circuit-level. Several reconfiguration strategies are presented and validated by time-domain behavioural simulations.

A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs
J.M. de la Rosa, S. Escalera, B. Pérez-Verdú, F. Medeiro, O. Guerra, R. del Río and A. Rodríguez-Vázquez
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp 2246-2264, 2005
abstract doi pdf

This paper describes a 0.35-mu m CMOS chopper-stabilized switched-capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values ( 0.5, x 1, x 2, and x 4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40 degrees C to 175 degrees C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm(2) silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution Sigma Delta modulators.

High-level synthesis of switched-capacitor, switched-current and continuous-time sigma delta modulators using SIMULINK-based time-domain behavioral models
J. Ruiz-Amaya, J.M. de la Rosa, F.V. Fernández, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 9, pp 1795-1810, 2005
abstract doi pdf

This paper presents a high-level synthesis tool for Sigma Delta modulators (Sigma Delta Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for Sigma Delta M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of Sigma Delta Ms using both discrete-time and continuous-time circuit techniques.

Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+
R. del Río, J.M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 1, pp 47-62, 2004
abstract doi pdf

We present a 90-dB spurious-free dynamic range sigma-delta modulator (E AM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-mum CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB14 b respectively. The SigmaDelta modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the SigmaDelta modulator.

Analysis of error mechanisms in switched-current sigma-delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 38, no. 2-3, pp 175-201, 2004
abstract doi pdf

This paper presents a systematic analysis of the major switched-current ( SI) errors and their influence on the performance degradation of SigmaDelta Modulators (SigmaDeltaMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass SigmaDeltaM (2nd-LPSigmaDeltaM) and a 4th-order BandPass SigmaDeltaM (4th-BPSigmaDeltaM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in the case of 4th-BPSigmaDeltaMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI SigmaDeltaMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 mum CMOS SI 4th-BPSigmaDeltaM silicon prototype validate our approach.

Practical study of idle tones in 2nd-order bandpass Sigma Delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Microelectronics Journal, vol. 33, no. 11, pp 1005-1009, 2002
abstract doi pdf

This paper studies the tonal behaviour of the quantization noise in 2nd-order bandpass SigmaDelta modulators. Closed-form expressions for the frequency of the idle tones are derived for different locations of the signal centre frequency. The analytical results are validated through experimental measurements taken from a 0.8 mum CMOS prototype realized using fully differential switched-current circuits. (C) 2002 Elsevier Science Ltd. All rights reserved.

Conferences

Using ANNs to Predict Frequency Spectrum Occupancy in Cognitive-Radio Receivers
P.I. Okorie, L.A. Camuñas-Mesa and J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2022
abstract

This paper analyses the use of Artificial Neural Networks (ANNs) to identify vacant portions of the electromagnetic spectrum or frequency holes in Cognitive Radio (CR) systems. Several ANN topologies are considered, including Convolutional Neural Networks (CNNs), Long Short-Term Memory (LSTM) networks or hybrid combinations of them. These ANNs are modeled and compared in terms of their complexity, speed and accuracy of the prediction. As an application, a CR-based receiver is simulated, where Radio-Frequency (RF) signals are digitized by a Band-Pass Sigma-Delta Modulator (BP-ΣΔM) with a tunable notch frequency, which is modified according to the less occupied band predicted by the ANNs.

Automated Design of Sigma-Delta Converters: From Know-How to AI-assisted Optimization
J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2022
abstract

The design of analog and mixed-signal circuits is based on the well-known top-down/bottom-up methodology, which involves a number of tasks at different abstraction levels of the system hierarchy: from specifications to circuit implementation. Although there have had many efforts to optimize analog synthesis and verification procedures, existing CAD methods and tools are far from an automated design flow, as that commonly used in digital circuits.
In this scenario, this talk presents an overview of the automated design and optimization of Analog-to-Digital Converters (ADCs), which are one of the key building blocks in a vast number of digital-driven electronic systems. Without loss of generality, Sigma-Delta Modulators (ΣΔMs) are taken as case study to illustrate the analysis, modeling and design techniques under discussion. Special emphasis is put on how to combine the knowledge derived from state-of-the-art optimization algorithms, with heuristic methods and know-how, as well as recent approaches based on Artificial Intelligence (AI) algorithms, in order to maximize the performance of M ADCs while keeping computational efficiency high.

Using Software-Defined Radio Learning Modules for Communication Systems
L.A. Camuñas-Mesa and J.M. de la Rosa
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2022
abstract

The paradigm known as Cognitive Radio (CR) proposes a continuous sensing of the electro-magnetic spectrum in order to modify dynamically the parameters of transmission, making an intelligent use of the environment. This paradigm becomes especially relevant under the increasing number of IoT (Internet of Things) devices producing congestion in the spec-trum. Nowadays, many different Software-Define Radio (SDR) platforms provide with the tools to implement CR systems. In the framework of a ‘Communication Systems’ course, this paper presents a methodology to learn the fundamentals of radio transmitters and receivers doing practical experiments using commercial SDR modules.

AI-Managed Cognitive Radio Digitizers
J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2022
abstract

This paper presents an overview of circuits and systems techniques for AI-managed analog/digital interfaces with application in Software-Defined Radio (SDR) and Cognitive Radio (CR) mobile telecom systems. Some design trends and challenges are discussed, going from new communications and computing paradigms for AIoT devices and networks, to digital-based/scaling-friendly analog circuit techniques for an efficient digitization. The state of the art on Analog-to-Digital Converters (ADCs) is surveyed, putting emphasis on highly-programmable Sigma-Delta Modulators as one of the best ADC candidates for SDR/CR transceivers. Some chip examples are shown to illustrate their potential application in AI-enhanced CR end-devices.

A Low-Input Capacitance 12-Bit SAR ADC for Use in Self-Powered IoT Nodes
N. Shahpari, M. Habibi, P. Malcovati and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2022
abstract

A 12-bit low-power SAR ADC with low-input capacitance is proposed. The topology exploits a separated block structure to achieve low-input capacitance. The separated block structure uses different sub-blocks for sampling and DAC. In this structure, the comparator input common-mode voltage is variable and, therefore, a rail-to-rail comparator with rail-to-rail offset cancellation is proposed to cancel the input common-mode dependent offset. The proposed comparator is modified to overcome the uneven distribution of kickback noise too. In order to achieve a 12-bit resolution, the bootstrapped switch is modified. With the aid of the proposed offset cancellation, kickback noise reduction and switch, the ADC achieves 11.08-bit ENOB and the input capacitance is reduced to 2 pF, leading to relatively low input power consumption with no need for a reference supply voltage.

Cognitive Radio Circuits and Systems - Application to Digitizers
H. Aboushady, A. Sayed, L.A. Camuñas-Mesa and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2021
abstract

This paper gives an overview of Cognitive-Radio (CR) circuits and systems, that will enable the implementation of new technology paradigms such as software-defined electronics and Artificial Intelligence (AI) managed Internet-of-Things (IoT). A survey of the state of the art, trends and design challenges is presented from a top-down perspective - from system-level to circuit and chip implementation. As an application, special emphasis is put on analog/digital interfaces as one of the key building blocks in CR-based devices. Cutting-edge architectures - mostly based on ΣΔ Modulators (ΣΔMs) - are discussed, as well as the best candidate circuit strategies to implement CR-based digitizers in deep nanometer CMOS.

Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors
G.J. Dolecek and J.M. de la Rosa
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2021
abstract

This paper presents a low power non-recursive compensated modified comb decimation structure. A new simple wideband compensator for a modified comb is proposed. The compensator has only three coefficients, presented in a Signed Power of Two (SPT) form, which can be implemented by adders and shifts. As a result, we get a multiplierless compensator. Since the modified comb is a multiplierless filter, the overall filter is, like a comb filter, also a multiplierless filter. The compensated modified comb decreases comb-filter passband droop and improves its alias rejection. The benefits of the compensated modified comb are proven by the comparisons with the state of the art.

Analysis of Parasitic Effects on Capacitor-Loaded Broadside-Coupled Split-Ring Resonator RF Filters
P.T. Howe, N.M. Mahyuddin and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
abstract

Radio-Frequency (RF) filters are one of the key components in the front-end of wireless transceivers that can be miniaturized in order to develop cost and power efficient reconfigurable mobile terminals as those required in next generations (5G/6G) of telecom systems. However, several factors need to be investigated in order to implement multi-standard/multi-mode devices in practice. One of the critical limitations is the deviations of basic performance metrics due to fabrication process variations and effect of parasitic circuit elements. In this context, a parametric analysis on a miniaturized capacitor-loaded broadside-coupled split-ring-resonator filter in sub-6GHz band is presented in this paper. Physical and parasitic effects like substrate thickness, capacitor equivalent series resistance and capacitance variation are analyzed against the filter performance. The effect of each of these parameters on the performance of RF filters is shown such that the solutions for these effects can be considered during mass manufacturing.

Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices
C. Mohan, L.A. Camuñas-Mesa, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
abstract

The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired neuromorphic systems. Large-scale neuromorphic hardware platforms are being developed with increasing number of neurons and synapses, having a critical bottleneck in the online learning capabilities. Spike-timing-dependent plasticity (STDP) is a widely used learning mechanism inspired by biology which updates the synaptic weight as a function of the temporal correlation between pre- and post-synaptic spikes. In this work, we demonstrate experimentally that binary stochastic STDP learning can be obtained from a memristor when the appropriate pulses are applied at both sides of the device.

A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-based CT MASH ΣΔ Modulator
M. Honarparvar, J.M. de la Rosa and M. Sawan
Conference · International Symposium on Integrated Circuits and Systems ISICAS 2020
abstract

We present in this brief a novel multi-stage noise-shaping (MASH) 3-1 continuous-time (CT) delta-sigma modulator ( Σ δM ) with gated ring oscillator based quantizers (GROQs) in both stages of the cascade. The use of GROQs increases the linearity performance with respect to the conventional voltage controlled oscillator based quantizers (VCOQs) and allows a more robust extraction of the front-end stage quantization error in the time domain, thus making the proposed architecture more suitable to implement high-order expandable scaling-friendly MASH Σ δ Ms, in which the back-end stages are implemented by mostly-digital GRO-based time-to-digital converters (TDCs). The circuit has been fabricated in a 65-nm CMOS technology with 1-V supply voltage, and it operates at 640-MHz sampling frequency to digitize 10-MHz signals. To the best of the authors‚ knowledge, this is the first reported experimental validation of a GRO-based CT MASH Σ δM , featuring a 79.8-dB signal to noise ratio (SNR) at -2.2-dBFS, a 77.3-dB signal to (noise + distortion) ratio (SNDR) at -4-dBFS and a dynamic range (DR) of 81.7 dB, with a power consumption of 12-mW. These metrics demonstrate state-of-the-art performance with a DR-based Schreier FOM of 170.9 dB.

Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
abstract

Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages-coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.

Low Order Wideband Multiplierless Comb Compensator
G.J. Dolecek, L. Camuñas-Mesa and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2020
abstract

This paper presents a novel multiplierless wideband comb compensator with a low absolute value of passband deviation and a low number of adders. The number of adders depends on the number of cascaded combs, and it is between 5 and 9. Similarly, the absolute value of the passband deviation of the compensated comb depends also on the number of cascaded combs and varies from 0.06 dB (single comb) to 0.11 dB (six cascaded combs). The magnitude response of the compensator is synthesized using sinewave functions resulting in a fourth-order compensator filter. The comparisons with some recent methods from literature are presented to show the benefits of the proposed approach.

Using Neural Networks for Optimum band selection in Cognitive-Radio Systems
V. Zúñiga, L. Camuñas-Mesa, B. Linares-Barranco, T. Serrano-Gotarredona and J.M. de la Rosa
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2020
abstract

The growing development of Internet of Things (IoT) devices is producing an increasing use of the electromagnetic spectrum for wireless communications. Cognitive Radio (CR) technology provides communication terminals with the capability to select arbitrary frequency bands dynamically in order to make a more efficient use of the frequency spectrum and bands occupied by different standards and communication protocols. In this work, we propose a system which uses Long Short-Term Memory (LSTM) networks to predict the future occupation of frequency bands and modifies the specifications of the analog and radio-frequency front-end, adapting dynamically to the best communication channel. System-level simulations of a band-pass filter are shown as a case study to validate the presented approach.

Efficient Digitizers for a Digital-Driven World
J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
abstract

Data converters are key enablers for the feasible implementation of coming cyber-physical devices connected in the Internet-of-Things (IoT), where the analog/digital (A/D) interface constitutes one of their main design bottlenecks. Year after year, a number of circuits and systems techniques are embedded in different architectures of Analog-to-Digital Converters (ADCs) in order to cover a wider resolution-vs-speed conversion range. The limits of energy efficiency of ADCs are continuously pushed in order to digitize very diverse types of signals in many different applications - from ultra-low-power biomedical devices to ultra-wide-band communications.
This lecture gives an overview of some emerging data-conversion strategies at the forefront of the state of the art, which will enable the implementation of new technology paradigms such as the so-called software-defined electronics and cognitive radio.
A number of trends and design challenges in the design of efficient digitizers will be discussed, as well as the implications derived from their integration in deep-nanometer CMOS. Main limitations and problems faced by cutting-edge designs as well as tendencies, research opportunities and perspectives on the evolution of data converters will be envisioned, highlighting how they can improve their performance and efficiency in an increasingly digital-driven world.

Analysis of Linearity in FD-SOI Body-Input Voltage Controlled Ring Oscillators - Application to ADCs
J. Ahmadi-Farsani and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2019
abstract

This paper studies the use of the body terminal as control voltage of ring oscillators implemented in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) processes, thus allowing a wider tuning range of the threshold voltage. This effect is exploited in this work to improve the linearity of Voltage-Controlled Ring Oscillators (VCROs) to be used as building blocks of Analog-to-Digital Converters (ADCs). An intuitive analysis of basic VCRO current-starved inverter cells is carried out in order to derive an approximate expression of the voltage-to-frequency characteristic. Electrical simulations in a 28-nm node are shown to get insight about the influence of main design parameters and applied to the design of VCRO-based Sigma-Delta (SD) ADCs up to the layout level, whose performance metrics demonstrate the benefits of the presented approach.

A current attenuator for efficient memristive crossbars read-out
C. Mohan, J.M. de la Rosa, E. Vianello, L. Perniola, C. Reita, B. Linares-Barranco and T. Serrano-Gotarredona
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2019
abstract

This paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that drive integrate-and-fire neurons, which subsequently allows to reduce the size of integrating capacitors by several orders of magnitude, making IC integration possible. The proposed circuit uses a linear switch to divide the inference current and scale it down by a factor of about 10⁴. The proposed attenuator has been designed in 130nm CMOS technology. Simulation results considering noise, process and temperature variations are shown to validate the presented approach.

Bulk-input VCO-based sigma-delta ADCs with enhanced linearity in 28-nm FD-SOI CMOS
J. Ahmadi-Farsani and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2019
abstract

This paper investigates the use of the transistor threshold-voltage tuning feature available in 28-nm Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology in order to improve the performance of Voltage-Controlled Oscillators (VCOs) with application in Analog-to-Digital Converters (ADCs). Circuit techniques that exploit the benefits of the enhanced body-effect biasing tunnability are applied to the proposed VCO in order to improve its linearity, frequency range and robustness to technology-process variations with respect to conventional ring oscillators. The proposed circuit is applied to the design of a second-order ΣΔ ADC clocked at a configurable rate of 1-to-2 GHz. The ADC uses a multi-phase VCO-based front-end integrator as the only analog circuit, while the rest of its building blocks are digital circuits. Transistor-level simulations show that the presented techniques improve the linearity with respect to conventional VCO-based ΣΔMs, featuring 10-bit effective resolution within a 10-MHz signal bandwidth, with an estimated power consumption of 230μW.

A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation
S. Asghar, S. Saadat Afridi, A. Pillai, A. Schuler, J.M. de la Rosa and I. O'Connell
Conference · International Symposium on Integrated Circuits and Systems ISICAS 2018
abstract

Asynchronous spiking pixel with programmable sensitivity to illumination
J.A. Leñero-Bardallo, M. Delgado-Restituto, R. Carmona-Galan and A. Rodriguez-Vazquez
Conference · International Symposium on Integrated Circuits and Systems ISICAS 2018
abstract

A spiking pixel to be used in image sensor arrays for asynchronous frame-based operation is presented. The pixel features both local and global adaptive sensitivity to the illumination level. Local adaptation is performed by adjusting the voltage stored in an embedded analog memory according to the average illumination within a neighborhood. Global adaptation to the overall illumination of the array is implemented by adjusting a voltage value common to all the pixels. These programming capabilities allow full control on the sensor sensitivity, pixel output data flow, and energy consumption, thus, overcoming the limitations observed in current image sensors based on spiking pixels. Experimental results validate the functionality of the proposal.

A 0.9-V 100-μW Feedforward Adder-Less Inverter-based MASH ΔΣ Modulator with 91-dB Dynamic Range and 20-kHz Bandwidth
M. Honarparvar, J.M. de la Rosa and M. Sawan
Conference · International Symposium on Integrated Circuits and Systems ISICAS 2018
abstract

Embedding MATLAB Optimizers in SIMSIDES for the High-Level Design of ΣΔ Modulators
B. Cortés-Delgadillo, P.A. Rodríguez-Navas and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract

This paper shows how to combine SIMSIDES, a SIMULINK-based time-domain behavioral simulator, with the different optimization engines available in MATLAB for the automated high-level design of ΣΔ modulators. To this purpose, an updated version of SIMSIDES has been developed, which includes a user-friendly interface that links the simulator with the optimizers, and guides designers through the main steps required to set the design variables, constraints and select the most suitable algorithm to maximize the performance of an arbitrary modulator topology for a given set of specifications. Several examples and results of the optimization procedure are shown to illustrate the benefits of the presented tool for the highlevel synthesis of ΣΔ modulators.

Man or Machine - Design Automation of Delta-Sigma Modulators
J. Wagner, M. Ortmanns and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract

This paper presents a state-of-the-art overview and recent advances on circuit and system level design methods and EDA tools for the automation and optimization of Delta-Sigma (ΔΣ) modulators. Main synthesis strategies and techniques are highlighted, putting emphasis on those aspects, which need to be taken into account in order to maximize the performance of ΔΣ converters, while keeping computational efficiency high. Based on the comparison of the approaches considered in this survey, the authors try to answer, where man or machine can come in.

Behavioral Modeling of SAR ADCs in Simulink
G. Molina-Salgado, A. Dicataldo, D. O'Hare, I. O'Connell and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract

This paper presents a toolbox for the behavioral simulation of SAR ADCs in Simulink®. The models include the most limiting circuit effects such as sampled thermal noise, capacitor mismatch, finite settling, comparator noise and offset. A user friendly interface is also included to allow study and high-level design of SAR ADCs, which is illustrated by means of a design example. It is also shown that the proposed toolbox is several orders of magnitude faster than electrical simulators, while keeping a high accuracy.

A 2MS/s, 11.22 ENOB, 3.2 V_pp-d SAR ADC with improved DNL and offset calculation
S. Asghar, S. Afridi, A. Pillai, A. Schuler, J.M. de la Rosa and I. O'Connell
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract

A 12-bit SAR ADC with an extended input range of 3.2 V_pp-d (±1.33 VREF) achieved through the use of an input sampling scaling technique, is presented. The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The ADC is implemented in a 0.13 μm CMOS process and achieves an SNDR of 69.3 dB and an SFDR of 79 dB without calibration, while consuming 0.9 mW, with a measured DNL of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.

Design Considerations of Mash ΔΣ Modulators with GRO-Based Quantization
M. Honarparvar, J.M. de la Rosa, F. Nabki and M. Sawan
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract

A gated ring oscillator (GRO) based multi-stage noise-shaping ΔΣ modulator (ΔΣM) is presented in this paper. Loop-filter integrators followed by a digitally implemented GRO make the proposed architecture suitable for scaling-friendly implementations. Quantization noise of the first stage is represented in the time domain and it eases the quantization error extraction with a simple digital circuitry. The GRO offers inherent dynamic element matching, and hence no extra circuitry is needed to linearize the DACs in the feedback path. Time-domain behavioral simulations are shown to study of main GRO non-idealities considering a discrete-time MASH 3-1 topology, featuring a SNDR of 94 dB for an OSR of 16 over a 2-MHz signal bandwidth.

Bulk-based DC offset calibration for Low-power Memristor Array Read-Out System
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, L. Perniola, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2017
abstract

Memristors in neuromorphic circuits typically need to drive currents of many mA because their Low Resistance State (LRS) is in the order of a few kΩ and many devices need to be activated simultaneously which results in high power consumptions. Reducing read-out pulses amplitudes below the typical 0.1V is not trivial, as offset voltages of read-out circuits start to affect the results. This paper presents a three-stage cascaded calibration to compensate for the resting offset voltage of crossbar lines generated in the amplifiers driving memristive devices in memristor array read-out systems. The proposed calibration technique is based on adjusting the bulk voltage of the input differential pairs by means of a switchable cascade of resistor ladders. As a result, the calibrated offset voltage can be further reduced with the number of stages in the cascade, leading to a calibration voltage step below 0.1mV -only limited in practice by mismatch and electrical noise. The circuit has been designed in 130nm CMOS technology, and its operation has been verified with oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in neuromorphic circuits. Layout-extracted simulations considering PVT variations are considered to validate the presented calibration technique.

Design Automation of ΣΔ Converters: A Review of Modeling, Synthesis and Optimization Techniques
J.M. de la Rosa
Conference · Electron Devices and Solid-State Circuits EDSSC 2017
abstract

This work presents an overview of the state of the art and recent advances on CAD tools for the design automation and optimization of ΣΔ converters. System-level modeling and simulation strategies are outlined, putting emphasis on how they can be combined with heuristic techniques and know-how to maximize the performance of data conversion based on Modulators.

Emerging Sigma-Delta Modulation Techniques for an Efficient Digitization in the Internet of Things
J.M. de la Rosa
Conference · International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2017
abstract

This talk gives an overview of ΣΔ modulation techniques for the efficient implementation of analog/digital interfaces in IoT devices. Main design challenges derived from their integration in deep nanometer CMOS are identified, and state-of-the-art circuits and systems solutions are discussed. Diverse application scenarios, ranging from ultra-low-power biomedical devices to ultra-wide-band wireless communications, are considered as case studies.

Novel Band-Pass ΔΣ Modulators Based on a Modified Adder-Less Feed-Forward Structure
M. Honarparvar, J.M. de la Rosa, F. Nabki and M. Sawan
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2017
abstract

Two Band-Pass (BP) Discrete Time (DT) Delta-Sigma (DS) modulators are proposed in this paper. In both cases, the drawback of high-speed power-hungry adder is tackled by proposing a modified unity signal transfer function (STF) adder-less feed- forward structure. The first proposed BP DT DS modulator is a conventional adder-less multi-stage noise shaping (MASH) DS modulator, while the noise leakage problem, caused by the mismatches between analog loop filter and digital cancellation logic (DCL), is mitigated by proposing a second topology in which the DCL is omitted. All of these features make the proposed modulators suitable for low-voltage and low-power applications, while the second proposed topology features a higher robustness against noise leakage and mismatch. Time-domain behavioral simulations show a 0-dBFS overload input level for the proposed architectures while the DC-gain is relaxed for the second proposed architecture such that a 67-dB SNDR can be obtained with only a 30-dB amplifier DC-gain at a -20-dBFS input signal level.

On the Use of Offset Calibration Techniques for Low-Power Memristor Arrays Read-Out
C. Mohan, T. Serrano-Gotarredona, J.M. de la Rosa and B. Linares-Barranco
Conference · International Conference on Memristive Materials, Devices & Systems MEMRISYS 2017
abstract

Neuromorphic RRAM circuits need typically to drive currents of many mA because the low resistance state is in the order of a few kΩ and many devices need to be activated simultaneously, thereby resulting in high power consumptions. Reducing read-out pulses amplitudes below the typical 0.1V is not trivial, as offset voltages of read-out circuits start to affect the results. This paper presents a calibration circuit to compensate for the resting offset voltage of crossbar lines generated in the amplifiers driving memristive devices in memristor array readout systems. The proposed calibration technique is based on adjusting the bulk voltage of the input differential pairs by means of a switchable cascade of resistor ladders. As a result, the calibrated offset voltage can be further reduced with the number of stages in the cascade, leading to a calibration voltage step below 0.1mV -only limited in practice by mismatch and electrical noise. The circuit has been designed in a 130-nm CMOS technology, and its operation has been verified with oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in neuromorphic circuits. Layout-extracted simulations considering PVT variations are shown to validate the presented calibration technique.

Designing High-Performance ΣΔ Converters - All You Need to Know and Nobody Told You + Future Applications
J.M. de la Rosa, S. Pavan, N. Maghari and S. Ho
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
abstract

The main objective of the tutorial is to give a comprehensive overview of ΣΔ converters, their state-of-the art performance, applications, design challenges and practical solutions as well as how to address a real design by following an efficient and systematic design methodology. All these ingredients are put together with a huge list of bibliographic references, design recipes and advises that will allow the audience to learn many practical tricks about the design of ΣΔ modulators ¿ from theory and system level aspects to experimental characterization. Future design trends and applications of these converters will also be presented.

Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms
M. Velasco-Jiménez, R. Castro-López and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
abstract

This demo shows how to use multi-objective evolutionary algorithms for the optimum high-level design of ΣΔ analog-to-digital converters. The methodology illustrated in the demo is based on the combination of SIMSIDES, a SIMULINK-based time-domain behavioral simulator for ΣΔ modulators, with multi-objective optimization techniques. The proposed methodology allows designers to explore the design space in an efficient and intuitive way in order to fulfill a number of different design objectives simultaneously, by finding out the best sets of target specifications - defined as Pareto-optimal fronts. The presented approach can be extended to several kinds of optimizers implemented in MATLAB, and diverse examples are illustrated so that visitors will learn how to apply it to their own designs and projects. Although the demo is focused on ΣΔ ADCs, the tools shown in the demo can be used for the optimization of any other analog integrated circuits and systems.

Design Guidelines of ΣΔ Modulators: From System to Chip and Application to Reconfigurable ADCs
J.M. de la Rosa
Conference · Conference on Electron Devices and Solid-State Circuits EDSSC 2016
abstract

This paper presents a tutorial guide for the systematic design of ΣΔ Modulators from system-level specifications to circuit-level design and silicon implementation. The whole design flow is outlined and illustrated by several case studies and chip examples intended for reconfigurable ADCs in multi-standard wireless telecom systems.

Using Arduino and On-Chip Serial-to-Parallel Register to Test Widely-Programmable ADCs
L.A. García-Lugo, E.C. Becerra-Alvarez, J. Ceballos-Cáceres and J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
abstract

This paper presents an experimental set-up that combines on-chip digital techniques with off-chip Arduino-based hardware to simplify the test of widely-programmable analog-to-digital converters. The presented methodology is specially intended for analog and mixed-signal circuits which require a large number of digital signals to reconfigure their performance to different electrical specifications, environment signal conditions, battery status, etc. To this end, a serial-to-parallel register is implemented on chip in order to generate the required number of digital control signals from an input serial data provided offchip. Such serial data can be generated by using an Arduino-based hardware set-up, which can be easily programmed in MATLAB, with no additional test instruments required. As an application, the proposed method is applied to the experimental characterization of a fourth-order band-pass continuous-time ΣΔ modulator, integrated in a 65-nm CMOS technology, which can digitize signals placed at programmable carrier frequencies for software defined radio.

Design of a 9-bit 4MS/s Wilkinson ADC for SiPM-based Imaging Detectors
G. Fernandez, D. Gascon and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2016
abstract

This paper presents the design and electrical implementation of a Wilkinson analog-to-digital converter for imaging detectors based on the use of silicon photo-multiplier scintillators. A multi-channel architecture, which shares the ramp generator among the different channels, is used to maximize the sampling frequency with the minimum power consumption and silicon area. The circuit has been implemented in a 0.35-μm CMOS technology up to the layout level, featuring state-of-the-art performance with 9-bit effective resolution, 4-MS/s sampling frequency, 0.95mW/channel, while clocked at 2.56GS/s with 1.5-V full-scale range.

Design of a Power-Efficient Widely-Programmable Gm-LC Band-Pass Sigma-Delta Modulator for SDR
A. Morgado, R. del Río, J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
abstract pdf

This paper presents the design and layout implementation of a fourth-order band-pass continuous-time Sigma-Delta (SD) modulator intended for the digitization of radio-frequency signals in software-defined-radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the feedforward path and a non-return-to-zero digital-to-analog converter with a finite-impulsive-response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65- nm CMOS, can digitise signals with up to 57-dB SNDR within 40-MHz bandwidths, with an adaptive power dissipation of 16.7- to-22.8 mW, and a programmable 1.2/2GHz clock rate.

High-Level Optimization of Sigma-Delta Modulators using Multi-Objetive Evolutionary Algorithms
M. Velasco-Jiménez, R. Castro-López and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
abstract

This paper presents a high-level synthesis methodology based on the use of multi-objective evolutionary algorithms for the optimization of Sigma-Delta (SD) modulators. Compared to conventional approaches, the proposed method allows to explore a number of different design objectives simultaneously in the design space in order to find out the best sets of target specifications -- defined as Pareto-optimal fronts. This strategy leads to more efficient designs in terms of effective resolution, bandwidth and power consumption. As an application, the proposed method is applied to the high-level design of a 65-nm CMOS LC-based fourth-order band-pass continuous-time SD modulator, showing a number of experiments to validate the presented approach.

Introduction to the IEEE-CASS Workshop on Micro/Nanoelectronic Circuits and Systems
T. Serrano-Gotarredona and J.M. de la Rosa
Conference · International Conference on Computer as a Tool EUROCON 2015
abstract

Very few social and technological revolutions in the history of humankind have become as vertiginous as the one experienced in the first decade of the 21st century. In fact, it would be very difficult to explain our present society without resorting to the so-called Information Technologies, and particularly to some technological achievements such as the Internet, mobile phones and social networks. Technology downscaling toward deep nanoscale level has allowed to put billions of transistors together in a single chip, thus making it possible to integrate entire systems with increasingly number of applications, which span from consumer electronics and computing to telecom and biomedical devices.

A Comparative Study of nanoHUB Tools for the Simulation of Carbon-based FETs
J.M. de la Rosa
Conference · nanoHUB User Conference 2015
abstract

This work compares the different tools available in nanoHUB for the electrical simulation of carbon- based field-effect transistors made up of either carbon nanotubes (CNTs) or graphene. Among others, the following tools are considered: CNTbands, CNTFET lab, FETToy and GFET tools. Electrical (I-V) characteristics are simulated by using these tools and compared with those obtained by reported models for SPICE-like electrical simulators. Main figures are compared from a circuit designer¿s viewpoint, in terms of main performance metrics, accuracy, reliability and design parameters for their use in practical circuit design.

Sigma-Delta converters: fundamentals, state of the art and applications
J.M. de la Rosa
Conference · Selected Topics on Advanced Research on Circuits and Systems STAR-CAS 2015
abstract

This lecture presents a tutorial overview of Sigma-Delta Modulators, their basic concepts, fundamental architectures and circuits, and new generations of topologies which are pushing the state of the art on Analog-to-digital Converters (ADCs) forward in a number of application scenarios. A number of emerging topics, trends and circuits and systems techniques - like radio-frequency and ultra-high speed (GHz-range) digitization; passive, amplifier-less and mostly-digital circuit implementations; time-coded quantization; hybrid SDM/Nyquist-rate topologies, etc. - are surveyed, as well as the implications derived from their integration in deep nanometer CMOS technologies. Main limitations and problems faced by cutting-edge designers are identified, giving a didactic explanation of all of them, supported by an exhaustive statistical analysis of more than 500 outstanding ICs in the frontiers of analog-digital interfaces.

A Comparison of CAD Tools for the Study of Nanoelectronic Devices, Circuits and Systems
José M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
abstract

This paper overviews diverse CAD tools for the study of nanoelectronics in both research and education, putting emphasis on circuits made up of carbon-based field-effect transistors, namely carbon nanotubes (CNTs) and graphene. Some tools available in nanoHUB.org are outlined and compared with other traditional/conventional methods which are based on reported models for the simulation of CNT/G-FET devices and circuits in Verilog-A, SPICE-like simulators and MATLAB. Their main features are analyzed from a circuit designer viewpoint, in terms of main performance and characterisation metrics for their use in the analysis, modeling and design of integrated devices, circuits and systems. The knowledge derived from this research is applied to improve the teaching and learning experience of students enrolled in diverse courses dealing with nanoelectronics and materials engineering degrees, through the incorporation of virtual labs and projects based on the use of the tools outlined in this study.

RF to Digital Sigma Delta Converters - Design Trends, Challenges and Applications
J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
abstract

Abstract not avaliable

On the Use of Passive Circuits to Implement LC-based Band-Pass CT ΣΔ Modulators
G.M. Salgado, G. Jovanovic-Dolecek and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2015
abstract

This paper discusses the use of passive circuits for the implementation of band-pass continuous-time ΣΔ modulators intended for digitizing radio-frequency signals in wireless communication systems. Several alternative loop filters, considering either a fully passive or an hybrid active/passive circuit realization of the embedded resonators, are applied to the high-level design of fourth-order single-loop band-pass ΣΔ modulators with current-mode feedback digital-to-analog converter. The resulted modulator topologies are synthesized considering a widely programmable notch frequency, and compared in terms of their sensitivity to main circuit error mechanisms, including finite output swing, quality factor of inductors, and technology process variations. Time-domain simulations validate the presented approach, showing the feasibility of using fully passive and hybrid active/passive resonators to implement band-pass continuous-time ΣΔ analog-to-digital converters.

Novel two-stage comb decimator with improved frequency characteristic
G.M. Salgado, G.J. Dolecek and J.M. de la Rosa
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2015
abstract

This paper presents a novel low-power two-stage comb-based decimator in which the passband droop is decreased and the attenuation in all odd folding bands are increased. This is achieved by using simple corrector filter and the sharpening technique in the second stage. The only design parameter is the number of the cascaded comb filters K in the first stage. However, the second stage remains the same for all values of the parameter K. The proposed method is compared with the similar methods in the open literature. FPGA implementation proves that the proposed structure has improved characteristics at the cost of an increase of 33.3% in power consumption, compared with the comb.

Simulation-Based Comparison of CNT-FETs and G-FETs from a Circuit Designer's Perspective
M. Porcel de Soto and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2015
abstract

This paper compares the performance achieved by carbon-based field-effect transistors made up of either carbon nanotubes or graphene, based on the SPICE models reported for the electrical simulation of these devices. The results achieved by these models are compared with silicon-based conventional CMOS devices, in terms of their main electrical (IDS-vs-VDS and IDS -vs-VGS) characteristics as well as their fundamental performance metrics, including the intrinsic voltage gain, Av, transconductance efficiency, gm/IDS, and transit frequency, fT. These figures of merit are obtained for diverse biasing and sizing conditions, and discussed from a circuit designer's perspective, in order to determine the benefits and drawbacks of the materials and devices under study. As an application, some carbon-based basic analog and digital circuits are designed and compared with their CMOS counterparts, in order to highlight their potential advantages in each case.

Overview of Carbon-Based Circuits and Systems
S. Rodriguez, A. Rusu and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2015
abstract pdf

This paper presents an overview of the state of the art on carbon-based circuits and systems made up of carbon nanotubes and graphene transistors. A tutorial description of the most important devices and their potential benefits and limitations is given, trying to identify their suitability to implement analog and digital circuits and systems. Main electrical models reported so far for the design of carbon-based field-effect devices are surveyed, and the main sizing parameters required to implement such devices in practical integrated circuits are analyzed. The solutions proposed by cutting-edge integrated circuits and devices are discussed, identifying current trends, challenges and opportunities for the circuits and systems community.

Energy Efficient Transconductor for Widely Programmable Analog Circuits and Systems
A. Morgado, R. del Río and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2015
abstract

This paper presents a novel transconductor which is widely tunable and reconfigurable to a number of circuit specifications with an adaptive power consumption. Current- starving techniques are combined with programmable output stages so that the output current range and granularity can be arbitrarily set, while increasing energy efficiency with the number of active stages. These characteristics make the proposed circuit very suited to enlarge the autonomy and battery life in a number of portable multi-mode/multi-standard devices, spanning from biomedical applications and mobile phones to wireless sensor networks.

Sigma-Delta ADCs for Software-Defined-Radio Applications
G. Molina-Salgado, G. Jovanovic-Dolecek and J.M. de la Rosa
Conference · IFIP/IEEE Int. Conference on Very Large Scale Integration VLSI-SoC 2014
abstract

Abstract not avaliable

Design Guide of High-Performance Sigma-Delta Data Converters: From Specifications to Chip Implementation and Measurements
J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2014
abstract

This tutorial presents a systematic, comprehensive and practical description of high-performance Sigma-Delta Modulators (ΣΔMs), their state-of-the-art architectures, circuit techniques, analysis and synthesis methods and CAD tools, as well as their practical design considerations -going from system-level specifications to silicon integration, prototyping, and measurements. A number of case studies and examples are given to illustrate the design considerations explained in the tutorial, covering the whole design flow of ΣΔ ADCs, and putting emphasis on their application to the efficient implementation of Software-Define-Radio (SDR) and RF-to-digital conversion. Although the tutorial focuses on ΣΔ converters, the practical recipes and design procedures discussed during this course can be extended and applied to the design of other kinds of high-performance data converters.

An overview of decimator structures for efficient sigma-delta converters: Trends, design issues and practical solutions
G. Molina Salgado, G. Jovanovic Dolecek and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2014
abstract

Classical decimation structures usually use comb filters at first stage due to the simplicity of comb filters. However, comb filters cannot satisfy high performance demands of state-of-the-art Sigma-Delta (ΣΔ) analog-digital converters (ADCs). Some possible solutions are comb based structures which are power and area efficient and posses an improved magnitude characteristic. The principal issues in the comb-based filter design are: power and area efficiency, high alias rejection and approximately flat passband characteristic, considering also high values of the decimation factors. In this paper we first review the new trends in ΣΔ ADCs and demands for the decimation block design. Next we review power and area efficient structures. The methods to improve the alias rejection of comb filters, as well as the methods for the compensation for the comb passband droop, and those strategies which simultaneously improve the alias rejection and the passband droop are reviewed in the following. Finally we review the multirate decimation structures.

Design considerations of bandpass CT ΣΔ modulators for software-defined-radio receivers
G. Molina Salgado, G. Jovanovic Dolecek, A. Morgado and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2014
abstract

This paper discusses design considerations of LC-based bandpass continuous-time ΣΔ modulators intended for the analog-to-digital conversion of radio-frequency signals in software-defined-radio receivers. A top-down high-level synthesis methodology -based on the combination of undersampling techniques, programmable notch frequency and adequate selection of loop-filter coefficients- is presented to design efficient modulator architectures, which can be adapted to fulfill the requirements of diverse wireless communication standards, while keeping stability and robustness to circuit errors. Main architectureand circuit-level design issues are analyzed, considering diverse case studies based on Gm-LC resonators and different kinds of digital-to-analog converters. Time-domain simulations validate the presented approach1.

Live Demonstration: Using SIMULINK S-functions for the Efficient Modeling and Simulation of Analog Integrated Circuits and Systems
J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2014
abstract

This demo shows how to implement efficient behavioral modeling and simulation techniques for the systematic design of analog circuits and systems in MATLAB/SIMULINK. The methodology described in the demo is based on the use of C-coded SIMULINK S-functions to develop precise models of analog circuits, which allow designers to simulate complex systems with reduced simulation time, while keeping high accuracy. This simulation approach can be combined with an optimizer to automate the high-level synthesis and verification of many different analog integrated systems. As an application, two different toolboxes developed using the proposed techniques are illustrated in this demo: one is intended for the simulation of wireless receivers and the other one focuses on ΣΔ data converters. Through the multiple examples included in these toolboxes, visitors will experience the philosophy behind the presented approach and will learn how to apply it to their own designs and projects. ISCAS Track: Analog Signal Processing.

Single Event Transients trigger instability in Sigma-Delta Modulators
D. Malagon, J.M. de la Rosa, R. del Río and G. Leger
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2014
abstract

In this paper we emulate the errors caused by SET in a Flexible 4th-Order Sigma-Delta Modulator with DC-to-44MHz Tunable Center Frequency in 1.2-V 90-nm CMOS. We identify the virtual ground of the integrators as a sensitive node and show that a charge injection may drive the modulator into long-term instability.

Spatial Detection System for Mini-Secondary Electrons Detectors
A. Garzón-Camacho, B. Fernández, M.A.G. Alvarez, J. Ceballos and J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2014
abstract

This paper describes the design and experimental characterization of an electronic front-end intended for spatial detection of ion beams at counting rates over 10^6 particles per second (pps). A multi-channel system architecture is considered, which is essentially made up of three main sub-systems: a TIA, a line receiver and a charge-to-digital converter. A number of experiments have been carried out considering different particles sources and physical conditions, demonstrating that the presented readout electronics is very appropriate for fast and precise particle tracking in secondary electrons detectors.

Modified Comb Decimator for High Power-of-Two Decimation Factors
J.M. de la Rosa
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2014
abstract

This paper presents a modified two-stage comb decimation structure for Sigma-Delta Analog-to-Digital Converters (ADC) with high decimation factor, which can be implemented as a power of two. The proposed structure exhibits a decreased passband droop, as well as increased attenuations in the folding bands compared with the power and area efficient structures recently proposed in the literature. This is achieved by introducing a simple corrector filter at second CIC (Cascaded- Integrator-Comb) stage, such that it works at the rate, which is less than the high input rate by half of the decimation factor. The corrector filters depend only on the number of the cascaded equivalent combs. In that way the same corrector can be used for the comb decimator with different decimation factors but with the equal number of the cascaded combs. The comparison with the power and area efficient comb-based structures from literature, and the VHDL implementation, confirm the efficiency of the proposed structure.

Behavioral Modelling of a 4th order LP ΣΔ Modulator-Towards the design of a Hybrid proposal
J.M. de la Rosa
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2014
abstract

Hybrid ΣΔ modulator has the property of take advantage of the capabilities of CT and DT architectures and is thus very effective in the cascade approach. In this paper, we show the behavioral simulation of ΣΔ modulators in SIMSIDES. A set of experiments based on models for analyzing the overall performance of SC ΣΔ modulators were used in order to translate design considerations into a set of values such that the design at transistor level be established by the desired performance of the proposed architecture. This design methodology is not the most accurate but it allows the designer to get a general comprehension of the system under design, a comprehension at the highest level of abstraction. The system under study is a cascade 4th order hybrid ΣΔ modulator, from which the second stage is a 2nd order Low-Pass (LP) DT ΣΔ modulator. The ideal behavioral performance of the DT modulator is used as vehicle to show how non-idealities must be taken into account, and also how to translate design considerations into a set of physical values for designing building blocks at transistor level.

Readout Electronics System for Particle Tracking in Secondary Electron Detectors
A. Garzón-Camacho, B. Fernández, M.A.G. Alvarez, J. Ceballos and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2014
abstract

This paper presents the design and implementation of an electronic front-end intended for spatial detection of ion beams at counting rates higher than 10^6 particles per second. The readout system is made up of three main multi-channel building blocks, namely: a transimpedance preamplifier, a signalconditioning line receiver and a charge-to-digital converter, which are properly combined with some off-the-shelf components. Several experiments have been carried out, considering α particles sources and particles beams, featuring an adaptive shaping time frame of 170-to-230 ns with a peak signal-to-noise ratio of up to 25.2dB. These performance metrics are competitive with the state of the art, showing the suitability of the proposed data acquisition system for accurate and fast particle tracking detection.

Comb Structures for Sigma-Delta ADCs with High Even Decimation Factors
G. Molina-Salgado, G. Jovanovic-Dolecek and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2014
abstract

This paper analyses comb-based decimation structures for Sigma-Delta Analog-Digital Converters (ADCs), with high even decimation factors. The topology under study has two stages: the first stage is a non-recursive-comb and the second one is a CIC (Cascaded-Integrator-Comb) structure. As a result, efficient structures are identified in terms of the power consumption and silicon area. Additionally, alternative topologies are proposed to improve alias rejections of the analyzed decimator structures.

Improving the Learning Experience of Micro/Nanoelectronic Materials and Devices with nanoHUB
J.M. de la Rosa
Conference · nanoHUB User Conference 2014
abstract

This poster illustrates how to incorporate some simulation tools provided by nanoHUB as part of the virtual labs included in undergraduate and master courses given in Electrical and Materials Engineering degrees. The work is based on the experience of the author over the last five years by teaching Electronic Materials and Devices integrated in micro/nano-technologies. The reported activities - carried out in class and linked to an e-learning virtual environment - allowed students to improve their learning experience of the different topics covered in the course and to get a deep insight and a better intuition about nanotechnology - from physical principles and concepts to device/circuit simulation and fabrication.

Efficient Behavioral Modeling and Simulation Techniques for the Systematic Design of Analog Integrated Circuits and Systems: Application to Wireless Receivers and Sigma-Delta Converters
J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2013
abstract

This tutorial presents a comprehensive description of behavioral modeling and simulation techniques, showing how to implement these techniques in an efficient way using MATLAB/SIMULINK. The methodology described in this tutorial is based on the use of the so called C-coded SIMULINK S-functions to develop precise models of analog circuits, which allow designers to simulate complex systems with reduced simulation time, while keeping high accuracy. This simulation approach can be combined with an optimizer to automate the high level synthesis and verification of many different analog integrated systems. As an application, two different toolboxes developed using the proposed techniques are illustrated in this tutorial: one is intended for the simulation of wireless receivers and the other one focuses on ΣΔ data converters. Through the multiple examples included in these toolboxes, tutorial attendees will get inside into the philosophy behind the presented approach and will learn how to apply it to their own designs and projects.

Power and Area Efficient Comb-Based Decimator for Sigma-Delta ADCs with High Decimation Factors
G. Molina-Salgado, G. Jovanovic Dolecek and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2013
abstract pdf

This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.

An Empirical and Statistical Comparison of State-of-the-Art Sigma-Delta Modulators
J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2013
abstract

This paper examines and compares the state of the art in ΣΔ Modulators from an empirical but systematic perspective. Statistical data extracted from more than 300 cutting-edge integrated circuits have been exhaustively analyzed to identify trends, design challenges, as well as the most efficient solutions proposed for different application scenarios in the frontiers of the ΣΔ modulation technique. The results of this study are presented as design guidelines in order to help designers to select the optimum ΣΔ architecture and circuit implementation for a given set of specifications.

Band-Pass Continuous-Time ΣΔ Modulators with Widely Tunable Notch Frequency for Efficient RF-to-Digital Conversion
G. Molina-Salgado, G. Jovanovic-Dolecek and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2013
abstract

This paper presents a design methodology to synthesize band-pass continuous-time ΣΔ modulators with a widely programmable notch frequency for the efficient digitization of radio-frequency signals in the next generation of software-defined-radio mobile systems. The presented modulator architectures are based on a fourth-order loop filter - implemented with two LC-based resonators - and a finite-impulsive-response feedback loop to increase their flexibility and degrees of freedom, considering three different cases for the digital-to-analog converter waveform, namely: a return-to-zero, a non-return-to-zero and a raised-cosine waveform. In all cases, the notch frequency can be reconfigured from 0.1fs to 0.4fs, while keeping the noise shaping performance, stability and low sensitivity to circuit-element tolerances. This feature can be combined with undersampling techniques to achieve an efficient and robust digitization of 0.5-to-5GHz signals with scalable resolution and programmable signal bandwidth.

Undersampling RF-to-Digital CT ΣΔ Modulator with Tunable Notch Frequency and Simplified Raised-Cosine FIR Feedback DAC
S. Asghar, J.M. de la Rosa and R. del Río
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2013
abstract pdf

This paper presents a continuous-time fourth-order band-pass Sigma-Delta (SD) Modulator for digitizing radio-frequency signals in software-defined-radio mobile systems. The modulator architecture is made up of two resonators and a 16-level quantizer in the feedforward path and a raised-cosine finite-impulsive- response feedback DAC. The latter is implemented with a reduced number of filter coefficients as compared to previous approaches, which allows to increase the notch frequency programmability from 0.0375fs to 0.25fs, while keeping stability and robustness to circuit-element tolerances. These features are combined with undersampling techniques to achieve an efficient and robust digitization of 0.455-to-5GHz signals with scalable 8-to-15bit effective resolution within 0.2-to-30MHz signal bandwidth, with a reconfigurable 1-to-4GHz sampling frequency.

Effect of Circuit Errors and Hybrid Continuous-Time/Discrete-Time Sigma-Delta Modulators
J.G. García-Sánchez and J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2012
abstract

This paper analyses the effect of circuit nonidealities on the performance of hybrid continuous-time/discrete-time modulators. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies. The effect of three error mechanisms is considered, namely: mismatch, finite dc gain error and finite gain-bandwidth product. In all cases, closedform expressions are derived for the nonideal in-band noise power of all modulators under study, giving an analytical relation between their system-level performance and the corresponding circuit-level error parameters. Time-domain behavioral simulations are in good agreement with theoretical predictions, demonstrating the validity of the presented approach.

A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW Flexible 4th-Order SD Modulator with DC-to-44MHz Tunable Center Frequency in 1.2-V 90-nm CMOS
S. Asghar, R. del Río and J.M. de la Rosa
Conference · IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2012
abstract pdf

This paper describes the design of a switched-capacitor fourth-order single-loop ΣΔ modulator with a 5-level embedded quantizer. The loop filter consists of a cascade of resonators with distributed feedforward coefficients, which can be programmed to make the zeros of the noise transfer function variable. As a result, the modulator can be reconfigured either as a lowpass or as a bandpass analog-to-digital converter with a tunable notch frequency and an optimized loop-filter zero placement. The circuit -designed and implemented in a 1.2-V 90-nm CMOS technology- incorporates diverse architecture- and circuit-level strategies to adapt its performance to different sets of specifications with a variable sampling frequency of 100 and 200MHz and scalable power consumption. Post-layout simulations (for a frequency range of DC to 22MHz) and behavioral simulations (from 22 to 44MHz) show a correct operation of the circuit in steps of 1-to-2MHz, featuring an adaptive SNDR of 74-to-86, 57-to-68 and 50-to-59dB within a signal bandwidth of 200kHz, 1MHz and 2MHz, respectively, while dissipating a scalable power consumption of 16-to-22mW.

Hybrid continuous-time/discrete-time circuit techniques for the efficient implementation of wideband ΣΔ ADCs
J.G. García-Sánchez and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2012
abstract

This paper discuses the use of hybrid continuous-time/discrete-time ΣΔ modulators for the implementation of high-efficiency wideband analog-to-digital converters. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies. The effect of three error mechanisms is considered, namely: mismatch, finite dc gain error and finite gain-bandwidth product. In all cases, closed-form expressions are derived for the nonideal in-band noise power of all ΣΔ modulators under study, giving an analytical relation between their system-level performance and the corresponding circuit-level error parameters. Time-domain behavioral simulations are in good agreement with theoretical predictions, demonstrating the validity of the presented approach.

A power-scalable concurrent cascade 2-2-2 SC ΣΔ modulator for Software Defined Radio
A. Morgado, J.G. García, S. Asghar, L.I. Guerrero, R. del Río and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
abstract pdf

This paper presents a flexible 1.2-V 90-nm CMOS cascade three-stage SC ΣΔ modulator with local resonation in the last two stages, unity signal transfer function and programmable (either 3 or 5 level) quantization in all stages. The chip reconfigures its loop filter order (2nd, 4th, 6th order), the clock frequency (from 40 to 240MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental results demonstrate the flexibility of the proposed modulator, featuring a programmable noise shaping within a 100kHz-to-10MHz signal band, with adaptive power dissipation.

A preamplifier for the front-end readout system of particles tracking in secondary electron detectors
A. Garzón-Camacho, B. Fernandez, M.A.G. Alvarez, J. Ceballos and J.M de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
abstract pdf

This paper presents the design and characterization of a preamplifier used in the electronic front-end of low-pressure gaseous secondary electron detectors. The circuit -implemented in a printed circuit board as a proof of concept -has been designed to cope with the specifications of the readout electronics used in spatial resolution measurements. Experimental results show a transimpedance gain of 80dB, an overall voltage gain of 18 dB, a peak signal-to-noise ratio of 36.5 dB and a shaping time frame of 140-170ns. These features improve the performance of previous reported approaches to the problem, and allow us to minimize the overlapping probability in secondary electron detections for radioactive ion beams tracking, achieving a counting rate higher than 106 particles per second.

Behavioral modeling techniques for teaching communication circuits and systems
J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
abstract pdf

This paper discusses the use of behavioral simulation techniques to improve the quality of teaching/learning circuits and systems for communications. The proposed pedagogical methodology has been applied in several electrical engineering courses, in both undergraduate and master degrees. The method allows students to better understand some complex circuit-and physical-level phenomena, by describing them at a higher abstraction level. In addition to enhance their understanding of design problems and skills, students become more motivated and satisfied. As an application, two case studies are considered in this work: a radio-frequency front-end system and an analog-to-digital converter. In both cases, behavioral models of the different building blocks have been implemented in MATLAB/SIMULINK and used by the students enrolled in two courses named: Electronic Circuits for Communications and Wireless Transceivers: Standards, Techniques and Architectures.

Using behavioral modeling and simulation for learning communication circuits and systems
J.M. de la Rosa
Conference · IEEE Global Engineering Education Conference EDUCON 2012
abstract pdf

This paper analyzes the use of behavioral simulation techniques to enhance the teaching-learning process in electrical engineering courses, specifically those dealing with circuits for communication systems. The method-which can be applied to both undergraduate and master courses-allows students to better understand complex circuit-and device-level phenomena, by describing them at a higher abstraction level. As a demonstration vehicle of the presented methodology, two examples are considered in this work: an analog front-end of a direct-conversion digital radio receiver and a modulator. In both cases, behavioral models of the different subcircuits have been implemented in MATLAB/SIMULINK and used by the students enrolled in two different courses: an undergraduate course and a master course. The results presented in this paper reveal that students become highly motivated and satisfied with the course contents and the proposed simulation-based learning methodology. © 2012 IEEE

A teamwork-based education strategy for teaching lab of analog integrated circuits design
J.M. de la Rosa
Conference · IEEE Global Engineering Education Conference EDUCON 2012
abstract pdf

This paper describes the education activities carried out to motivate students enrolled in a laboratory course focused on the design of analog CMOS integrated circuits. Instead of using the traditional method based on doing practical exercises, a teamwork methodology was followed that consisted on a chip design project implemented by a group of students, each one playing a different role in the design team and being in charge of different tasks. A short training period at the beginning of the course was used for a preliminary assessment of students in order to assign their task and role in the design project. One of the students was selected as the project manager, while teachers acted as project reviewers. A set of control mechanisms, including internet-based video conferences and chats, was established. These tools allowed students to coordinate their activities and also were used by professors to check the work in progress during the course-apart from those review sessions taking place on-site in classroom. As a result of all these initiatives, students become more encouraged to do the practical exercises required to fulfill the course objectives and-at the same time-they developed and improved other complementary competencies, like the ability to work in a team and to defend their work by means of oral presentations. © 2012 IEEE

Using nanoHUB.org for teaching and learning nanoelectronic devices in materials engineering
J.M. de la Rosa
Conference · IEEE Global Engineering Education Conference EDUCON 2012
abstract pdf

This paper presents an educational methodology that uses the computational resources available in the nanoHUB.org online research and education platform. To this end, a number of software tools provided by nanoHUB.org have been incorporated as part of the practical lab exercises and linked to an e-learning virtual environment of a course on Electronic Materials, with emphasis on Nanoelectronic devices. The activities carried out during the course allowed students to enhance their understanding of those theoretical concepts dealing with Nanoelectronic materials and devices, thus becoming more motivated and satisfied. As an application and example, a set of experiences carried out by students is described. These experiences cover different Nanoelectronic materials and devices, going from physical and theoretical principles to device simulation. The proposed method has been applied to an undergraduate course, although it could be extended also to master students enrolled in courses dealing with materials science and engineering.

Efficient Hybrid Continuous-Time/Discrete-Time Sigma Delta Modulators for Broadband Wireless Telecom Systems
J.G. García-Sánchez and J.M. de la Rosa
Conference · Doctoral Conference on Computing, Electrical and Industrial Systems DOCEIS 2012
abstract

This work analyzes the use of hybrid continuous-time/discrete-time Sigma Delta modulators for the implementation of analog-to-digital converters intended for wideband mobile applications. Two alternative multirate cascade Sigma Delta architectures are discussed and analyzed, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. Both multirate Sigma Delta modulators are compared with conventional single-rate continuous-time cascade Sigma Delta modulators in terms of their sensitivity to non-ideal effects, considering different target specifications. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid Sigma Delta modulators, in which the continuous-time circuits operate at a higher rate than the discrete-time parts of the modulator.

Design and Measurements of a Preamplifier for Particles Tracking in Secondary Electrons Detectors
A. Garzón-Camacho, B. Fernández, M.A.G. Álvarez, J. Ceballos and J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2011
abstract

This paper presents a preamplifier design and experimental characterisation to be used in the Front-End Electronic (FEE) requiered for spatial resolution measurements in low-pressure gaseous Secondary Electrons Detectors (Se D). The circuit - implemented in a Printed Circuit Board (PCB) as a probe of concept - achieves a transimpedance of 80dB, a DC-gain of 18dB, a Signal-to-Noise Ratio (SNR) of 36dB and a chaping time of 140-170ns. These characteristics allow us to minimise the overlapping probability in tracking detection for Radioactive Ion Beams (RIB) with a counting rate higher than 10(6) particles per second.

Uso de nanohub.org para la enseñanza de dispositivos nanoelectrónicos
J.M. de la Rosa
Conference · International Symposium on Innovation and Technology ISIT 2011
abstract

This paper presents a simulation-based educational methodology that uses the computational resources available in the nanoHUB.org online platform. A number of software tools provided by nanoHUB.org have been incorporated as part of the teaching contents to the WebCT e-learning environment of a course on Electronic Materials, with emphasis on nanoelectronic devices. The activities carried out during the course allowed students to enhance their understanding of those theoretical concepts dealing with nanoelectronic materials and devices, thus becoming more motivated and satisfied.

High-level Design of an Hybrid CT/DT Cascade ΣΔ Modulator for Beyond-3G Applications
L.I. Guerrero-Linares, F. Sandoval Ibarra, J.M. de la Rosa and García-Sánchez
Conference · Iberchip XVII Workshop IWS 2011
abstract pdf

This paper presents a novel hybrid cascade CT/DT ΣΔ modulator suitable for the next generation of wireless communications. This novel ΣΔ modulator can achieve the adequate SNR level for Beyond-3G system communications by means of the combination of the advantage of CT and DT circuits and also to get an adequate topology for nanometer CMOS implementation. Simulation result (MATLAB/SIMULINK), achieves a SNR=76 dB with an Equivalent Number of Bits ENOB=12.3 for a signal

High-level Design of a Hybrid Cascade ΣΔ Modulator for UMTS/GSM/Bluetooth/WLAN Applications
L. Guerrero-Linares, F. Sandoval-Ibarra and J.M. de la Rosa
Conference · Workshop on Analog and Digital Electronic Design WADED 2011
abstract

This paper shows a block diagram-based adaptable continuous-time/discrete-time (CT/DT) ΣΔ modulator intended for Beyond-3G applications. The goal of such a hybrid proposal is taking advantage on the signal processing capabilities of both modulators-type as well as to build a novel topology suitable for manufacturing it in CMOS processes. High-level simulation results show an efficient Equivalent Number Of Bits (ENOB) for several communication standards (GSM, UMTS, Bluetooth, and WLAN). The requirements for GSM and UMTS are satisfied by the DT architecture, the CT architecture meets the requirements for Bluetooth, and WLAN requirements are satisfied by the whole hybrid architecture, which is based on a cascade design. Simulation results (MATLAB/SIMULINK) show a dynamic range of 104.7, 90.7, 96.9, and 84.9 dB for GSM, UMTS, Bluetooth, and WLAN with ENOB equivalent to 17.2, 14.8, 15.9, and 13.9 bits, respectively.

Efficient Analog CMOS Circuits for the Next Generation of Software-Defined-Radio Mobile Systems: Trends, Challenges and Solutions
J.M. de la Rosa
Conference · International Symposium on Innovation and Technology ISIT 2011
abstract

Abstract not available

Continuously-Tuned 1-V 90-nm CMOS LNAs for Multi-Standard Wireless Applications
E.C. Becerra-Alvarez, F. Sandoval-Ibarra and J.M. de la Rosa
Conference · Workshop on Analog and Digital Electronic Design WADED 2011
abstract

This paper discusses the use of continuously-tuned Low Noise Amplifiers (LNAs) for the implementation of multistandard radio receivers. Two LNA circuits are presented. One is based on a two-stage inductively degenerated common-source configuration and the other one is a folded cascode amplifier. Both LNAs employ MOS-varactor based tuning networks to make the operating frequency continuously programmable within the band of interest. Experimental measurements show a continuous tuning of Noise Figure (NF) and S-parameters within a 1.75-2.48GHz band, featuring NF<3.7dB, S21>19.6dB and IIP3> -9.8dBm. This design was implemented in a 1-V 90-nm CMOS technology.

Analysis of the Influence of the Biasing Circuit on the Performance of a Low Noise Amplifier with Feedback
J.M. Dores, E. Becerra-Alvarez, M.A. Martins, J.M. de la Rosa and J.R. Fernandes
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2011
abstract

In this paper we present a comparative study among different biasing circuits of a inductorless low-area Low Noise Amplifier (LNA) with feedback. With this study, we intend to determine the most suitable biasing circuit to achieve the best LNA performance. The LNAs under study are simulated in two different CMOS processes, 130 nm and 90 nm, to validate our conclusions in different technologies. The voltage supply in both cases is 1.2 V. The best LNA implemented in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltge gain (Av) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology implemented in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are imput impedance marched and have a noise figure below 2.4 dB measured at 2.4 GHz. The layout of noise figure below 2.4 dB measured at 2.4 GHz. The layout of the LNA siumlated in the 130 nm technology was designed achieving an area of 0.012 mm2, wiich is near the size of a pad or an inductor.

A comparative study of biasing circuits for an inductorless wideband Low Noise Amplifier
J.M. Dores, E. Becerra-Alvarez, M.A. Martins, J.M. de la Rosa and J.R. Fernandes
Conference · International Midwest Symposium on Circuits and Systems MWSCAS 2011
abstract pdf

In this paper we present a comparative study of different biasing versions of an inductorless low-area Low Noise Amplifier (LNA). With this study, we intend to determine the most suitable biasing circuit to achieve the best LNA performance. The LNAs under study are simulated in two different CMOS processes, 130 nm and 90 nm. The supply voltage is 1.2 V. The best LNA implemented in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (Av) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology implemented in 90 nm technology has a bandwidth of 11.2 GHz, voltage gain of 16.6 dB and consumes 1.9 mW. Both LNAs have input impedance matching and have a noise figure below 2.4 dB at 2.4 GHz.

High-Efficiency Cascade ΣΔ ADCs for Software-Defined-Radio Mobile Systems
A. Morgado, R. del Río and J.M. de la Rosa
Conference · International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design IWADC 2011
abstract pdf

This paper discusses a number of techniques to implement efficient cascade ΣΔ modulators intended for low-voltage, wideband, multi-mode applications. Several architectural strategies -such as loop-filter order reconfiguration and concurrency- are embedded in SMASH topologies with unity signal transfer function and resonation in order to improve the performance, while keeping high robustness against circuit errors. The proposed ΣΔ architectures -properly combined with circuit-level reconfiguration and biasing adaptation techniques- constitute a suited solution to implement analog-to-digital converters in future software-definedradio mobile terminals.

Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom
J.G. García-Sánchez and J.M. de la Rosa
Conference · IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2011
abstract

This paper presents the design of a hybrid continuous-time/discrete-time fourth-order cascade SIGMA DELTA modulator intended for wideband low-power wireless applications. The circuit is based on a new concept of multirate operation, in which the front-end stage - implemented using continuous-time (Gm-C) integrators - operates at a higher rate than the back-end (switched-capacitor) stage. This strategy benefits from the faster operation of continuous-time circuits while keeping power efficiency and high robustness against circuit element tolerances. Simulation results show that the modulator is able to operate with a maximum sampling rate of up to 1GHz, digitizing signals with a 44-to-92dB peak signal-to-(noise+distortion) ratio within a programmable 5-to-60MHz bandwidth.

Design considerations and experimental results of continuously-tuned reconfigurable CMOS LNAs
E.C. Becerra-Alvárez, J.M. de la Rosa and F. Sandoval-Ibarra
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2011
abstract

This paper analyses the use of continuously-tuned Low Noise Amplifiers (LNAs) for the implementation of the next generation of software-defined radio receivers. Two LNA circuits are discussed. One is based on a folded cascode stage and the other one consists on a two-stage inductively degenerated common-source configuration. Both LNAs - designed and implemented in a 1-V 90-nm CMOS technology - employ MOS-varactor based tuning networks to make the operating frequency continuously programmable within the band of interest, targeting the requirements of GSM, UMTS, Bluetooth and WLAN standards, as well as any other operation mode in between. Practical design issues are presented, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors and varactors; as well as technology parameter deviations. Experimental measurements demonstrate a correct operation of the circuits, showing a continuous tuning of Noise Figure (NF) and S-parameters within a 1.75-2.48GHz band, featuring NF<3.7dB, S(21) > 19.6dB and IIP3> -9.8dBm in a frequency range of 1.75-2.23GHz.

Systematic Design of ΣΔ Converters in Nano-Scale CMOS - A Practical Design Guide
J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
abstract

This tutorial presents a comprehensive and practical description of SDM operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to physical implementation, packaging and measurements, with emphasis on nanometer CMOS realization.

Trends and challenges in the design of SD modulators: state-of-the-art survey and application to software defined radio
J.M. de la Rosa
Conference · International Conference on Microelectronics ICM 2010
abstract

Abstract not avaliable

Design issues and experimental characterization of a continuously-tuned adaptive CMOS LNA
E.C. Becerra-Alvarez, J.M. de la Rosa and F. Sandoval-Ibarra
Conference · Iberchip XVI Workshop IWS 2010
abstract pdf

This paper presents the design implementation and experimental characterization of an adaptive Low Noise Amplifier (LNA) intended for multi-standard Radio Frequency (RF) wireless transceivers. The circuit -fabricated in a 90-nm CMOS technology- is a two-stage inductively degenerated common-source topology that combines PMOS varactors with programmable load to make the operation of the circuit continuously tunable. Practical design issues are analyzed, considering the effect of circuit parasitics associated to the chip package and integrated inductors, capacitors and varactors. Experimental measurements show a continuous tuning of NF and Sparameters within the 1.75-2.23GHz band, featuring NF<3.7dB, S21 >19.6dB and IIP3> -9.8dBm, with a power dissipation < 23mW from a 1-V supply voltage.

Continuously-tuned nanometer CMOS LNAs - design issues and experimental characterization
E.C. Becerra-Alvarez, J.M. de la Rosa and F. Sandoval-Ibarra
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
abstract

Abstract not avaliable

Flexible ΣΔ Modulators for Multi-Standard Wireless Transceivers: Novel Architectures and Circuit Solutions
A. Morgado, R. del Río and J.M. de la Rosa
Conference · Design, Automation and Test in Europe Conf. PhD Forum DATE 2010
abstract pdf

Abstract not available

A 100kHz-10MHz BW, 78-to-52dB DR,4.6-to-11mW flexible SC sigma-delta modulator in 1.2-V 90-nm CMOS
A. Morgado, R. del Río, J.M. de la Rosa, L. Bos, J. Ryckaert and Van Der Plas
Conference · European Solid State Circuits Conference ESSCIRC 2010
abstract pdf

This paper presents an adaptive 1.2-V 90-nm CMOS cascade two-stage (2-2) SC sigma delta modulator with 3-level quantization and unity signal transfer function in both stages. The chip reconfigures its loop filter order (either 2 nd or 4 th- order), clock frequency (from 40 to 240 MHz) and scales power according to the required specifications for different wireless standards, covering: GSM, Bluetooth, GPS, UMTS, DVB-H and WiMAX. Measurements feature a dynamic range of 78/70/71.5/66/62/52dB and a peak signal-to- (noise+distortion) ratio of 72.3/68.0/65.4/63.3/59.1/48.7dB within 100kHz/500kHz/1MHz/2MHz/4MHz/10MHz, while consuming 4.6/5.35/6.2/8/8/11mW, respectively. These results show a competitive performance with the state-of-the-art multi-standard sigma delta modulators, covering one of the widest regions in the DR-vs.-Bandwidth plane. ©2010 IEEE.

Adaptive SMASH ΣΔ converters for the next generation of mobile phones - Design issues and practical solutions
A. Morgado, R. del Río and J.M. de la Rosa
Conference · IEEE International New Circuits and Systems Conference NEWCAS 2010
abstract pdf

This paper discusses practical design issues associated to the implementation of sigma delta analog-to-digital converters intended for mobile telecom applications. After a comprehensive description of the proposed adaptive resonation-based Sturdy MASH sigma delta modulator, architectural and circuit-level timing limitations are analysed in detail, showing different design trade-offs. As a result of this analysis, a novel time-saving implementation of the dynamic element matching required in the multi-bit front-end digital-to-analog converter is presented. The circuit solutions found can be applied to SC reconfigurable implementations operating up to 320-MHz sampling frequencies. In order to demonstrate the capabilities of the considered modulator, a case study covering a number of standards, including GSM, Bluetooth, UMTS, DVB-H, WiMax and WLAN is shown. Time-domain behavioural simulations including main circuit-level errors validate the presented study. © 2010 IEEE.

Multirate hybrid CT/DT cascade sigma delta modulators with decreasing OSR of back-end DT stages
J.G. García-Sánchez and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
abstract pdf

This paper presents novel architectures of multirate hybrid cascade continuous-time/discrete-time Sigma Delta modulators that take advantage of the potentially faster operation of the continuous-time part of the circuit, while keep a reduced sampling operation of the back-end discrete-time stages. Compared to conventional multirate Sigma Delta modulators, the proposed architectures use a higher sampling rate in the front-end (continuous-time) stage of the modulator, whereas the back-end (discrete-time) stages operate at a lower rate. It is demonstrated that the intrinsic aliasing signal can be cancelled in the digital domain, with no additional analog hardware required. The resulting Sigma Delta topologies are potentially faster than conventional multirate Sigma Delta modulators, more power efficient than hybrid monorate architectures and more robust than cascade continuous-time implementations. The combination of these features results in a new class of Sigma Delta modulators, very suited for the implementation of analog-to-digital converters in the next generation of broadband wireless telecom systems.

Design of a 1-V 90-nm CMOS folded cascode LNA for multi-standard applications
E.C. Becerra-Alvárez, J.M. de la Rosa and F. Sandoval
Conference · IEEE International Midwest Symposium on Circuits and Systems MSCAS 2010
abstract pdf

This paper analyses the use of folded cascode Low Noise Amplifiers (LNAs) for the implementation of multi-standard wireless transceivers. The proposed LNA consists of a two-stage topology made up of a folded cascode and simple-stage amplifiers that use NMOS-varactor based tuning networks to make the operating frequency continuously programmable. The circuit has been designed and implemented in a 90-nm CMOS technology in order to cope with the requirements of GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b/g) standards. Practical design issues are analysed, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors and varactors; as well as technology parameter deviations. The circuit design is optimized using genetic algorithms to achieve the required specifications with adaptive power consumption. Layout-extracted simulation results demonstrate a correct operation of the proposed circuit, showing a continuous tuning of Noise Figure (NF) and S-parameters within the 1.85-2.48GHz band, featuring NF<3.8dB, S(21) > 12dB and IIP3> -12dBm, with an adaptive power dissipation between 13.3mW and 23.1mW from a 1-V supply voltage.

A Flexible Resonation-Based Cascade ΣΔ Modulator with Simplified Cancellation Logic
J.M. de la Rosa, A. Morgado, J.G. García and R. del Río
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2009
abstract pdf

This paper presents a new two-stage cascade ΣΔ modulator architecture that uses inter-stage resonation to increase its effective resolution as compared to conventional cascades and avoids the need for digital filtering in the error cancellation logic. The combination of these two strategies, together with the use of unity signal transfer function in all stages, make the presented modulator highly tolerant to noise leakages, very robust to non-linearities and mismatches of the loop-filter circuitry, and especially suited for low-voltage implementations at low oversampling ratios. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators, simplifies the switched-capacitor implementation of the resonation and makes the presented architecture very suited for reconfigurable multi-standard applications. As an illustration, a Beyond-3G case study is shown to demonstrate the benefits of the presented approach.

A New Reconfigurable Cascade ΣΔ Modulator Architecture with Inter-Stage Resonation and no Digital Cancellation Logic
A. Morgado, J.G. García, R. del Río and J.M. de la Rosa
Conference · Design of Circuits and Integrated Systems Conference DCIS 2009
abstract pdf

This paper presents a new two-stage cascade ΣΔ modulator architecture that uses inter-stage resonation to increase its effective resolution as compared to conventional cascades and avoids the need for digital filtering in the error cancellation logic. The combination of these two strategies, together with the use of unity signal transfer function in all stages, make the presented modulator highly tolerant to noise leakages, very robust to non-linearities and mismatches of the loop-filter circuitry, and especially suited for low-voltage implementations at low oversampling ratios. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators, simplifies the switched-capacitor implementation of the resonation and makes the presented architecture very suited for reconfigurable multi-standard applications. Besides, several practical details about the implementation of the modulator are given throughout the paper. As an illustration, a Beyond-3G case study is shown to demonstrate the benefits of the presented approach.

Resonation-based hybrid continuous-time/discrete-time cascade sigma delta modulators - application to 4G wireless telecom
J.M. de la Rosa, A. Morgado and R. del Río
Conference · VLSI Circuits and Systems Conference at 4th SPIE Microtechnologies for the New Millennium, 2009
abstract pdf

This paper presents innovative architectures of hybrid Continuous-Time/ Discrete-Time (CT/DT) cascade sigma delta Modulators sigma delta Ms) made up of a front-end CT stage and a back-end DT stage. In addition to increasing the digitized signal bandwidth as compared to conventional sigma delta Ms, the proposed topologies take advantage of the CT nature of the front-end sigma delta M stage, by embedding anti-aliasing filtering as well as their suitability to operate up to the GHz range. Moreover, the presented modulators include multi-bit quantization and Unity Signal Transfer Function (USTF) in both stages to reduce the integrator noutput swings, and programmable resonation to optimally distribute the zeroes of the overall Noise Transfer Function (NTF), such that the in-band quantization noise is minimized for each operation mode. Both local and inter-stage (global) based resonation architectures are synthesized and compared in terms of their circuit complexity, resolution-bandwidth programmability and robustness with respect to circuit non-ideal effects. The combination of all mentioned characteristics results in novel hybrid sigma delta Ms, very suited for the implementation of adaptive/reconfigurable Analog-to-Digital Converters (ADCs) intended for the 4th Generation (4G) of wireless telecom systems. © 2009 SPIE.

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices
E.C. Becerra-Alvarez, F. Sandoval-Ibarra and J.M. de la Rosa
Conference · SPIE Microtechnologies for the New Millennium 2009
abstract pdf

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S21>13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band. © 2009 SPIE.

Adaptive CMOS LNAs for beyond-3G RF receivers - A multi-standard GSM/WCDMA/BT/WLAN case study
E.C. Becerra-Alvarez, F. Sandoval-Ibarra and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2009
abstract pdf

This paper reviews the main circuit strategies reported so far for the implementation of multi-standard Low-Noise Amplifiers (LNAs) and presents a reconfigurable and adaptive LNA intended for Beyond-3G RF hand-held devices. The circuit, designed and implemented in a 90-nm CMOS technology, combines a reduced number of inductors with PMOS-varactors and programmable load to adapt its performance to different standard specifications with optimized power consumption. As a case study, the LNA has been designed to cope with the requirements of four standards: GSM, WCDMA, Bluetooth (BT) and WLAN (IEEE 802.11b-g). Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S-21>13.3dB and IIP3>10.9dBm over a 1.85-2.48GHz band, with an adaptive power consumption between 17.4mW and 21.7mW from a 1-V supply voltage.(dagger 1)

Hybrid continuous-time/discrete-time cascade sigma delta modulators with programmable resonation
J.M. de la Rosa, A. Morgado and R. del Río
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2009
abstract

This paper presents novel architectures of hybrid continuous-time/discrete-time cascade Sigma Delta modulators that combine the benefits of both circuit techniques with programmable noise transfer function resonation and unity signal transfer function in all stages. Both local and inter-stage based resonation topologies are synthesized and compared in terms of their circuit complexity, resolution-bandwidth programmability and robustness with respect to circuit implementation. As an application, a multi-standard case study is presented, targeting 5-14 bit programmable effective resolution within a tunable 100kHz-100MHz signal bandwidth.(dagger 1)

Reconfigurable Switched-Current Sigma-Delta Power Amplifier
R. Rodríguez-Calderón and J.M. de la Rosa
Conference · Iberchip XIV Workshop IWS 2008
abstract pdf

In this paper a reconfigurable switched-current sigma delta modulator for power amplifier is shown, which is a suitable topology to save energy and integrated area in portable applications. Results have shown the correct operation of a 1.8V, 0.18μm CMOS reconfigurable switched-current sigma delta modulator with 11bits dynamic range within 1MHz and 7.8bits within 3.8MHz bandwidth.

High-Performance Analog and Mixed-Signal Integrated Circuits: Our Experience at IMSE
J.M. de la Rosa-Utrera
Conference · Workshop on Electronics for Novel Nuclear Physics Detectors, 2008
abstract

Abstract not avaliable

A 90-nm CMOS Reconfigurable LNA for 4G Wireless Hand-Held Devices
E.C. Becerra-Alvarez, F. Sandoval-Ibarra and J.M. de la Rosa
Conference · Iberchip XIV Workshop IWS 2008
abstract pdf

An adaptive Low-Noise Amplifier (LNA) for the fourth generation (4G) of wireless telecom systems is presented.
The circuit, implemented in a 90nm standard RF CMOS technology, is a two-stage topology that combines inductive- source degeneration with MOS-varactor based tuning networks and programmable bias currents, in order to adapt its performance to different standard specifications with reduced number of inductors and minimum power dissipation. As an application, the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b-g). Simulation results, including technology parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<1.77dB, S21>16dB, S11, S22<-5.5dB and IIP3>-3.3dBm over the 1.85-2.48GHz band, with an adaptive power consumption between 25.3mW and 53.3mW.

A Novel Low-Voltage Reconfigurable ΣΔ Modulator for 4G Wireless Receivers
A. Morgado, R. del Río and J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2008
abstract pdf

This paper presents a new adaptable cascade ΣΔ modulator architecture for low-voltage multi-standard applications. It uses two reconfiguration strategies: a programmable global resonation and a variable loop-filter order. These techniques are properly combined in a novel topology that allows to increase the effective resolution in a given bandwidth, whereas keeping relaxed output swing requirements and high robustness to mismatch and to non-linearities of the amplifiers. Time-domain simulations including the main circuit-level non-idealities are shown to demonstrate the benefits of the presented modulator when it is configured to cope with the requirements of GSM, UMTS, WLAN and Wi-Max.

Two novel cascade ΣΔ modulators for broadband low-voltage A/D conversion
A. Morgado, R. del Río and J.M. de la Rosa
Conference · IEEE International Midwest Symposium on Circuits and Systems MWSCAS 2008
abstract pdf

This paper presents two new architectures of cascade Sigma Delta modulators that, based on the use of resonation, increase their effective resolutions compared to previously reported topologies while presenting high robustness to non-linearities of the amplifiers and very relaxed output swing requirements. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architectures very suited for highly-linear broadband A/D conversion(+1).

A low-voltage flexible cascade sigma delta modulator for beyond-3G wireless telecom
A. Morgado, R. del Río and J.M. de la Rosa
Conference · IEEE International Midwest Symposium on Circuits and Systems MWSCAS 2008
abstract pdf

This paper presents a new adaptable cascade EA modulator architecture for low-voltage multi-standard applications. It uses two reconfiguration strategies: a programmable global resonation scheme and a variable loop-filter order. These techniques are properly combined in a novel topology that allows to increase the effective resolution in a given bandwidth, whereas keeping relaxed output swing requirements and high robustness to mismatch and to non-linearities of the amplifiers. Time-domain simulations including main circuit-level effects are shown to demonstrate the benefits of the presented modulator when it is configured to cope with the requirements of GSNL UMTS, NVLAN and Wi-Max.(+1)

A triple-mode reconfigurable sigma-delta modulator for multi-standard wireless applications
A. Morgado, R. del Río and J.M. de la Rosa
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 08
abstract pdf

This paper presents the implementation and experimental characterization of a reconfigurable Sigma Delta modulator intended for multi-mode wireless receivers that is capable to perform the analog-to-digital conversion for GSM, Bluetooth, and UMTS standards. The Sigma Delta modulator reconfigures its cascade topology and building blocks in order to adapt the performance to the diverse standard specifications with optimized power consumption. The prototype has been implemented in a 130-nm CMOS technology and features dynamic ranges of 86.7/81.0/63.3dB and peak signal-to-(noise+distortion)ratios of 74.0/68.4/52.8dB at 400ksps/2Msps/8Msps, respectively The modulator power consumption is 25.2/25.0/44.5mW of which 11.0/10.5/ 24.8mW are dissipated in the analog circuitry.

Resonation-based Cascade ΣΔ Modulators for High-Linearity Broadband A/D Conversion
A. Morgado, R. del Río and J.M. de la Rosa
Conference · XXII Conf. on Design of Circuits and Integrated Systems DCIS 2007
abstract pdf

This paper presents two new architectures of cascade ΣΔ modulators that, based on the use of resonation, allow to increase the effective resolution compared to previously reported topologies whereas keeping relaxed output swing and high robustness to non-linearities of the amplifiers. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architectures very suited for the implementation of highly-linear broadband A/D conversion.

Adaptive CMOS circuits for 4G wireless networks
J.M. de la Rosa and M. Ismail
Conference · European Conference on Circuit Theory and Design ECCTD 2007
abstract pdf

The extraordinary growth of wireless communication technologies has prompted the emergence of a large number of new applications and standards. These new standards -like WMAN or UWB- are complementing the existing ones -such as GSM, UMTS or WLAN- and it is forecasted that the fourth generation (4G) of wireless terminals will make the convergence of services provided by cellular phones, satellite, long-range and short-range connectivity possible, giving rise to the so-called always-best-connected systems. The implementation of these systems in future handheld wireless devices will require low power low cost multi-standard multi-band chipsets, capable to operate over the different co-existing communication protocols, signal conditions, battery status, etc. The efficient implementation of these chipsets demands for reconfigurable building blocks that can adapt to the large number specifications with minimum power dissipation and at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop this new generation of RF transceivers, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. Fuelled by the technology evolution, the trend is to move the digitizing component as close as possible to the antenna, whereas the role of analog/RF circuits consists of implementing the necessary signal conditioning and data conversion interface. However, the integration in standard CMOS of increasingly complex analog/RF parts, with stringent demands on power consumption and cost as the two main differentiators, imposes a number of challenges and trade-offs that make their design a key issue to guarantee the quality of service of future beyond-3G (B3G) wireless devices. These challenges will be addressed in this tutorial through a comprehensive description of the state-of-the-art architectures, building-blocks, design trade-offs and practical considerations of reconfigurable CMOS RF/analog circuits for emerging B3G systems. The tutorial is divided into two lectures. The first presentation deals with radio design IPs whereas the second presentation focuses on data converters. These presentations will highlight both the trends and the opportunities for innovation in this area. A number of topics will be covered including: system-planning strategies, architecture- vs. circuit-level reconfiguration techniques, first-pass-silicon radio transceiver design in nanometer CMOS, robustness-vs.-reconfigurability trade-offs, low-voltage and low-power circuit techniques. Finally, examples from test chips will be presented.

Novel topologies of cascade sigma delta modulators for low-voltage wideband applications
A. Morgado, R. del Río and J.M. de la Rosa
Conference · European Conference on Circuit Theory and Design ECCTD 2007
abstract pdf

This work presents two novel topologies of cascade EA modulators with unity signal transfer function that avoid the need of digital filtering in the error cancellation logic. The combination of these two aspects make them highly tolerant to noise leakages, very robust to non-linearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioral simulations are presented that demonstrate the higher efficiency of the proposed topologies compared to existing cascades intended for wideband applications.(dagger 1).

An adaptive sigma delta modulator for multi-standard hand-held wireless devices
A. Morgado, R. del Río and J.M. de la Rosa
Conference · IEEE Asian Solid-State Circuits Conference A-SSCC 2007
abstract pdf

This paper describes the design and experimental characterization of a 130-nm CMOS cascade Sigma Delta modulator intended for multi-standard wireless telecom systems. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt its performance to different standard specifications with optimized power dissipation. Measurements show a correct operation for GSM/Bluetooth/WCDMA standards, featuring a dynamic range of 86.7/81.0/63.3dB and a peak signal-to-(noise+distortion) ratio of 74.0/68.4/52.8dB within 200kHz/1MHz/4MHz, respectively. The power consumption is 25.2/25.0/44.5mW, of which 11.0/10.5/24.8 are due to the analog part of the circui(dagger 1).

A 12-bit@40 MS/s Gm-C cascade 3-2 continuous-time sigma-delta modulator
R. Tortosa, A. Aceituno, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2007
abstract pdf

This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade Sigma Delta modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.(dagger 1).

Design of a 130 nm CMOS reconfigurable cascade sigma delta modulator for GSM/UMTS/Bluetooth
A. Morgado, R. del Río and J.M. de la Rosa
Conference · International Symposium on Circuits and Systems ISCAS 2007
abstract pdf

This paper reports a 130-nm CMOS programmable cascade Sigma Delta modulator for multistandard wireless terminals, covering three standards: GSM, Bluetooth and UNITS. The modulator is reconfigured at both architecture- and circuit-level in order to adapt its performance to the different standard specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

A SIMULINK block set for the high-level simulation of multistandard radio receivers
A. Morgado, R. del Río and J.M. de la Rosa
Conference · International Symposium on Circuits and Systems ISCAS 2007
abstract pdf

This paper describes a SIMULINK block set for the behavioral simulation of RF receivers. Building blocks are modeled including their main circuit-level non idealities. These models are incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, what makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As a case study, a direct-conversion receiver intended for 4G telecom systems is modeled and simulated using the proposed toolbox.

Towards systematic design of multi-standard converters
V.J. Rivas, R. Castro-López, A. Morgado, O. Guerra, E. Roca, R. del Río, J.M. de la Rosa and F.V. Fernández
Conference · Conference on VLSI Circuits and Systems III, 2007
abstract

In the last few years, we are witnessing the convergence of more and more communication capabilities into a single terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements: (1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels, with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design information. The systematic design methodology is illustrated via the design of a multi-standard YEA modulator meeting the specifications of three wireless communication standards.

Design of a 0.13 μm CMOS cascade expandable sigma delta modulator for multi-standard RF telecom systems
A. Morgado, R. del Río and J.M. de la Rosa
Conference · Conference on VLSI Circuits and Systems III, 2007
abstract

This paper reports a 130-nm CMOS programmable cascade Sigma Delta modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit-level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

A design tool for high-resolution high-frequency cascade continuous-time sigma delta modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V Fernández
Conference · Conference on VLSI Circuits and Systems III, 2007
abstract

This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time (CT) cascade EA modulators. The salient features of this methodology are: (a) flexible behavioral modeling for optimum accuracy efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; and (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Sigma Delta modulator in a 1.2V 130nm CMOS technology.

Behavioral modeling and simulation of multi-standard RF receivers using MATLAB/SIMULINK
A. Morgado, R. del Río and J.M. de la Rosa
Conference · Conference on VLSI Circuits and Systems III, 2007
abstract

This paper presents a SIMULINK block set for the behavioral modeling and high-level simulation of RF receiver front-ends. The toolbox includes a library with the main RF circuit models that are needed to implement wireless transceivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the following non-idealities: thermal noise characterized by the Noise Figure (NF) and the Signal-to-Noise Ratio (SNR) and nonlinearity expressed by the input-referred 2nd- and 3rd-order intercept points, IIP2 and IIP3, respectively. In addition to these general parameters, some block specific errors have been also included, like oscillator phase noise and mixer offset. These models have been incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, what makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As an application of the capabilities of the presented toolbox, a multi-standard Direct-Conversion Receiver (DCR) intended for 4G telecom systems is modeled and simulated considering the building-block requirements for the different standards.

A SIMULINK-based Approach for the Behavioral Modeling and Simulation of Multistandard RF Receivers
A. Morgado, R. del Río and J.M. de la Rosa
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2006
abstract

This paper presents a toolbox for the simulation of multistandard radio receivers using MATLAB/SIMULINK. Behavioral models of building blocks, including their main circuit errors, are described and incorporated into SIMULINK by combining library blocks with C-coded S-functions in order to reduce the simulation time while keeping high accuracy and interoperability of different circuit models. As a case study, the complete model of a direct-conversion receiver intended for GSM/UMTS/Bluetooth/WLAN is presented. Simulation results are shown for the different standards in order to illustrate the capabilities of the proposed tool.

Design of a 0.18 μm low-voltage switched-current SA modulator for multistandard communication systems
R. Rodríguez-Calderón, E. Becerra-Álvarez, F. Sandoval-Ibarra and J.M. de la Rosa
Conference · Midwest Symposium on Circuits and Systems MWSCAS 2006
abstract pdf

This paper presents a 1.5-V, 0.18um CMOS reconfigurable switched-current SA modulator for multistandard (GSM, Bluetooth, WCDMA) telecom systems. The modulator topology is an expandable cascade architecture which can be reconfigured both at the architecture level and at the circuit level in order to adapt the modulator performance to the different standards with adjustable power consumption. For this purpose, programmable Class AB memory-cell arrays are used to implement the modulator loop filter. Transistorlevel simulations are shown that demonstrate correct operation for all standards, featuring 12-bit, 11-bit and 7.8-bit dynamic range within 200-kHz, 1-MHz and 3.8-MHz bandwidth, respectively. © 2006 IEEE.

Design of a 1.2-V 130 nm CMOS 13-bit@40 MS/s cascade 2-2-1 continuous-time sigma delta modulator
R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Conference · IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2006
abstract pdf

This paper presents the design of a continuous-time multibit cascade 2-2-1 Sigma Delta modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.

A 12-bit CMOS current steering D/A converter for embedded systems
J. Ruiz-Amaya, M. Delgado-Restituto, J.F. Fernández-Bootello, D. Brandano, R. Castro-López and J.M. de la Rosa
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2006
abstract pdf

This paper describes the design of a 12-bit digital-to-analog converter for a wireline modem chip implemented in a 0.13 mu m digital CMOS technology. Transistor-level simulations from extracted layout at the nominal modem data rate of 80MS/s show an Spurious-Free Dynamic-Range (SFDR) better than 62dB at Nyquist rate under industrial operation conditions (40 to 85 degrees temperature range and +/- 10% supply variations) and for all technology process corners. Additionally, the converter achieves a Multi-Tone Power Ratio (MTPR) higher than 59dB for different Discrete MultiTone (DMT) test patterns consisting of 1536 carriers that fall in the Nyquist band. Simulation results at a higher data rate of 200MS/s are also shown in the paper. The converter dissipates less than 150mW from a mixed 3.3/1.2V supply and occupies less than 1.7mm(2).

Design of a 1.2-V cascade continuous-time Sigma triangle modulator for broadband telecommunications
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · International Symposium on Circuits and Systems ISCAS 2006
abstract pdf

This paper presents the design of a continuous-time multibit cascade 2-2-1 Sigma Delta modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 0.13 mu m CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.

Reconfiguration of cascade sigma delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2006
abstract pdf

This paper presents design considerations for cascade Sigma-Delta Modulators (Sigma Delta Ms) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1(L-2) expandible Sigma Delta M is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach.

Design and Electrical Implementation of a 1.8-V Multistandard Switched-Current ΣΔ Modulator
R. Rodríguez-Calderón, J.M. de la Rosa and F. Sandoval-Ibarra
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
abstract pdf

This paper describes the design and electrical implementation of a 1.8-V, 0.18μm CMOS reconfigurable switched-current ΣΔ modulator for multistandard (Bluetooth, WCDMA) communication systems. The modulator topology is an expandible cascade architecture which can be reconfigured both at the architecture level and at the circuit level in order to adapt the modulator performance to the different standards with adjustable power consumption. For this purpose, programmable Class AB memory-cell arrays are used to implement the modulator loop filter. Simulation results are shown that demonstrate correct operation for all standards, featuring 11bits dynamic range within 1MHz and 7.8bits within 3.8MHz bandwidth.

Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
abstract pdf

This paper analyses the effect of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Derived expressions show that the jitter-induced noise power can be separated into two main components: one that depends on the modulator loop filter transfer function and the other one due to the input signal parameters, i.e amplitude and frequency. The latter component, not considered in previous approaches, allows us to accurately predict the resolution loss caused by jitter, showing effects not taken into account up to now in literature which are specially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Time-domain simulations of several modulator topologies intended for VDSL application are given to validate the presented analysis.

Frontiers of CMOS Sigma-Delta Converters - Part2: Continuout-Time Sigma-Delta Converters
A. Rodríguez-Vázquez and J.M. de la Rosa
Conference · European Conference on Circuit Theory and Design ECCTD 2005
abstract pdf

Sigma-delta converters are very well suited for the implementation of analog front-ends in CMOS SoCs. Owing to different advances on both architectures and circuit techniques, these converters are today employed for applications spanning a very wide frequency interval, from instrumentation to telecom. They are clearly dominant in measurement, voice, and audio systems, and coexist with algorithmic, subranging, and pipeline converters in systems for mobile communications and broadband wireline applications like ADSL. Furthermore, it is commonly accepted that whenever an industrial application can be addressed by using a sigma-delta converter, this solution is considered very well suited, for feasibility, yield, robustness, and time-to-market reasons. During the last few years, significant efforts and contributions have been made to decrease the power budget of sigma-delta converters, to increase their bandwidth and to make them fully compatible with last generation, low-voltage sub-micron technologies. The extended usage of multi-bit quantizers, the emergence of new continuous-time architectures and synthesis techniques, the combination of continuous-time and discrete-time filters, the usage of calibration, the compatibility with very low voltage supplies,... are examples of recent advances on CMOS sigma-delta converter design. Based on a comprehensive description of sigma-delta operating principles, this tutorial presents an overview of the advances which are currently shaping the field of CMOS sigma-delta converter design. Topics covered in the tutorial include the following: New architectures and optimization techniques for wideband discrete-time sigma-delta modulators. New synthesis techniques and architectures for continuous-time sigma-delta modulators. Continuous-time, discrete-time hybrid architectures. New sigma-delta and hybrid converter architecture: parallel, time-interleaved, sigma-delta pipeline,... Calibration techniques. Strategies for multi-mode and multi-standard transceivers. Low-voltage, low-power design. Deep-submicron design.

Design Considerations for Multistandard Cascade ΣΔ Modulators
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
abstract pdf

This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.

A 0.13μm CMOS Current Steering D/A Converter for PLC and VDSL Applications
J. Ruiz-Amaya, J.F. Fernández-Bootello, J.M. de la Rosa, M. Delgado-Restituto and R. del Río
Conference · XX Conference on Design of Circuits and Integrated Systems DCIS 2005
abstract pdf

This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The converter is segmented in an unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distributed in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Transistor-level simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher than 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 active area.

An approach to the design of the design of multistandard ΣΔ modulators
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · WSEAS Int. Conf. on Electronics, Control and Signal Processing ICECS 2005
abstract

This paper discusses issues concerning the design of cascade sigma-delta modulators intended for multistandard wireless receivers. Four standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator topology in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture-and circuit-level in order to adapt the modulator performance to the standards requirements with adaptive power consumption. Time-domain behavioural simulations are shown to validate the presented approach.

A CMOS High-Resolution Automotive Sensor A/D Interface Based on a 110-dB @ 40kS/s Programmable-Gain Cascade 2-1 Sigma-Delta Modulator with Embedded Design-for-Testability Strategies
J.M. de la Rosa, S. Escalera, O. Guerra, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference · Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
abstract

Abstract not available

A 12-bit 80 MS/s A/D/A Interface for Power-Line Applications in 0.13μm Digital CMOS Technology
J. Ruiz-Amaya, J.F. Fernández-Bootello, J.M. de la Rosa, R. del Río and M. Delgado-Restituto
Conference · 5th Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
abstract

Abstract not available

Continuous-time cascaded delta sigma modulators for VDSL: A comparative study
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract

This paper describes new cascaded continuous-time Sigma Delta modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely: transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.

A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 sigma delta modulator with programmable gain and programmable chopper stabilization
O. Guerra, S. Escalera, J.M. de la Rosa, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract

This paper describes a 0.35 μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/ 2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40 degrees C, 175 degrees C).The modulator architecture has been selected after an exhaustive comparison among multiple Sigma Delta M topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy.The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.

Simulation-based high-level synthesis of nyquist-rate data converters using MATLAB/SIMULINK
J. Ruiz-Amaya, J.M. de la Rosa, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB (R). The embedded simulator uses SIMULINK (R) C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK (R) elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK (R) platform by using the MATLAB (R) engine library, so that the optimization core runs in background while MATLAB (R) acts as a computation engine. The implementation on the MATLAB (R) platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13 mu m CMOS 12-bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.

Embedded desing-for-testability strategies to test high-resolution SD modulators
S. Escalera, A. Espin, O. Guerra, J.M. de la Rosa, F. Medeiro and B. Pérez-Verdú
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract

This paper describes the design-for-testability strategies integrated in a 0.35 mu m CMOS 17-bit@40-kS/s chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces.After a brief review on the most important effects degrading the circuit performance, a test technique, based on the division of the circuit into several blocks that are tested separately, is presented.Experimental results shows the utility of the implemented test technique to detect errors in the circuit and to characterize the most important blocks with a minimum increase of extra area for the additional test circuitry.

Design of a 12-bit 80 MS/s pipeline analog-to-digital converter for PLC-VDSL applications
J. Ruiz-Amaya, M. Delgado-Restituto, J.F. Fernández-Bootello and J.M. de la Rosa
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract

This paper describes the design of a 12-bit 80MS/s pipeline Analog-to-Digital converter implemented in 0.13 mu m CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation, synthesis and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool.The converter is based on a 10-stage pipeline preceded by a sample/hold with bootstrapping technique. Each stage gives 1.5 effective bits, except for the first one which provides 2.5 effective bits to improve linearity. The Analog-to-Digital architecture uses redundant bits for digital correction, it is planned to be implemented without using calibration and employs a subranging pipeline look-ahead technique to increase speed. Substrate biased MOSFETs in the depletion region are used as capacitors, linearized by a series compensation.Simulation results show that the Multi-Tone Power Ratio is higher than 56dB for several DMT test signals and the estimated Signal-to-Noise Ratio yield is supposed to be better than 62 dB from DC to Nyquist frequency. The converter dissipates less than 150mW from a 3.3V supply and occupies less than 4 mm(2) die area. The results have been checked with all process corners from -40 degrees to 85 degrees and power supply from 3V to 3.6V.

A direct synthesis method of cascaded continuous-time sigma-delta modulators
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
abstract pdf

This paper presents an efficient method to synthesize cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. In addition to place the zeroes of the loop filter in an optimum way, the proposed methodology leads to more efficient architectures in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealifies.(dagger 1)

Analysis of clock jitter error in multibit continuous-time sigma delta modulators with NRZ feedback waveform
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
abstract pdf

This paper presents a detailed study of the clock jitter error in multibit continuous-time Sigma Delta modulators with non-return-to-zero feedback waveform. Closed-form expressions are derived for the in-band error power and the signal-to-noise ratio showing that the jitter-induced noise can be separated into two main components: one depending on the modulator loop filter and the other one due to the input signal. The latter, not considered in previous approaches, allows us to accurately predict the signal-to-noise ratio degradation and to optimize the modulator performance in terms of jitter insensitivity. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascaded or single-loop architectures. Time-domain simulations of several modulators are shown to validate the presented approach.(dagger 1)

An embedded 12-bit 80 MS/s A/D/A interface for power-line communications in 0.13 um pure digital CMOS technology
M. Delgado-Restituto, J. Ruiz-Amaya, J.M. de la Rosa, J.F. Fernández-Bootello, L. Díez, R. del Río and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
abstract pdf

This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13 mu m pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band powerline communications. The A/D converter uses a pipelined structure, whereas the D/A stage is based on segmented current steering techniques. In both cases, specifications are 12-b resolution at 80MS/s and MTPR above 56dB.

Behavioral modeling simulation and high-level synthesis of pipeline A/D converters
J. Ruiz-Amaya, J.M. de la Rosa, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
abstract pdf

This paper presents a MATLAB (R) toolbox for the time-domain simulation and high-level sizing of pipeline analog-to-digital converters. SIMULINK (R) C-coded S-functions are used to describe the behavioral models of all building blocks, including their main circuit errors. This approach significantly speeds up system-level simulations while keeping high accuracy - verified with HSPICE - and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable CAD tool for the high-level design of broadband communication analog front-ends. As a case study, an embedded 0.13 mu m CMOS 12bit@80MS/s A/D interface for a PLC chipset is designed to show the capabilities of the presented tool.(dagger 1)

Architectures and design considerations for wireline sigma delta modulators beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Workshop on ADC Modelling and Testing IWADC 2005
abstract

In this paper we discuss design considerations for sigma-delta modulators (&USigma;&UDelta; Ms) aimed at high-linearity highspeed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range of 12-15 bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade architectures in a low-voltage deep-submicron scenaRío. We show that, after proper architecture selection, guided by a simple power estimation method, these &USigma;&UDelta; Ms are good candidates to achieve ADSL performances in coming CMOS processes. Experimental results on a prototype for ADSL+ applications designed in 2.5-V 0.25-μ m CMOS suggest the possibility of programming or reusing the design for other telecom applications, thanks to the easiness to expand or shrink this family of cascade &USigma;&UDelta; Ms to other orders. Estimated performance of the adapted prototype for ISDN, SDSL, and VDSL applications provides promising results. © 2005 Elsevier Ltd. All rights reserved.

A New Method for the High-Level Synthesis of Continuous-Time Cascaded ΣΔ Modulators
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2004
abstract pdf

This paper presents an efficient method to design cascaded ΣΔ modulators implemented with continuous-time circuits. Instead of using a discrete-to-continuous time transformation, the proposed methodology is based on the direct synthesis of the whole cascaded architecture. This leads to more efficient topologies in terms of circuit complexity, power consumption and robustness with respect to parasitics. As an application, new cascaded topologies are synthesized and optimized to cope with VDSL specifications.

Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters
J. Ruiz Amaya, J.M. de la Rosa and M. Delgado-Restituto
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2004
abstract pdf

This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of pipeline analog-to-digital converters in MATLAB. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK as C-compiled S-functions. This approach significantly speeds up system-level simulations while keeping high accuracy -verified with HSPICE- and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s ADC for a PLC chipset is designed to show the capabilities of the presented tool.

MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time sigma delta modulators
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, E. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
abstract pdf

This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of SigmaDelta Modulators (SigmaDeltaMs). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for SigmaDeltaM synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.

A 0.35 μm CMOS 17-bit@40 kS/s sensor A/D interface based on a programmable-gain cascade 2-1 sigma delta modulator
J.M. García-González, S. Escalera, J.M. de la Rosa, O. Guerra, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
abstract pdf

This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35mum standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) SigmaDelta modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage opamps, has a fixed gain of 10 and it is capable of handling signals with 20kHz-bandwidth and amplitudes ranging from muVs to hundreds of mVs with a signal-to-(noise+distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulation results show 17-bit@40kS/s for all cases of the modulator gain.

An alternative DFT methodology to test high-resolution sigma delta modulators
S. Escalera, J.M. García-González, O. Guerra, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2004
abstract pdf

In this paper, a novel DfT methodology to test high-resolution SigmaDelta Modulators (SigmaDeltaM) is introduced. The aim of the proposal is to reduce the test time required by conventional methodologies without degrading the accuracy of the results. A detailed description of the additional circuitry needed to perform these tests is presented as well as some initial simulation results to show the utility of the approach.

An optimization-based tool for the high-level synthesis of discrete-time and continuous-time sigma delta modulators in the MATLAB/SIMULINK environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, F.V. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
abstract pdf

This paper presents a MATLAB toolbox for the automated high-level sizing of SigmaDelta Modulators (SigmaDeltaMs) based on the combination of an accurate time-domain behavioural simulator and a statistical optimizer. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.)

SIMSIDES Toolbox: An Interactive Tool for the Behavioural Simulation of Discrete- and Continuous-time ΣΔ Modulators in the MATLAB/SIMULINK Environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, R. del Río, B. Moreno-Reina, B. Pérez-Verdú, R. Tortosa, R. Romay and A. Rodríguez-Vázquez
Conference · Design of Circuits and Integrated Systems Conf. DCIS 2003
abstract

This paper presents an user-friendly tool, named SIMSIDES, for the time-domain simulation of ΣΔ modulators in the MATLAB/SIMULINK environment. The tool is able to simulate an arbitrary ΣΔ topology implemented by using discrete-time - switched-capacitor and switched-current - and continuous-time circuit techniques, considering the most important circuit parasitics. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions. The combination of high accuracy, short CPU-time and interoperability of different circuit models, make the tool into a valuable instrument to optimize the design of ΣΔ analog-to-digital converters.

Design and Implementation of a 0.35μm CMOS Programmable-Gain 2-1 Cascade ΣΔ Modulator for Automotive Sensors
J.M. García-González, S. Escalera, J.M. de la Rosa, F. Medeiro, R. del Río, O. Guerra, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2003
abstract

Abstract not available

Description Languages and Tools for Behavioural Simulation of ΣΔ Modulators: a Comparative Survey
R. Castro-López, J. Ruiz-Amaya, J.M. de la Rosa, R. Romay, R. del Río, F. Medeiro, F.V. Fernández, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Forum on Specification & Design Languages FDL 2003
abstract

Abstract not available

Design Considerations for ΣΔ Modulators Beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Workshop IBERCHIP 2003
abstract

In this paper we discuss design considerations for Sigma-Delta modulators (ΣΔM) aimed at high-linearity, high-speed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range 12-15bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade multi-bit architec-tures in a low-voltage, deep-submicron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are still promising candidates to achieve post-ADSL performances in coming CMOS processes.

A 2.5-V CMOS wideband sigma-delta modulator
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE Instrumentation and Measurement Technology Conference I2MTC 2003
abstract pdf

A high-performance SigmaDelta modulator for wireline communication applications is presented It employs a 4th-order cascade multi-bit architecture that requires only 16 oversampling ratio, and has been implemented using fully-differential SC circuits in a 0.25-mum CMOS technology. Measurements show a dynamic range of 84dB operating at Z2MS/s output rate, and 79dB at 4.4MS/s. The whole prototype dissipates 65.8mW from a 2.5-V supply.

Expandible high-order cascade Sigma Delta modulator with constant, reduced systematic loss of resolution
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Instrumentation and Measurement Technology Conference I2MTC 2003
abstract

An arbitrary order sigma-delta modulator cascade architecture is presented with only 1-bit loss of resolution due to scaling issues, even with single-bit quantization. This loss is kept with a high overloading point, regardless of the order. Simulations reveal that circuit imperfections can be tolerated up to 6th order, so that 90-dB SNDR can be obtained with x16 oversampling, without multi-bit quantization.

Design considerations for an automotive sensor interface sigma delta modulator
F. Medeiro, J.M. de la Rosa, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
abstract pdf

In this paper we discuss design considerations for a Sigma-Delta modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. This SigmaDeltaM contains a programmable-gain input interface to accommodate the output signal level of a variety of automotive sensors. We show that this characteristic can be efficiently implemented by proper architecture selection and ad hoc sampling and integration capacitor structures. Behavioral simulations of a 17bit 40kS/s modulators are included to illustrate the design considerations.

A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switched-current and continuous-time sigma delta modulators
J. Moreno-Reina, J.M. de la Rosa, F. Medeiro, R. Romay, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
abstract pdf

This paper describes how to extend the capabilities of SIMULINK for the time-domain simulation of SigmaDelta modulators implemented by using switched-capacitor, switched-current and continuous-time Circuits, considering the most important error mechanisms. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions-The outcome is a complete SIMULINK block library that allows interactive, fast and accurate simulation of an arbitrary SigmaDelta topology.

A sigma delta modulator for a programmable-gain, low-power, high-linearity automotive sensor interface
J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems 2003
abstract

This paper describes the design and electrical implementation of a 0.351mum CMOS 17-bit@40kS/s Sigma-Delta Modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. First of all, the paper discusses the most important limiting factors and design considerations applicable to a high-resolution SigmaDeltaM for sensor interfaces. After an exhaustive comparison among multiple SigmaDeltaM architectures in terms of resolution, speed and power dissipation, a third-order (2-1) cascade SigmaDeltaM is chosen. For a better fitting to the characteristics of different sensor outputs, the SigmaDeltaM here includes a programmable set of gains (0.5, 1, 2, and 4). The gain programmability is implemented by a reconfigurable capacitor array of unitary capacitors. In order to relax the amplifier dynamics requirements for the different modulator gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. Behavioural simulations considering transistor-level circuit parasitics shows a Dynamic Range (DR.) over 105dB for all cases of the modulator gain.

A 79-dB 4.4MS/s ΣΔ Modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2002
abstract

Abstract not available

Design of a broadband ΣΔ modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2002
abstract

Abstract not available

A 2.5-V sigma delta modulator in 0.25μm CMOS for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
abstract pdf

This paper presents a dual-quantization cascade SC SigmaDelta modulator intended for A/D conversion in ADSL applications. The modulator combines a low oversampling ratio with 3-bit resolution in the last stage, to achieve 14bit@4.4MS/s (16x) and 15bit@2.2MS/s (32x) with no need of correction/calibration mechanisms. It consumes 66mW from a single 2.5-V supply and has been implemented in 0.25-mum CMOS technology.

Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Workshop on Advances in Analog Circuit Design AACD 2002
abstract

This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-mum CMOS technology are given and illustrated through experimental results.

Books

Sigma-Delta Converters: Practical Design Guide, 2nd Edition
J.M. de la Rosa
Book · 568 p, 2018
abstract link

Sigma-Delta Modulators (SDMs) have become one of the best choices for the implementation of analog/digital interfaces of electronic systems integrated in CMOS technologies. Compared to other kinds of Analog-to-Digital Converters (ADCs), ΣΔMs cover one of the widest conversion regions of the resolution-versus-bandwidth plane, being the most efficient solution to digitize signals in an increasingly number of applications, which span from high-resolution low-bandwidth digital audio, sensor interfaces, and instrumentation, to ultra-low power biomedical systems and medium-resolution broadband wireless communications.
Following the spirit of its first edition, Sigma-Delta Converters: Practical Design Guide, 2nd Edition takes a comprehensive look at SDMs, their diverse types of architectures, circuit techniques, analysis synthesis methods, and CAD tools, as well as their practical design considerations. It compiles and updates the current research reported on the topic, and explains the multiple trade-offs involved in the whole design flow of Sigma-Delta Modulators -from specifications to chip implementation and characterization. The book follows a top-down approach in order to provide readers with the necessary understanding about recent advances, trends, and challenges in state-of-the-art ΣΔMs. It makes more emphasis on two key points, which were not treated so deeply in the first edition:
- It includes a more detailed explanation of ΣΔMs implemented using Continuous-Time (CT) circuits, going from system-level synthesis to practical circuit limitations.
- It provides more practical case studies and applications, as well as a deeper description of the synthesis methodologies and CAD tools employed in the design of ΣΔ converters.
Sigma-Delta Converters: Practical Design Guide, 2nd Edition serves as an excellent textbook for undergraduate and graduate students in electrical engineering as well as design engineers working on SD data-converters, who are looking for a uniform and self-contained reference in this hot topic. With this goal in mind, and based on the feedback received from readers, the contents have been revised and structured to make this new edition a unique monograph written in a didactical, pedagogical, and intuitive style.

CMOS Sigma-Delta Converters: Practical Design Guide
J.M. de la Rosa and R. del Río
Book · 426 p, 2013
abstract link

This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations -going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues -from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence Design FrameWork II. As well as being a comprehensive reference to the theory, the book is also unique in that it gives special importance on practical issues, giving a detailed description of the different steps that constitute the whole design flow of sigma-delta ADCs.

Nanometer CMOS Sigma-Delta Modulators for Software Defined Radios
A. Morgado, R. del Río and J.M. de la Rosa
Book · 288 p, 2011
abstract link

This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes. This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview of the state-of-the-art performance, challenges and practical solutions, providing the necessary insight to implement successful design, through an efficient design and synthesis methodology. Readers will learn a number of practical skills from system-level design to experimental measurements and testing.

CMOS cascade sigma-delta modulators for sensors and telecom. Error analysis and practical design
R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa and A. Rodríguez-Vázquez
Book · ACSP, 299 p, 2006
abstract link pdf

CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. Main focus is on cascade architectures, although considerations pertaining to circuits and error analysis are general and hence valid for other architectures. The book differs from others in the complete, in-depth coverage of SC circuit errors, in the detailed elaboration and description of practical design plan, and in the thorough presentation of considerations leading to practical high-performance designs. Another differentiating feature of this book is the coverage into a unified description of largely different application areas. On the one hand, sensor front-ends, where the limiting factor is thermal noise. On the other, wire-line telecom front-ends, where the limiting factor is linked to the dynamic behavior of the building blocks. The book starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. This presentation is both complete and comprehensive. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allow the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors. CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators. In this sense, the book is intended for a large audience: from mixed-signal designers who want to optimize and to shorten the design cycle of sigma-delta modulators with challenging specifications, to non-experienced readers who want a comprehensive and practical description of sigma-delta design and SC errors.

Systematic design of CMOS switched-current bandpass sigma-delta modulators for digital communication chips
J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez (Eds.)
Book · 499 p, 2002
abstract link pdf

Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips gives a systematic methodology for designing Sigma-Delta Modulators (Sigma-Delta Ms), specially those of the bandpass type, realized in digital CMOS technologies by using switched-current (SI) circuits. For this purpose, an analysis of SI error mechanisms as well as their influence on the performance of Sigma-Delta Ms is presented in a detailed and comprehensive style. On the one hand, the depth of such an analysis allows designers to get practical knowledge of the performance degradation of SI Sigma-Delta Ms through closed-form expressions that relate the modulator specifications to SI cell design parameters. On the other hand, the behavioural models derived from that study make it possible a fast and precise time-domain simulation of SI Sigma-Delta Ms, shown in the book through a simulator developed in MATLAB/SIMULINK. The architectures and circuit design methodologies presented in this book are demonstrated through two standard CMOS IC prototypes - the first silicon realizations of SI bandpass Sigma-Delta Ms - intended for AM digital radio receivers. The good performance comparison obtained with current state-of-the-art of switched-capacitor ICs demonstrates the viability of SI circuits for the realization of digital communication chips. Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips is organized such that it can be useful for a large audience: from novices in the field to experienced Sigma-Delta M designers. The comprehensive treatment of SI Sigma-Delta Ms given in this book will allow all of them to improve their productivity through the incorporation of circuit knowledge and CAD tools to optimize the design and to shorten the design cycle.

Book Chapters

Flexible Nanometer CMOS Low-Noise Amplifiers for the Next Generation Software-Defined-Radio Mobile Systems
E.C. Becerra-Alvarez, F. Sandoval-Ibarra and J.M. de la Rosa
Book Chapter · Integrated circuits for analog signal processing, pp 145-169, 2013
abstract doi pdf

This chapter reviews the main circuit strategies reported so far for the implementation of reconfigurable and adaptive CMOS Low-Noise Amplifiers (LNAs) intended for multi-standard wireless telecom systems. Different performance metrics are analyzed and compared, and a number of practical design considerations are given in order to optimize the performance of these kinds of LNAs in terms of Noise Figure (NF) and S-parameter programmability, with scalable power consumption. To this purpose, a circuit design methodology is presented which combines a mathematical model with electrical simulations. As an application of the proposed design methodology, a LNA Integrated Circuit (IC) implemented in a 1-V 90-nm CMOS technology is presented. The circuit consists of a two-stage inductively degenerated common-source configuration and uses MOS-varactor based tunning networks to make the resonant frequency continuously programmable within the band of interest. This allows the LNA to target the requirements of a number of commercial licensed standards, as well as any other operation modes in between. Practical implementation issues are discussed, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors, varactors, as well as technology parameter deviations. Experimental results are presented to demonstrate the correct operation of the IC, showing a continuous tuning of NF and S-parameters within a 1.75-2.48 GHz band, and featuring {NF} < 3.7 {dB}, S21 > 19.6 {dB} and {IIP3} > - 9.8 {dBm} in a frequency range of 1.75-2.23 GHz.

High-order cascade multi-bit ΣΔ modulators
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 307-343, 2003
abstract doi pdf

Motivated by the commercial success of the wireline communication products, mixed-signal designers are being pushed to integrate A/D and D/A interfaces featuring 12- to 16-bit effective resolution for signal bandwidths well in excess of 1MHz. These specifications must be achieved in a low-voltage scenario, making use of poor performance (and often badly characterized) devices, which decreases the 'analog speed' of deep-submicron CMOS processes.

Sigma-delta CMOS ADCs: An overview of the state-of-the-art
A. Rodríguez-Vázquez, F. Medeiro, J.M. de la Rosa, R. del Río, R. Tortosa and B. Pérez-Verdú
Book Chapter · CMOS Telecom Data Converters, pp 37-91, 2003
abstract doi

As stated in Chapter 1, analog-to-digital conversion involves a number of tasks, namely:
- Sampling the input signal at frequency f s, with prior anti-aliasing filtering and, in some cases, holding the sampled values.
- Quantizing the input sample values with N bits; i.e., mapping each continuous-valued input sample onto the closest discrete-valued level out of the (2ˆN - 1) discrete levels covering the input signal variation interval.
- Encoding the result in a digital representation.

CMOS comparators
R. Domínguez-Castro, M. Delgado-Restituto, A. Rodríguez-Vázquez, J.M. de la Rosa and F. Medeiro
Book Chapter · CMOS Telecom Data Converters, pp 149-182, 2003
abstract doi

abstract not available

Bandpass sigma-delta A/D converters: Fundamentals, architectures and circuits
J.M. de la Rosa, B. Pérez-Verdú, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 523-559, 2003
abstract doi pdf

The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow bandwidth. Thus, BPΣΔMs have much in common with their lowpass counterparts - whose properties have been covered in previous Chapters of this book. However, there are some issues which are peculiar to BPΣΔ-ADCs. This Chapter is devoted to the description of these issues. In Section 11.2, digital radio receivers are revised, pointing out the necessity for an ADC at the IF location. Section 11.3 and Section 11.4 explain the basic concepts and architectural issues of BPΣΔ-ADCs. The problems derived from circuit implementation are treated in Section 11.5. Finally, Section 11.6 summarizes the performance of state-of-the-art BPΣΔ-ADCs

Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter · Analog Circuit Design: Structured Mixed-Mode Design, Multi-Bit Sigma-Delta Converters, Short Range RF Circuits, pp 235-260, 2002
abstract doi

This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-um CMOS technology are given and illustrated through experimental results.

Trade-offs in the design of CMOS comparators
A. Rodríguez-Vázquez, M. Delgado-Restituto and J.M. de la Rosa-Utrera
Book Chapter · Trade offs in analog circuit design, pp 407-441, 2002
abstract doi

This chapter first presents an overview of CMOS voltage comparator architectures and circuits. Starting from the identification of the comparator behavior, Section 14.2 introduces several comparator architectures and circuits. Then, Section 14.3 assumes these topologies, characterizes high-level attributes, such as static gain, unitary time constant, etc., and analyzes the resolution-speed trade-off for each architecture. Such analysis provides a basis for comparison among architectures. These previous sections of the chapter neglect the influence of circuit dissymmetries. Dissymmetries are covered in Section 14.4 and new comparator topologies are presented to overcome the offset caused by dissymmetries. Related high-level trade-offs for these topologies are also studied in this section.

Other publications

Overview of Sigma-Delta Modulators: Fundamentals, State-of-the-Art Survey and Practical Design Guide
J.M. de la Rosa
Course · Advanced Topics in Microelectronic Engineering, Tyndall National Institute, Cork (Ireland), 2013
abstract

This course presents a systematic and comprehensive description of the universe of ΣΔMs, their diverse types of architectures, circuit techniques, analysis and synthesis methods and CAD tools, as well as their practical design considerations - going from system-level specifications to silicon integration, prototyping, and measurements. A number of case studies and examples are given to illustrate the design considerations explained in the course, covering the whole design flow of SD ADCs. A review of the state of the art on nanometer CMOS implementations is also presented in the course, giving a survey of cutting-edge ΣΔM architectures and circuit techniques. The statistical data extracted from more than 300 cutting-edge Integrated Circuits (ICs) is exhaustively analysed to identify trends, design challenges, as well as the most efficient solutions proposed for different applications in the frontiers of ΣΔMs.

Nanometer CMOS Wireless Transceivers - Application to the Next Generation of Software-Defined-Radio Mobile Terminals
J.M. de la Rosa
Course · Escuela Argentina-Uruguaya de Micro-Nanoelectrónica, Tecnología y Aplicaciones, 2010
abstract

Abstract not avaliable

Reconfigurable chips: Towards the fourth generation of mobile phones
J.M. de la Rosa
Didactic Material · Coloquios en la Facultad de Física. Universidad de Sevilla, 2007
abstract pdf

Abstract not available

CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 2
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course · Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
abstract pdf

Based on a comprehensive description of sigma-delta modulation operating principles, this course presents an overview of the advances in architectures, circuits, models, methods and practical considerations for the design of high-performance CMOS sigma-delta A/D interfaces - from system to physical level design - as well as packaging and test. The course is divided into three theoretical lectures and two practical sessions. The first lecture describes the basic concepts, fundamentals and architectures and makes a revision of the state-of-the-art on CMOS sigma-delta ADC integrated circuits. The second lecture moves farther down to the circuit- and physical level to present the building blocks normally used to implement sigma-delta ADCs as well as the impact of their error mechanisms. The analyses and models covered in the first two lectures form the basis of a systematic design methodology described in the third session, where a SIMulink-based SIgma-DElta Simulator (SIMSIDES) is introduced. Finally, as an application, two practical exercises will be carried out by using SIMSIDES in order to put in practice the knowledge learned in the course.

CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 1.b
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course · Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
abstract pdf

CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 1.a
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course · Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
abstract pdf

Microelectronics: The Engine of the Information Society
J.M. de la Rosa
Didactic Material · Semana de la Ciencia y la Tecnología. Escuela Superior de Ingenieros, Universidad de Cádiz, 2004
abstract pdf

Abstract not available

Bandpass Sigma-Delta Modulators: Principles, Architecture and Circuits
A. Rodríguez-Vázquez and J.M. de la Rosa
Course · CMOS Data Converters for Communications. ESD-MSD Mixed Signal Design Cluster, 2002
abstract pdf

Abstract not available

BROWSE BY TYPE

Journals591
Conferences1174
Books30
Book chapters81
Others9

BROWSE BY YEAR

202414

202335

202281

202183

2020103

201977

2018106

2017111

2016104

2015111

2014104

201380

2012108

2011102

2010120

200977

200867

200770

200665

200578

200468

200362

200259

RESEARCH

Follow @BibliotecaImse

IMSE Publications

ADVANCED SEARCH

Author: José M. de la Rosa Utrera
Year: Since 2002

Journal Papers

Conferences

Books

Book Chapters

Other publications

BROWSE BY TYPE

BROWSE BY YEAR

RESEARCH

IMSE Publications

ADVANCED SEARCH

Author: José M. de la Rosa Utrera Year: Since 2002

Journal Papers

Conferences

Books

Book Chapters

Other publications

BROWSE BY TYPE

BROWSE BY YEAR

RESEARCH

SHARE

Author: José M. de la Rosa Utrera
Year: Since 2002