Found results matching for:
Author: José M. Mora Gutiérrez
Year: Since 2002
Journal Papers
Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA
F.E. Potestad-Ordonez, E. Tena-Sanchez, J.M. Mora-Gutierrez, M. Valencia-Barrero and C.J. Jimenez-Fernandez
Journal Paper · IEEE Access, vol. 9, pp 168444-168454, 2021
abstract
doi
Attacks on cryptocircuits are becoming increasingly sophisticated, requiring designers to include more and more countermeasures in the design to protect it against malicious attacks. Fault Injection Attacks and Differential Fault Analysis have proven to be very dangerous as they are able to retrieve the secret information contained in cryptocircuits. In this sense, Trivium cipher has been shown to be vulnerable to this type of attack. This paper presents four different fault detection schemes to protect Trivium stream cipher implementations against fault injection attacks and differential fault analysis. These countermeasures are based on the introduction of hardware redundancy and signature analysis to detect fault injections during encryption or decryption operations. This prevents the attacker from having access to the faulty key stream and performing differential fault analysis. In order to verify the correct operation and the effectiveness of the presented schemes, an experimental system of non-invasive active attacks using the clock signal in FPGA has been designed. This system allows to know the fault coverage for both multiple and single faults. In addition, the results of area consumption, frequency degradation, and fault detection latency for FPGA and ASIC implementations are presented. The results show that all proposed countermeasures are able to provide a fault coverage above 79% and one of them reaches a coverage of 99.99%. It has been tested that the number of cycles for fault detection is always lower than the number of cycles needed to apply the differential fault analysis reported in the literature for the Trivium cipher.
Experimental FIA Methodology using Clock and Control Signal Modifications under Power Supply and Temperature Variations
F.E. Potestad-Ordóñez, E. Tena-Sánchez, J.M. Mora-Gutierrez, M. Valencia-Barrero and C.J. Jiménez-Fernández
Journal Paper · Sensors, vol. 21, no. 22, article 7596, 2021
abstract
doi pdf
The security of cryptocircuits is determined not only for their mathematical formulation, but for their physical implementation. The so-called fault injection attacks, where an attacker inserts faults during the operation of the cipher to obtain a malfunction to reveal secret information, pose a serious threat for security. These attacks are also used by designers as a vehicle to detect security flaws and then protect the circuits against these kinds of attacks. In this paper, two different attack methodologies are presented based on inserting faults through the clock signal or the control signal. The optimization of the attacks is evaluated under supply voltage and temperature variation, experimentally determining the feasibility through the evaluation of different Trivium versions in 90 nm ASIC technology implementations, also considering different routing alternatives. The results show that it is possible to inject effective faults with both methodologies, improving fault efficiency if the power supply voltage decreases, which requires only half the frequency of the short pulse inserted into the clock signal to obtain a fault. The clock signal modification methodology can be extended to other NLFSR-based cryptocircuits and the control signal-based methodology can be applied to both block and stream ciphers.
ASIC design and power characterization of standard and low power multi-radix Trivium
J.M. Mora, C.J. Jiménez and M. Valencia
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 11, pp 2682-2686, 2020
abstract
doi
We are presenting the experimental measurements of the power consumption and the maximum frequency in an ASIC prototype of 12 versions of the Trivium cipher: one standard version and two low power versions (FPLP and MPLP) with four different radix (radix-1, radix-2, radix-8 and radix-16). It is also described the mechanism for measuring power consumption in each Trivium implemented in the ASIC prototype. The clock tree of the ciphers has been designed in such a way that the clock signal of each Trivium can be cut independently. The experimental setup uses the Agilent 93000 testing system. The results show that the higher radix versions have a lower operating frequency and that the lower radix low-power versions have a very high power reduction. However, the Trivium radix-16 versions generate 16 bit/clock cycle so the measurements conclude that the MPLP version is the one with the lowest power consumption per bit (0.69 pJ/bit at 50 MHz.).
Multiradix Trivium Implementations for Low-Power IoT Hardware
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp 3401-3405, 2017
abstract
doi
The integration of lightweight symmetric encryption is becoming increasingly widespread in very low-power Internet of Things applications, with the rapid emergence of very low energy block and stream ciphers in portable and wireless systems. Trivium is one of the lightweight stream ciphers shortlisted for the hardware profile of the eSTREAM project. This paper describes low-power multiradix Trivium implementations based on the use of parallelization techniques to reduce dynamic power consumption. The low-power Trivium designs were implemented and characterized in TSMC 90 nm to compare area resources and power reduction. The implementation results show that our proposed designs offer dynamic power savings of 31%-45% with radix-1 and radix-2 when compared with the standard Trivium, and 15% with radix-8. There is no improvement, however, with radix-16.
Power and energy issues on lightweight cryptography
A.J. Acosta, E. Tena-Sánchez, C.J. Jiménez and J.M. Mora
Journal Paper · Journal of Low Power Electronics, vol. 13, no. 3, pp 326-337, 2017
abstract
doi
Portable devices such as smartphones, smart cards and other embedded devices require encryption technology to guarantee security. Users store private data in electronic devices on a daily basis. Cryptography exploits reliable authentication mechanisms in order to ensure data confidentiality. Typical encryption security is based on algorithms that are mathematically secure. However, these algorithms are also costly in terms of computational and energy resources. The implementation of security mechanisms on dedicated hardware has been shown as a first-order solution to meet prescribed security standards at low power consumption with limited resources. These are the guidelines of the so-called lightweight cryptography. Upcoming Internet of Thing (IoT) is extensively demanding solutions in this framework. Interestingly, physical realizations of encryption algorithms can leak side-channel information that can be used by an attacker to reveal secret keys or private data. Such physical realizations must therefore be holistically addressed. Algorithm, circuit and layout aspects are to be considered in order to achieve secure hardware against active and passive attacks. In order to address the challenges raised by the IoT, both academia and industry are these days devoting significant efforts to the implementation of secure lightweight cryptography. This paper is a survey of (i) lightweight cryptography algorithms; (ii) techniques to reduce power applied to cryptohardware implementations; (iii) vulnerability analysis of low-power techniques against sidechannel attacks; and (iv) possibilities opened to emerging technologies and devices in the "More than Moore" scenario.
Trivium hardware implementations for power reduction
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Journal Paper · International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 188-198, 2017
abstract
doi
This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.
CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutierrez and M.A. Lagos-Florido
Journal Paper · IEEE Transactions on Nuclear Science, vol. 63, no. 4, pp. 2379-2389, 2016
abstract
doi
This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35 μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.
A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz,A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Journal Paper · IEEE Transactions on Magnetics, vo. 51, no. 1, article 4001804, 2015
abstract
doi pdf
This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D magnetometer for space applications, with a significant reduction in mass and volume while maintaining a high sensitivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances and a rad-hard mixed-signal ASIC designed in a standard 0.35 μm CMOS technology. The ASIC performs sensor-signal conditioning and analogue-to-digital conversion, and handles calibration tasks, system configuration, and communication with the outside. The proposed system provides high sensitivity to low magnetic fields, down to 3 nT, while offering a small and reliable solution under extreme environmental conditions in terms of radiation and temperature.
Four-channel self-compensating single-slope ADC for space environments
S. Sordo-Ibáñez, S. Espejo-Meana, B. Piñero-García, A. Ragel-Morales, J. Ceballos-Cáceres, M. Muñoz-Díaz, L. Carranza-González, A. Arias-Drake, J.M. Mora-Gutiérrez, M.A. Lagos-Florido and J. Ramos-Martos
Journal Paper · Electronics Letters, vol. 50, no.8, pp 579-581, 2014
abstract
doi pdf
A multichannel high-resolution single-slope analogue-to-digital converter (SS ADC) is presented that automatically compensates for process, voltage and temperature variations, as well as for radiation effects, in order to be used in extreme environmental conditions. The design combines an efficient implementation by using a feedback loop that ensures an inherently monotonic and very accurate ramp generation, with high levels of configurability in terms of resolution and conversion rate, as well as input voltage range. The SS ADC was designed in a standard 0.35 μm CMOS technology. Experimental measurements of the performance and stability against radiation and temperature are presented to verify the proposed approach.
A precise 90 degrees quadrature OTA-C oscillator tunable in the 50-130-MHz range
B. Linares-Barranco, T. Serrano-Gotarredona, J. Ramos-Martos, J. Ceballos-Cáceres, J.M. Mora and A. Linares-Barranco
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 4, pp 649-663, 2004
abstract
doi pdf
We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-mum CMOS process. The oscillator is tunable in the frequency range from 50 to 130 MHz. The two phases produced by the oscillator show a low-quadrature phase error. A novel current-mode amplitude control scheme is developed that allows for very small amplitudes. Stability of the amplitude control loop is studied as well as design considerations for its optimization. Experimental results are provided.
Precise 90 degrees quadrature current-controlled oscillator tunable between 50-130 MHz
B. Linares-Barranco, T. Serrano-Gotarredona, J. Ramos-Martos, J. Ceballos-Cáceres, J.M. Mora and A. Linares-Barranco
Journal Paper · Electronics Letters, vol. 39, no. 11, pp 823-825, 2003
abstract
doi pdf
A VLSI continuous time sinusoidal OTA-C quadrature oscillator fabricated in a standard double-poly 0.8 mum CMOS process is presented. The oscillator is tunable in the frequency range from 50-130 MHz. The two phases produced by the oscillator show an extremely low phase difference error (less than 2degrees over the whole frequency range). A novel current mode amplitude control scheme is developed that allows for very small amplitudes. Experimental results are provided.
Conferences
Review of Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA
F.E. Potestad-Ordoñez, E. Tena-Sánchez, C. Fernández-García, V. Zúñiga-González, J.M. Mora Gutiérrez, C. Baena-Oliva, P. Parra-Fernández, A.J. Acosta-Jiménez and C.J. Jiménez-Fernández
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
abstract
In this paper, we present a review of the work [1]. In this work a complete setup to break ASIC implementations of standard Trivium stream cipher was presented. The setup allows to recover the secret keys combining the use of the active noninvasive technique attack of clock manipulation and Differential Fault Analysis (DFA) cryptanalysis. The attack system is able to inject transient faults into the Trivium in a clock cycle and sample the faulty output. Then, the internal state of the Trivium is recovered using the DFA cryptanalysis through the comparison between the correct and the faulty outputs. The secret key of the Trivium were recovered experimentally in 100% of the attempts, considering a real scenario and minimum assumptions.
[1] F.E. Potestad-Ordoñez, M. Valencia-Barrero, C. Baena-Oliva, P. Parra-Fernández, C.J. Jiménez-Fernández, "Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA". In Sensors, vol. 20, num. 6909, pp. 1-19, 2020.
Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
E. Tena-Sánchez, F.E. Potestad-Ordoñez, V. Zúñiga-González, C. Fernández-García, J.M. Mora Gutiérrez, C.J. Jiménez-Fernández and A.J. Acosta-Jiménez
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
abstract
In this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of proposals have been presented to design circuits resistant to Power Analysis attacks. In this paper a deep review of the state of the art of gate-level countermeasures against Power Analysis attacks has been done, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison.
[1] E. Tena-Sánchez, F.E. Potestad-Ordoñez, C.J. Jiménez-Fernández, A.J. Acosta and R. Chaves, "Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks," Applied Sciences, 12(5), 2390, 2022.
Integration of two High-Performance Mixed-Signal Data Conversion IPs
G. Leger, A. Gines, E. Peralias, J.M. Mora and A. Ragel
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2021
abstract
This brief presents the experience of integrating two high-performance Data Converter IPs, an ADC and a DAC, in a single rad-hard test-chip. A system-level perspective is taken, underlining the importance of Design-for-Testability (DfT) structures and tuning structures for debugging purposes and achieving first-time right silicon. Modeling the interactions between domains (PCB, package, analog and digital) is also highlighted as a key to success, particularly for high performance circuits operating at the limits of technology.
Characterization, Screening and Qualification of the MEDA Wind-Sensor ASIC
S. Espejo, J. Ceballos, A. Ragel, L. Carranza, J.M. Mora, M.A. Lagos, J. Ramos, S. Sordo, E. Cordero and D. López
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2018
abstract
The paper describes the final characterization results of the MEDA-WS ASIC, which was described in a previous paper in AMICSA-2016. It describes as well the qualification and the screening processes that have been carried out, and the present status of its integration and calibration in the final engineering and flying modules of the wind-sensor instrument.
Low power implementation of Trivium stream cipher
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández, E. Potestad and M. Valencia-Barrero
Conference · Workshop on Cryptographic Hardware and Embedded Systems CHES 2015
abstract
Trivium is a synchronous stream cipher designed to generate up to 264 bits of key stream from an 80-bit secret key and an 80-bit initialization vector (IV). The architecture of this cipher is based on a 288-bit cyclic shift register accompanied by an array of combinational logic (AND, OR and XOR) to provide its feedback. The key stream generation consists mainly on an iterative process which updates some bits in the state register with logic operations to generate one bit of key stream.
A Front-End ASIC for a 3-D Magnetometer for Space Applications Based on Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · European Conference on Magnetic Sensors and Actuators EMSA 2014
abstract
Abstract not avaliable
A Rad-Hard Multichannel Front-End Readout ASIC for Space Applications
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · IEEE International Workshop on Metrology for Aerospace METROAEROSPACE 2014
abstract
This paper presents a single-chip solution for sensor-signals conditioning and digitalization in space applications. The rad-hard ASIC implements a set of 6 generic instrumentation channels that are highly configurable in terms of resolution, conversion rate, and input voltage range, providing a flexible solution for space applications requiring the digital acquisition of slow input signals with medium-to-high resolutions. The resolution can be configured between 12 bits at 19.6 kS/s and 16 bits at 2.6 kS/s. The differential input voltage range can be extended up to 4 Vpp. The instrumentation channels combine a programmable-gain, high input impedance instrumentation amplifier and dual-slope analog-to-digital converters with radiation hardening by design (RHBD) techniques in a standard 0.35 μm CMOS technology. Experimental results demonstrate the performance of the ASIC across an operating temperature range of -90 ºC to +125 ºC and its robustness against radiation effects up to 318 krad of TID, absence of latch-up up to at least 81.8 MeV·cm2/mg, and a SEUs LETth of 22.5 MeV·cm2/mg.
SEE Characterization of a Magnetometer Front-End ASIC using a RHBD Digital Library in AMS 0.35μm CMOS
J. Ramos-Martos, A. Arias-Drake, L. Carranza-González, S. Sordo-Ibáñez, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, S. Espejo-Meana and M.A. Lagos-Florido
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2014
abstract
A radiation-hardened-by-design (RHBD) digital library, developed for the Austria Microsystems (AMS) 0.35μm CMOS technology has been applied in a mixedsignal ASIC that operates as a multi-channel data acquisition system for magnetometers using anisotropic magnetoresistances (AMR). The circuit has been tested in the Heavy-Ion facilities of the Université Catholique de Louvain-la-Neuve (HIF-UCL). The experimental results demonstrate a LET threshold of 22.5 MeV·cm2/mg and absence of latchup up to 81.8 MeV·cm2/mg. This radiation-tolerant performance is obtained at the cost of a penalty in area and power with respect to the unhardened technology.
An Adaptive Approach to On-Chip CMOS Ramp Generation for High Resolution Single-Slope ADCs
S. Sordo-Ibanez, B. Piñero-García, S. Espejo-Meana, A. Ragel-Morales, J. Ceballos-Cáceres, M. Muñoz-Díaz, L. Carranza-González, A. Arias-Drake, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · European Conference on Circuit Theory and Design ECCTD 2013
abstract
Many image sensors employ column-parallel ADCs in their readout structures. Single-slope ADCs are ideally suited for these multi-channel applications due to their simplicity, low power and small overall area. The ramp generator, shared by all the converters in the readout architecture, is a key element that has a direct effect in the transfer characteristic of single-slope ADCs. Because a digital counter is inherently present in this conversion scheme, one common practice is to use a digital-to-analog converter driven by the counter to generate the ramp. Given the direct relationship between the DAC and the ADC transfer characteristics, one of the main issues is to ensure a sufficient linearity of the DAC, with special emphasis on its monotonicity. Very often, in particular when medium to high resolutions are aimed, this requires calibration of the DAC, which must be repeated every once in a while to account for temperature, process, power supply, and aging variations. This paper presents an inherently monotonic ramp generator with high levels of linearity and stability against any expected source of variations, combined with a very efficient realization and an inherent automatic adaptability to different resolutions. The ramp generator has been designed using radiation hardening by design (RHBD) techniques, allowing its use in space applications.
SEE Characterization of the AMS 0.35 μm CMOS Technology
J. Ramos-Martos, A. Arias-Drake, J.M. Mora-Gutiérrez, M. Muñoz-Díaz, A. Ragel-Morales, B. Piñero-García, J. Ceballos-Cáceres, L. Carranza-González, S. Sordo-Ibáñez, M.A. Lagos-Florido and S. Espejo-Meana
Conference · European Conference on Radiation and Its Effects on Components and Systems RADECS 2013
abstract
This work presents experimental results for the single-event effects characterization of a commercial (Austria Microsystems) 0.35 ΣΔm CMOS technology. It improves and expands previous results. The knowledge gained is being applied in the development of a RHBD digital library.
Design Methodology and Development of Mixed-Signal ASICs for Space Applications in Standard CMOS Technology
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2013
abstract
The design of mixed-signal ASICs for on-board space applications can provide several advantages that would not otherwise be possible with discrete components. However, extreme environmental conditions in terms of radiation and temperature imply a detailed knowledge of the technology used while CMOS commercial foundries do not usually have or make available these data. The aim of this work is to overcome these obstacles and offer solutions for space applications based on mixed-signal ASICs in commercial CMOS technologies. This paper presents the methodology followed for the assessment of a commercial (Austria Microsystems, AMS) 0.35 µm CMOS technology and for the development of a radiation hardened by design (RHBD) digital library. In addition, the described methodology has been applied to the development of two mixed-signal ASICs. The first chip performs the function of an optical digital transceiver for diffused-light intra-satellite optical communications. The second one implements a front-end solution for sensor data acquisition and signal conditioning and consists in a set of configurable multi-mode dual slope ADCs with resolution up to 16 bits.
A Front-End ASIC for a 16-Bit Three-Axis Magnetometer for Space Applications Based on Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · Conference on the Design of Circuits and Integrated Systems DCIS 2013
abstract
Many space applications require the measurement of magnetic fields. This includes many scientific and meteorological instruments, as well as satellite attitude control systems. The most widely used method for measuring magnetic fields in space missions has been the use of fluxgate sensors, mainly due to their reliability, robustness and relatively small mass and volume with respect to the total size of the satellite. However, the current trends of cost reduction and standardization in aerospace technology tends towards the design of small satellites, commonly called nano-satellites or even picosatellites, embodying a new challenge in the design of low-cost space instrumentation. In this scope, fluxgate sensors are massy and large enough so that their use is not addressable for these small satellites. This paper presents an alternative design of a three-axis magnetometer for the measurement of the strength and direction of an incident magnetic field in space applications, with a significant reduction in mass and volume while maintaining a high detectivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances (AMR) and a radiation hardened by design (RHBD) mixed-signal ASIC that performs signal conditioning and analog to digital conversion up to 16 bits, and also handles calibration tasks, system configuration and communication with the outside. The use of an ASIC instead of discrete components reduces both weight and volume, and achieves improvements in performance and consumption. The proposed magnetometer provides high sensitivy to low magnetic fields up to 30 μG of resolution while offering a small, low cost and reliable solution for space applications.
OWLS: A Mixed-Signal Asic for Optical Wire-Less Links in Space Instruments
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, M.A. Lagos-Florido, S. Sordo-Ibáñez, S. Espejo-Meana, I. Arruego, J. Martínez-Oter and M.T. Álvarez
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2012
abstract
pdf
This paper describes the design of a mixed-signal ASIC for space application and the techniques employed for radiation
hardening and temperature effects compensation. The work is part of a planned long-term effort and collaboration
between "Instituto de Microelectrónica de Sevilla (IMSE)", "Universidad de Sevilla (US)", and "Instituto Nacional de
Técnica Aeroespacial (INTA)" aimed to consolidate a group of experienced mixed-signal space-ASIC designers.
Low power implementation of Trivium stream cipher
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and Valencia-Barrero
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2012
abstract
This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The design was simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. The aim of this paper is to evaluate the suitability of this technique and compare the power consumption and the core area of the low power and standard implementations. The results show that the application of the technique reduces power consumption by more than 20% with only a slight penalty in area and operating frequency.
Evaluation of the AMS 0.35μm CMOS Technology for use in Space Applications
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, M.A. Lagos-Florido, S. Sordo-Ibáñez and S. Espejo-Meana
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2012
abstract
pdf
The design of mixed-signal application specific integrated circuits (ASICs) requires a detailed knowledge of the
behavior of the technology which exceeds the needs of digital designs. For space applications, with its
extended-temperature and radiation environment, the job of the mixed-signal designer is made even more difficult as in
most cases commercial foundries do not have or make available data on the behavior of their devices under those nonstandard
conditions.
Radiation Characterization of the austriamicrosystems 0.35 μm CMOS Technology
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero.García, M. Muñoz-Díaz, M.A. Lagos-Florido and S. Espejo-Meana
Conference · Conference on Radiation Effects on Components and Systems RADECS 2011
abstract
pdf
The design of mixed-signal ASICs for space requires a detailed knowledge of the behaviour of the technology to be used in an environment imposing radiation levels and temperatures beyond those found in standard applications. Commercial foundries providing standard CMOS technologies do not usually have or make available data on the behaviour of their devices under those conditions. Instituto de Microelectrónica de Sevilla and Universidad de Sevilla (IMSE-USE) have started a long term collaboration with the Spanish Instituto Nacional de Técnica Aeroespacial (INTA) to extend its experience on mixed-signal design to the field of ASICs for space applications. The assessment of a commercial (austriamicrosystems) 0.35 μm CMOS technology is a first step towards the development of a mixed-signal design methodology, including an RHBD digital library suitable for use in space
conditions.
Metodologia orientada a la elección de FPGAs con prioridad en el consumo de potencia
J.M. Mora-Gutierrez, G. Sassaw-Teshome, C.J. Jiménez-Fernández and M.Valencia-Barrero
Conference · Iberchip XVI Workshop IWS 2010
abstract
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En este trabajo se presenta una metodología de diseño orientada a explorar el cada vez más amplio conjunto de FPGAs con el fin de seleccionar la mejor opción. Los parámetros que se utilizan para realizar la exploración son los recursos consumidos, la frecuencia de operación y el consumo de potencia. Sobre este último parámetro, el más difícil de medir, se hace un especial énfasis. Se exploran dos fabricantes (Altera y Xilinx), dos familias diferentes de cada fabricante y dos subfamilias dentro de cada familia, una de la gama alta y otra de la gama baja. Esta exploración se ha realizado implementando dos circuitos que realizan la operación división de números de 64 bits usando dos algoritmos con plena vigencia.
Estudio comparativo de los divisores en la tecnología nanométrica CMOS
G. Sassaw, C.J. Jiménez, J.M. Mora and M. Valencia
Conference · II Simposio Internacional de Computación y Electrónica 2009
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Son varios los algoritmos de divisores propuestos para su realización en hardware, sin que haya un 'mejor divisor'. La búsqueda de un diseño óptimo para cada aplicación específica hace que sea indispensable la investigación de los algoritmos existentes a medida que se produce el avance de la tecnología. En este trabajo se presentan los resultados de la caracterización en área, tiempo y consumo de potencia de varias implementaciones de divisores en tecnologías CMOS nanométricas de 90 y 65 nm. Para la implementación se ha utilizado el flujo de diseño ASIC semicustom con elección entre tres voltajes de umbrales.
A 10 μm Thick Poly-Sige gyroscope processed above 0.35 μm CMOS
A. Scheurle, T. Fuchs, K. Kehr, C. Leinenbach, S. Kronmüller, A. Arias, J. Ceballos, M.A. Lagos, J.M. Mora, J.M. Muñoz, A. Ragel, J. Ramos, S. Van Aerde, J. Spengler, A. Mehta, A. Verbist, B. Du Bois, A. Witvrouw
Conference · IEEE International Conference on Micro Electro Mechanical Systems MEMS 2007
abstract
This paper describes a monolithically integrated omegaz-gyroscope fabricated in a surface-micromaching technology. As functional structure, a 10 μm thick Silicon-Germanium layer is processed above a standard high voltage 0.35 μm CMOS-ASIC. Drive and Sense of the in plane double wing gyroscope is fully capacitively. Measurement of movement is also done fully capacitively in continuous-time baseband sensing. For characterization, the gyroscope chip is mounted on a breadboard with auxiliary circuits. A noise floor of 0.01 degs/sqrt(Hz) for operation at 3 mBar is achieved.
Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits
A.J. Acosta, J.M. Mora, J. Castro and P. Parra
Conference · Conference on VLSI Circuits and Systems III, 2007
abstract
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The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the signal on the wire, as propagation delay, signal integrity, transition time, among others. The power concerns related to buffering have also received much attention, because of the low power requirements of modem integrated systems. In the same way, the buffer insertion has strong impact on the reliability of synchronous systems, since the suited distribution of clock requires reduced or controlled clock-skew, being the buffer and wire sizing, a crucial aspect. In a different way, buffer insertion has been also used to reduce noise generation, especially in heavily loaded nets, since the inclusion of buffers help to desynchronize signal transitions. However, the inclusion of buffers of inverters to improve one or more of these characteristics have often negative effect on another parameters, as it happens in the average and peak of supply current. Mainly, the inclusion of a buffer to reduce noise (peak power), via desynchronizing transitions, could introduce more dynamic consumption, but reducing the short-circuit current because of the increment of signal slope. Thus, the average/peak current optimization can be considered a design trade-off. In this paper, the mechanism to obtain an average/peak power optimization procedure are presented. Selected examples show the feasibility of minimizing switching noise with negligible impact on average power consumption.
Processing of MEMS Gyroscopes on Top of CMOS ICs
A. Witvrouw, A. Mehta, A. Verbist, B. Du Bois, S. Van Aerde, J. Ramos-Martos, J. Ceballos, A. Ragel, J.M. Mora, M.A. Lagos, A. Arias, J.M. Hinojosa, J. Spengler, C. Leinenbach, T. Fuchs and S. Kronmüller
Conference · IEEE International Solid-State Conference ISSCC 2005
abstract
Integrated 10 μm thick poly-SiGe gyroscopes are processed on top of an 8" standard 0.35 μm CMOS wafer with 5 metal levels by using an advanced plasma-enhanced chemical vapor deposition multi-layer technology. The gyroscopes are free-moving with Q-factors for the drive mode up to 10000 at the pressure of 0.8 mTorr while the CMOS chip is fully functional.
SIGEM, low-temperature deposition of Poly-SiGe MEMs structures on standard CMOS circuits
J. Ramos-Martos, J. Ceballos-Cáceres, A. Ragel-Morales, J.M. Mora-Gutierrez, A. Arias-Drake, M.A. Lagos-Florido, J.M. Muñoz-Hinojosa, A. Mehta, A. Verbist, B. du Bois, K. Kehr, C. Leinenbach, S. Van Aerde, J. Spengler and A. Witvrouw
Conference · Conference on VLSI Circuits and Systems II SPIE 2005
abstract
Fabrication of surface-micromachined structures by a post-processing module above standard IC circuits is an efficient way to produce monolithic microsystems, allowing nearly independent optimization of the circuitry and the MEMS process. However, until now the high-temperature steps needed for deposition of poly-Si have limited its application. SiGeM explores the possibilities offered by the low-temperature (450 degrees C) deposition and structuring of poly-SiGe layers, which is compatible with the temperature budget of fully-processed standard IC wafers. In the SiGeM project several low-temperature deposition methods (CVD, PECVD, LPCVD) were developed, and were evaluated with respect to growth rate and material quality. The interconnection technology to the underlying CMOS circuitry was also developed. The capabilities of this new integration technology will be demonstrated in a monolithic high-performance rate-of-turn sensor, currently considered the most demanding MEMs application in terms of material properties of the structural layer (thickness > 10 mu m, stress gradient < 03MPa/mu m) and signal processing circuitry (capacitance resolution in the aF range, SNR > 110 dB). System partitioning will combine analog and DSP circuit techniques to maximize resolution and stability. Parasitic electrical coupling within different parts of the system has been analyzed, and countermeasures to reduce it have been incorporated in the design. The feasibility of the approach has already been proved by preliminary characterization of working prototypes containing released microstructures deposited on top of preamplifier circuits built on a 0.35 mu m, 5-metal, 2-poly, standard CMOS process from Philips Semiconductors. Resonance frequencies are in good agreement with predictions, and quality factors above 8000 have been obtained at pressures of 0.8 mTorr. Measured SNR confirms the capability to achieve a resolution of 0.015 degrees/s over a bandwidth of 50 Hz.
A precise 90 degrees quadrature OTA-C VCO between 50-130 MHz
B. Linares-Barranco, T. Serrano-Gotarredona, J. Ramos-Martos, J. Ceballos-Cáceres, J.M. Mora and A. Linares-Barranco
Conference · International Symposium on Circuits and Systems ISCAS 2004
abstract
We present a VLSI continuous time sinusoidal OTA-C quadrature oscillator fabricated in a standard double-poly 0.8mum CMOS process. The oscillator is tunable in the frequency range from 50-130 MHz. A symmetric topology assures that the two phases produced by the oscillator present an extremely low phase difference error (less than 2degrees over the whole frequency range). A novel current mode amplitude control scheme is developed that allows for very small amplitudes. Experimental results are provided.
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