Found results matching for:
Author: Carlos J. Jiménez Fernández
Year: Since 2002
Journal Papers
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher
F.E. Potestad-Ordóñez, E. Tena-Sánchez, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and R. Chaves
Journal Paper · IEEE Access, vol. 10, pp 65548-65561, 2022
abstract
doi
Differential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the vulnerabilities of physical implementations of block ciphers, currently used in a multitude of applications, such as the Advanced Encryption Standard (AES). In order to minimize these types of vulnerabilities, several mechanisms have been proposed to detect fault attacks. However, these mechanisms can have a significant cost, not fully covering the implementations against fault attacks or not taking into account the leakage of the information exploitable by the power analysis attacks. In this paper, four different approaches are proposed with the aim of protecting the AES block cipher against DFA. The proposed solutions are based on Hamming code and parity bits as signature generators for the internal state of the AES cipher. These allow to detect DFA exploitable faults, from bit to byte level. The proposed solutions have been applied to a T-box based AES block cipher implemented on Field Programmable Gate Array (FPGA). Experimental results suggest a fault coverage of 98.5% and 99.99% with an area penalty of 9% and 36% respectively, for the parity bit signature generators and a fault coverage of 100% with an area penalty of 18% and 42% respectively when Hamming code signature generator is used. In addition, none of the proposed countermeasures impose a frequency degradation, in respect to the unprotected cipher. The proposed work goes further in the evaluation of the proposed DFA countermeasures by evaluating the impact of these structures in terms of power side-channel. The obtained results suggest that no extra information leakage is produced that can be exploited by PA. Overall, the proposed DFA countermeasures provide a high fault coverage protection with a low cost in terms of area and power consumption and no PA security degradation.
Hardware Countermeasures Benchmarking against Fault Attacks
F.E. Potestad-Ordóñez, E. Tena-Sánchez, A.J. Acosta, C.J. Jiménez-Fernández and R. Chaves
Journal Paper · Applied Sciences, vol. 12, no. 5, article 2443, 2022
abstract
doi
The development of differential fault analysis (DFA) techniques and mechanisms to inject faults into cryptographic circuits brings with it the need to use protection mechanisms that guarantee the expected level of security. The AES cipher, as a standard, has been the target of numerous DFA techniques, where its security has been compromised through different formulations and types of fault injections. These attacks have shown vulnerabilities of different AES implementations and building blocks. Consequently, several solutions have been proposed that provide additional protection to cover the identified vulnerabilities. In this paper, an extensive analysis has been carried out covering the existing fault injection techniques, the types of faults, and the requirements needed to apply DFA. Additionally, an analysis of the countermeasures reported in the literature is also presented, considering the protection provided, the type of faults considered, and the coverage against fault attacks. The eight different types of fault that allow us to perform DFAs on the AES cipher have been differentiated, as well as the vulnerabilities of the cipher. On the other hand, two comparisons have been made considering frequency penalty vs. area and fault coverage vs. area and frequency overhead. A metric has been proposed to compare the fault coverage of all the proposed solutions. To conclude, a final analysis is presented discussing the key aspects when choosing a particular solution and the possible development of new countermeasures to provide further protection against DFA.
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
E. Tena-Sánchez, F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, A.J. Acosta and R. Chaves
Journal Paper · Applied Sciences, vol. 12, no. 5, article 2390, 2022
abstract
doi
The fast settlement of privacy and secure operations in the Internet of Things (IoT) is appealing in the selection of mechanisms to achieve a higher level of security at minimum cost and with reasonable performances. All these aspects have been widely considered by the scientific community, but more effort is needed to allow the crypto-designer the selection of the best style for a specific application. In recent years, dozens of proposals have been presented to design circuits resistant to power analysis attacks. In this paper, a deep review of the state of the art of gate-level countermeasures against power analysis attacks has been carried out, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison. Advantages and drawbacks of the proposals are analyzed, showing quantified data for cost, performance (delay and power), and security when available. One of the main conclusions is that the RSL proposal is the best in masking, while TSPL, HDRL, SDMLp, 3sDDL, TDPL, and SABL are those with the best security performance figures. Nevertheless, a wise combination of hiding and masking as masked_SABL presents promising results.
Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA
F.E. Potestad-Ordonez, E. Tena-Sanchez, J.M. Mora-Gutierrez, M. Valencia-Barrero and C.J. Jimenez-Fernandez
Journal Paper · IEEE Access, vol. 9, pp 168444-168454, 2021
abstract
doi
Attacks on cryptocircuits are becoming increasingly sophisticated, requiring designers to include more and more countermeasures in the design to protect it against malicious attacks. Fault Injection Attacks and Differential Fault Analysis have proven to be very dangerous as they are able to retrieve the secret information contained in cryptocircuits. In this sense, Trivium cipher has been shown to be vulnerable to this type of attack. This paper presents four different fault detection schemes to protect Trivium stream cipher implementations against fault injection attacks and differential fault analysis. These countermeasures are based on the introduction of hardware redundancy and signature analysis to detect fault injections during encryption or decryption operations. This prevents the attacker from having access to the faulty key stream and performing differential fault analysis. In order to verify the correct operation and the effectiveness of the presented schemes, an experimental system of non-invasive active attacks using the clock signal in FPGA has been designed. This system allows to know the fault coverage for both multiple and single faults. In addition, the results of area consumption, frequency degradation, and fault detection latency for FPGA and ASIC implementations are presented. The results show that all proposed countermeasures are able to provide a fault coverage above 79% and one of them reaches a coverage of 99.99%. It has been tested that the number of cycles for fault detection is always lower than the number of cycles needed to apply the differential fault analysis reported in the literature for the Trivium cipher.
Experimental FIA Methodology using Clock and Control Signal Modifications under Power Supply and Temperature Variations
F.E. Potestad-Ordóñez, E. Tena-Sánchez, J.M. Mora-Gutierrez, M. Valencia-Barrero and C.J. Jiménez-Fernández
Journal Paper · Sensors, vol. 21, no. 22, article 7596, 2021
abstract
doi pdf
The security of cryptocircuits is determined not only for their mathematical formulation, but for their physical implementation. The so-called fault injection attacks, where an attacker inserts faults during the operation of the cipher to obtain a malfunction to reveal secret information, pose a serious threat for security. These attacks are also used by designers as a vehicle to detect security flaws and then protect the circuits against these kinds of attacks. In this paper, two different attack methodologies are presented based on inserting faults through the clock signal or the control signal. The optimization of the attacks is evaluated under supply voltage and temperature variation, experimentally determining the feasibility through the evaluation of different Trivium versions in 90 nm ASIC technology implementations, also considering different routing alternatives. The results show that it is possible to inject effective faults with both methodologies, improving fault efficiency if the power supply voltage decreases, which requires only half the frequency of the short pulse inserted into the clock signal to obtain a fault. The clock signal modification methodology can be extended to other NLFSR-based cryptocircuits and the control signal-based methodology can be applied to both block and stream ciphers.
Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA
F.E. Potestad-Ordóñez, M. Valencia-Barrero, C. Baena-Oliva, P. Parra-Fernández and C.J. Jiménez-Fernández
Journal Paper · Sensors, vol. 20, no.23, article 6909, 2020
abstract
doi
One of the best methods to improve the security of cryptographic systems used to exchange sensitive information is to attack them to find their vulnerabilities and to strengthen them in subsequent designs. Trivium stream cipher is one of the lightweight ciphers designed for security applications in the Internet of things (IoT). In this paper, we present a complete setup to attack ASIC implementations of Trivium which allows recovering the secret keys using the active non-invasive technique attack of clock manipulation, combined with Differential Fault Analysis (DFA) cryptanalysis. The attack system is able to inject effective transient faults into the Trivium in a clock cycle and sample the faulty output. Then, the internal state of the Trivium is recovered using the DFA cryptanalysis through the comparison between the correct and the faulty outputs. Finally, a backward version of Trivium was also designed to go back and get the secret keys from the initial internal states. The key recovery has been verified with numerous simulations data attacks and used with the experimental data obtained from the Application Specific Integrated Circuit (ASIC) Trivium. The secret key of the Trivium were recovered experimentally in 100% of the attempts, considering a real scenario and minimum assumptions.
An Academic Approach to FPGA Design Based on a Distance Meter Circuit
C.J. Jimenez-Fernandez, C. Baena-Oliva, P. Parra-Fernandez, F.E. Potestad-Ordonez and M. Valencia-Barrero
Journal Paper · IEEE Revista Iberoamericana de Tecnologías del Aprendizaje, vol. 15, no. 3, pp 123-128, 2020
abstract
doi
Digital design learning at Register Transfer (RT) level requires practical and complex examples as learning progresses. FPGAs and development boards offer a suitable platform for the implementation of these designs. However, classroom practice sessions usually last two hours, which does not allow the complexity of the designs be high enough. For this reason, interesting designs that can be made in several sessions are required. In this paper, the construction of a distance measuring system is presented. For this purpose, a distance measurement module based on ultrasound is available, the results are displayed in 7-segment displays on a Nexys4 board. This approach has been applied to three Electronic subjects at the University of Seville. The degree of satisfaction on the part of the students as well as the result of the evaluation of the experience by the teachers involved are shown.
ASIC design and power characterization of standard and low power multi-radix Trivium
J.M. Mora, C.J. Jiménez and M. Valencia
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 11, pp 2682-2686, 2020
abstract
doi
We are presenting the experimental measurements of the power consumption and the maximum frequency in an ASIC prototype of 12 versions of the Trivium cipher: one standard version and two low power versions (FPLP and MPLP) with four different radix (radix-1, radix-2, radix-8 and radix-16). It is also described the mechanism for measuring power consumption in each Trivium implemented in the ASIC prototype. The clock tree of the ciphers has been designed in such a way that the clock signal of each Trivium can be cut independently. The experimental setup uses the Agilent 93000 testing system. The results show that the higher radix versions have a lower operating frequency and that the lower radix low-power versions have a very high power reduction. However, the Trivium radix-16 versions generate 16 bit/clock cycle so the measurements conclude that the MPLP version is the one with the lowest power consumption per bit (0.69 pJ/bit at 50 MHz.).
Vulnerability Analysis of Trivium FPGA Implementations
F.E. Potestad-Ordonez, C.J. Jimenez-Fernandez and M. Valencia-Barrero
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp 3380-3389, 2017
abstract
doi
Today, the large amount of information ex-changed among various devices as well as the growth of the Internet of Things (IoT) demand the development of devices that ensure secure communications, preventing malicious agents from tapping sensitive data. Indeed, information security is one of the key challenges to address within the IoT field. Due to the strong resource constraints in some IoT applications, cryptographic algorithms affording lightweight implementations have been proposed. They constitute the so-called lightweight cryptography. A prominent example is the Trivium stream cipher, one of the finalists of the eSTREAM project. Although cryptographic algorithms are certainly simpler, one of their most critical vulnerability sources in terms of hardware implementations is side channel attacks. In this paper, it is studied the vulnerability of field-programmable gate array (FPGA) implementations of Trivium stream ciphers against fault attacks. The design and implementation of a system that alters the clock signal and checks the outcome is also described. A comparison between real and simulated fault injections is carried out in order to examine their veracity. The vulnerability of different versions of the Trivium cipher and their routing dependences has been tested in two different FPGA families. The results show that all versions of the Trivium cipher are vulnerable to fault attacks, although some versions are more vulnerable than others.
Multiradix Trivium Implementations for Low-Power IoT Hardware
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp 3401-3405, 2017
abstract
doi
The integration of lightweight symmetric encryption is becoming increasingly widespread in very low-power Internet of Things applications, with the rapid emergence of very low energy block and stream ciphers in portable and wireless systems. Trivium is one of the lightweight stream ciphers shortlisted for the hardware profile of the eSTREAM project. This paper describes low-power multiradix Trivium implementations based on the use of parallelization techniques to reduce dynamic power consumption. The low-power Trivium designs were implemented and characterized in TSMC 90 nm to compare area resources and power reduction. The implementation results show that our proposed designs offer dynamic power savings of 31%-45% with radix-1 and radix-2 when compared with the standard Trivium, and 15% with radix-8. There is no improvement, however, with radix-16.
Power and energy issues on lightweight cryptography
A.J. Acosta, E. Tena-Sánchez, C.J. Jiménez and J.M. Mora
Journal Paper · Journal of Low Power Electronics, vol. 13, no. 3, pp 326-337, 2017
abstract
doi
Portable devices such as smartphones, smart cards and other embedded devices require encryption technology to guarantee security. Users store private data in electronic devices on a daily basis. Cryptography exploits reliable authentication mechanisms in order to ensure data confidentiality. Typical encryption security is based on algorithms that are mathematically secure. However, these algorithms are also costly in terms of computational and energy resources. The implementation of security mechanisms on dedicated hardware has been shown as a first-order solution to meet prescribed security standards at low power consumption with limited resources. These are the guidelines of the so-called lightweight cryptography. Upcoming Internet of Thing (IoT) is extensively demanding solutions in this framework. Interestingly, physical realizations of encryption algorithms can leak side-channel information that can be used by an attacker to reveal secret keys or private data. Such physical realizations must therefore be holistically addressed. Algorithm, circuit and layout aspects are to be considered in order to achieve secure hardware against active and passive attacks. In order to address the challenges raised by the IoT, both academia and industry are these days devoting significant efforts to the implementation of secure lightweight cryptography. This paper is a survey of (i) lightweight cryptography algorithms; (ii) techniques to reduce power applied to cryptohardware implementations; (iii) vulnerability analysis of low-power techniques against sidechannel attacks; and (iv) possibilities opened to emerging technologies and devices in the "More than Moore" scenario.
Trivium hardware implementations for power reduction
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Journal Paper · International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 188-198, 2017
abstract
doi
This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.
A programmable and configurable ASIC to generate piecewise-affine functions defined over general partitions
P. Brox, R. Castro-Ramirez, M.C. Martinez-Rodriguez, E. Tena, C.J. Jimenez, I. Baturone and A.J. Acosta
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 12, pp 3182-3194, 2013
abstract
doi
This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated Circuit (ASIC) to generate Piecewise-Affine (PWA) functions. A Generic PWA form (PWAG) has been selected for integration, because of its suitability to implement any PWA function without resorting to approximation. The design of the ASIC in a 90 nm TSMC technology, its integration, test and characterization through different examples are detailed in the paper. Furthermore, the ASIC verification using an ASIC-in-the-loop methodology for embedded control applications is presented. To assess the characteristics of this verification, the double-integrator, a usual control application example has been considered. Experimental results validate the proposed architecture and the ASIC implementation.
Metodología de diseño electrónico dentro de prácticas obligatorias de laboratorio
C.J. Jiménez-Fernández, A. López-Ojeda and C. León de Mora
Journal Paper · Pixel-Bit: Revista de Medios y Educación, vol. 1, no. 37, pp 19-27, 2010
abstract
pdf
En la metodología de diseño de circuitos electrónicos tiene mucha importancia el uso de herramientas software. En el caso de diseño con circuitos discretos, éstas se usan para la verificación del comportamiento antes de la construcción del mismo. Esta metodología, que difícilmente puede enseñarse en clases de aula, puede verse en las prácticas de laboratorio. En esta comunicación presentamos el diseño de las prácticas de laboratorio de la asignatura Electrónica Analógica, en la que se integran herramientas informáticas de simulación antes del montaje de un sistema electrónico de forma que el alumno tenga un conocimiento del flujo de diseño analógico.
Arquitectura eficiente para la implementación hardware de sistemas de inferencia difusos
A. Cabrera, S. Sánchez-Solano, C.J. Jimémez, A. Barriga and I. Baturone
Journal Paper · Ingeniería Electrónica, Automática y Comunicaciones, vol. XXIII, no. 1, pp. 59-66, 2003
abstract
Se describen los elementos integrantes de una arquitectura de bajo costo y alto desempeño para la implementación hardware de sistemas de inferencia difusos, la cual se basa en el procesado de reglas activas, la limitación del grado de solapamiento de las funciones de pertenencia de las entradas y la utilización de métodos de defusificación simplificados. También se expone el entorno de desarrollo de sistemas difusos Xfuzzy, con énfasis en la herramienta XFVHDL, la cual permite la generación de código VHDL para los diferentes elementos de la arquitectura descrita.
Conferences
Digital Design Flow Based on Open Tools for Programmable Logic Devices
P. Navarro-Torrero, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez, A. Barriga-Barros, C.J. Jiménez-Fernández, M. Brox and P. Brox
Conference · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
abstract
doi
In this demonstrator, a design flow based on a set of open-source tools is showcased, enabling the simulation, synthesis, implementation, and programming of digital systems on programmable logic devices. Three academic examples, increasing in complexity, are shown running on open hardware development boards to demonstrate the validity of the digital design flow based on the APIO environment.
Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
abstract
doi
This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.
Teaching based on proposed by students designs: a case study
C.J. Jimenez-Fernandez, C. Baena-Oliva, P. Parra-Fernandez, M. Valencia-Barrero, F.E. Potestad-Ordoñez, E. Tena-Sanchez and A. Gallardo-Soto
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2022
abstract
Learning digital design at RT level is enhanced by practical, lab-based tasks. These tasks, if chosen appropriately, can be highly motivating. The fact that the proposal is attractive to students is an important incentive. Working with FPGAs and development boards is a very suitable tool for carrying out designs of varying complexity. This paper presents an experience developed in the Advanced Digital Design course (4th year of the Degree) consisting of a design on FPGA proposed by the students themselves based on some common specifications, such as the use of a matrix of 8x8 LEDs and that the design has to interact with some external element.
ICs tester design and its effect on application in electronics laboratories
F.E. Potestad-Ordonez, C.J. Jimenez-Fernandez, A. Gallardo-Soto, M. Valencia-Barrero, C. Baena-Oliva, P. Parra-Fernandez and E. Tena-Sanchez
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2022
abstract
One of the best methods to help students assimilate the theoretical concepts about electronic circuits is to perform laboratory sessions with real components. Therefore, the use of integrated circuits in electronics laboratory sessions and exams is very common. Since the electronic training of the students is very different, it is frequent that the devices break and become useless after a bad connection or manipulation. This paper presents the design of an integrated circuit tester, specifically the 741 and 74LS00. The effect observed on the attitude of the students after using the device (functionality check performed with the student there), before the practical sessions and laboratory exams, will be presented, and the different impressions from the point of view of the teachers will be analyzed.
Implementación hardware de un algoritmo ligero de cifrado
C. Fernández-García, V. Zúñiga-Ginzález, A. Casado-Galán, E. Tena-Sácnhez, F.E. Potestad-Ordóñez and C.J. Jiménez-Fernández
Conference · IX Jornadas de I+D+i & 1st International Workshop on STEM
abstract
Abstract not available
Desarrollo de setup experimental para la realización de cartografía EM en sistemas criptográficos
A. Casado-Galán, V. Zúñiga-González, F.E. Potestad-Ordóñez, C. Fernández-García, C.J. Jiménez- Fernández and E. Tena-Sácnhez
Conference · IX Jornadas de I+D+i & 1st International Workshop on STEM
abstract
El objetivo de la criptografía es garantizar la confidencialidad, integridad y disponibilidad de la información. En los dispositivos electrónicos, protegemos la información por medio de algoritmos criptográficos. Estos transforman la secuencia mediante operaciones matemáticas en diversas iteraciones haciendo que la información sea, con la potencia computacional de la que disponemos actualmente, imposible de recuperar sin conocer una determinada clave. Si bien teóricamente estos algoritmos son seguros, la implementación en circuitos electrónicos abre la puerta a vulnerabilidades que se pueden explotar para obtener información sobre el mensaje cifrado. Midiendo, por ejemplo, la emisión electromagnética (EM) de un circuito con instrumental apropiado para ello y tenemos un modelo matemático de este lo suficientemente preciso, podemos hackear el dispositivo y obtener la clave o mensaje cifrado. Este trabajo se centra en el desarrollo experimental de un setup de medida para realizar la cartografía EM de los sistemas criptográficos. Esto permite determinar los puntos de máxima emisión de información atacable. El setup experimental propuesto está totalmente automatizado desde un PC, donde con una mesa XY y el posicionamiento fijo de la sonda EM se puede barrer el área completa del dispositivo bajo test y capturar la emisión EM en cada punto.
Review of Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA
F.E. Potestad-Ordoñez, E. Tena-Sánchez, C. Fernández-García, V. Zúñiga-González, J.M. Mora Gutiérrez, C. Baena-Oliva, P. Parra-Fernández, A.J. Acosta-Jiménez and C.J. Jiménez-Fernández
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
abstract
In this paper, we present a review of the work [1]. In this work a complete setup to break ASIC implementations of standard Trivium stream cipher was presented. The setup allows to recover the secret keys combining the use of the active noninvasive technique attack of clock manipulation and Differential Fault Analysis (DFA) cryptanalysis. The attack system is able to inject transient faults into the Trivium in a clock cycle and sample the faulty output. Then, the internal state of the Trivium is recovered using the DFA cryptanalysis through the comparison between the correct and the faulty outputs. The secret key of the Trivium were recovered experimentally in 100% of the attempts, considering a real scenario and minimum assumptions.
[1] F.E. Potestad-Ordoñez, M. Valencia-Barrero, C. Baena-Oliva, P. Parra-Fernández, C.J. Jiménez-Fernández, "Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA". In Sensors, vol. 20, num. 6909, pp. 1-19, 2020.
Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
E. Tena-Sánchez, F.E. Potestad-Ordoñez, V. Zúñiga-González, C. Fernández-García, J.M. Mora Gutiérrez, C.J. Jiménez-Fernández and A.J. Acosta-Jiménez
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
abstract
In this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of proposals have been presented to design circuits resistant to Power Analysis attacks. In this paper a deep review of the state of the art of gate-level countermeasures against Power Analysis attacks has been done, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison.
[1] E. Tena-Sánchez, F.E. Potestad-Ordoñez, C.J. Jiménez-Fernández, A.J. Acosta and R. Chaves, "Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks," Applied Sciences, 12(5), 2390, 2022.
Adaptación de prácticas de laboratorios de Electrónica y Automatización a una modalidad semipresencial
E. Tena-Sánchez, F.E. Potestad-Ordóñez, M. Valencia-Barrero, A.J. Acosta and C.J. Jiménez-Fernández
Conference · Congreso Universitario de Innovación Educativa en las Enseñanzas Técnicas CUIEET 2021
abstract
En el curso 20/21, debido a la situación de pandemia mundial, tanto las clases teóricas como las prácticas sufrieron importantes cambios, además de los que se seguirán adoptando en próximos años. En este trabajo se exponen los problemas observados en las clases de laboratorio, más concretamente en la adecuación de los laboratorios de electrónica y automatización, donde el equipamiento y la capacidad ya eran limitados y se han agravado drásticamente por el problema de no poder juntar dos alumnos por puesto. Esto implica dividir el grupo en subgrupos, y plantear nuevos modelos didácticos adaptados a esta situación.
Learning VHDL through teamwork FPGA game design
C.J. Jimenez-Fernandez, C. Baena-Oliva, P. Parra-Fernandez, A. Gallardo-Soto, F.E Potestad-Ordoñez and M. Valencia-Barrero
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2020
abstract
The learning of digital design at the RT level by the students improves with practical work, which can be developed in teams, allow both the gradual advance of complexity as the learning progresses, and the proposal to be attractive to them, such as playing simple games. FPGAs and development boards offer a very suitable platform for the implementation of these designs. This paper presents a work in the Advanced Digital Design course (4th year of the Degree) consisting of the construction of a slightly adapted version of the game "Simon Says" in which the player must memorize a sequence that becomes more difficult for as levels pass. The work, which occupies the second half of the semester, is carried out by teams of three students and must have a demonstrator implemented on a Digilent Nexys4-DDR board.
Hamming-Code Based Fault Detection Design Methodology for Block Ciphers
F E. Potestad-Ordóñez, E. Tena-Sánchez, R. Chaves, M. Valencia-Barrero, A.J. Acosta-Jiménez and C.J. Jiménez-Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
abstract
Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to minimize this type of vulnerabilities, several mechanisms have been proposed to detect this type of attacks. However, these mechanisms can have a significant cost or not adequately cover the implementations against fault attacks. In this paper a novel approach is proposed, consisting in generating the signatures of the internal state using a Hamming code. This allows to cover a larger amount of faults allowing to detect even or odd bit changes, as well as multi-bit and multi-byte changes, the ones that make ciphers more vulnerable to DFA attacks. As case of study, this approach has been applied to the Advanced Encryption Standard (AES) block cipher implemented on FPGA using T-boxes. The results suggest a higher fault coverage with an overhead of 16% of resource consumption and without any penalty in the frequency degradation.
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, M. Valencia-Barrero, C. Baena and P. Parra
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2018
abstract
The fault injection in ciphers operation is a very successful mechanism to attack them. The inclusion of elements of protection against this kind of attacks is more and more necessary. These mechanisms are usually based on introducing redundancy, which leads to a greater consumption of resources or a longer processing time. This article presents how the introduction of placement restrictions on ciphers can make it difficult to inject faults by altering the clock signal. It is therefore a countermeasure that neither increases the consumption of resources nor the processing time. This mechanism has been tested on FPGA implementations of the Trivium cipher. Several tests have been performed on a Spartan 3E device from Xilinx and the experimental measurements have been carried out with ChipScope Pro. The tests showed that an adequate floorplanning is a good countermeasure against these kind of attacks.
FPGA design example for maximum operating frequency measurements
C.J. Jiménez-Fernandez, P. Parra-Fernandez, C. Baena-Oliva, M.Valencia-Barrero and F.E. Potestad-Ordoñez
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2018
abstract
The best way to learn how to design digital systems at the RT level is to use practical examples. In addition, from a teaching point of view, the more practical they are, the more attractive to students. But for a design to be attractive, even if it is presented with a low complexity, it is not possible to do it in a single practice session. This paper presents, as a demonstrator, the design at RT level and its implementation in FPGA of a digital system that uses the Trivium flow cipher and on which measurements of maximum operating frequency are made. This circuit is designed in three laboratory sessions of about two hours each.
Distance measurement as a practical example of FPGA design
C.J. Jiménez-Fernandez, P. Parra-Fernandez, C. Baena-Oliva, M.Valencia-Barrero and F.E. Potestad-Ordoñez
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2018
abstract
Digital design learning at the RT level requires practical examples and as learning progresses, the examples need to become more complex. FPGAs and development boards offer a very suitable platform for the implementation of these designs. However, classroom practice sessions usually last two hours, which does not allow the complexity of the designs be high enough. For this reason, interesting designs that can be made in several sessions are required In this paper, the construction of a distance measuring system is presented as a demonstrator. For this purpose, a distance measurement module based on ultrasound is available and the results are displayed in 7-segment displays on a Nexys4 board.
Creación de carteles autoexplicativos para laboratorios de electrónica
C.J. Jiménez, C. Baena and M. Valencia
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
abstract
Se presenta un proyecto cuyo objetivo ha sido la creación de carteles que, a modo de tutoriales resumidos, muestran de forma muy visual las tareas básicas a realizar en los laboratorios de electrónica. Están dirigidos a alumnos de asignaturas y titulaciones diversas. Se ha elegido la técnica de carteles por ser un medio muy amigable de refrescar informaciones, permitir contenidos altamente autoexplicativos y tener un coste razonablemente bajo. Se han creado ocho carteles que recogen desde el manejo del instrumental hasta la solución de errores comunes, pasando por la verificación y por la realización adecuada de montajes y medidas.
Aplicaciones docentes del diseño de un picoprocesador
C.J. Jiménez, C. Baena, P. Parra and M. Valencia
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
abstract
El conocimiento de la estructura interna y del mecanismo de funcionamiento de microprocesadores es una parte muy importante en la formación de ingenieros en electrónica e informática. Este conocimiento puede profundizarse con experiencias de diseño de procesadores, que reúnen además muchos aspectos vinculados a otros conocimientos básicos. Sin embargo, debido a su complejidad, el diseño de procesadores comerciales no es efectivo desde un punto de vista docente. En la presente comunicación presentamos una experiencia de diseño en VHDL de un procesador muy sencillo que demuestra los múltiples aprendizajes que suponen para el alumno.
Fault Injection on FPGA implementations of Trivium Stream Cipher using Clock Attacks
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Conference · Workshop on Trustworthy Manufacturing and Utilization of Secure Devices TRUDEVICE 2016
abstract
Nowadays the security of cryptographic circuits is threatened not only by attacks on the algorithm, but also
by attacks on the circuit implementation. They are the so-called side channel attacks and within such attacks
are the Active Fault Analysis attacks. In literature, there are reported some vulnerability analysis of the
Trivium stream cipher against Active Fault Analysis attacks using Differential Fault Analysis (DFA) [1][2].
The DFA technique is a side channel attack in which an attacker is able to inject a fault into the encryption or
decryption process, thus retrieving the secret information. For the Trivium cypher, a fault is injected into the
inner state. These works shown that if an attacker is able to inject only one fault in the inner state of the
Trivium, the key could be retrieved, but none of them checks its feasibility on a specific hardware
implementation. In this paper, it is presented an experimental analysis about the behaviour of FPGA
implementations of Trivium ciphers against fault injection through the variation of the clock signal. In
addition, it is made a comparative analysis between the experimental results obtained after the attack, and the
expected results obtained by the simulation and timing analysis, that is, the fault positions of the Trivium inner
state obtained experimentally and the fault positions expected by the timing analysis. This analysis was
presented in [3] and results show the vulnerabilities of these implementations and the impossibility of
determining the fault injections through simulation.
Experimental and Timing Analysis Comparison of FPGA Trivium Implementations Against Clock Fault Injection
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
abstract
The security of cryptocircuits is today threatened not only by attacks on algorithms but also, and above all, by attacks on the circuit implementations themselves. These are known as side channel attacks. One variety is the Active Fault Analysis attack, that can make a circuit vulnerable by changing its behavior in a certain way. This article presents an experimental fault insertion attack on an FPGA implementation of the Trivium stream cipher. It also compares the faults introduced with the faults expected after a timing analysis. The results show that this implementation is vulnerable to such attacks, and also that it is not possible to estimate the position of the inserted faults by means of timing analysis.
Fault Attack on FPGA Implementations of Trivium Stream Cipher
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
abstract
This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the number of faults introduced and its position in the inner state. The results obtained demonstrate the vulnerability of these implementations against fault attacks. As far as we know, this is the first time that experimental results of fault attack over Trivium are presented.
Low power implementation of Trivium stream cipher
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández, E. Potestad and M. Valencia-Barrero
Conference · Workshop on Cryptographic Hardware and Embedded Systems CHES 2015
abstract
Trivium is a synchronous stream cipher designed to generate up to 264 bits of key stream from an 80-bit secret key and an 80-bit initialization vector (IV). The architecture of this cipher is based on a 288-bit cyclic shift register accompanied by an array of combinational logic (AND, OR and XOR) to provide its feedback. The key stream generation consists mainly on an iterative process which updates some bits in the state register with logic operations to generate one bit of key stream.
A message transmission system with lightweight encryption as a project in a Master subject
C.J. Jiménez, C. Baena, M. Valencia, J.M. Fernández and A. Moreno
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2014
abstract
Master subjects should ideally be very practical, to allow students to apply the knowledge they have acquired to the solving of specific problems. This paper proposes the design of a secure communications system using an SPI bus as a Master subject. The system designed uses a stream cipher to encrypt and decrypt data and allows transmission of random length messages. It also uses CRCs to check message integrity.
Low power implementation of Trivium stream cipher
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and Valencia-Barrero
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2012
abstract
This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The design was simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. The aim of this paper is to evaluate the suitability of this technique and compare the power consumption and the core area of the low power and standard implementations. The results show that the application of the technique reduces power consumption by more than 20% with only a slight penalty in area and operating frequency.
Diseño e implementación de multiplicadores de Montgomery en FPGAs
G. Sassaw-Teshome, C.J. Jiménez-Fernández and M. Valencia-Barrero
Conference · Taller sobre Hardware Reconfigurable THR 2012
abstract
La multiplicación modular es la operación clave en sistemas de cifrado basados en clave pública,
como RSA y curvas elípticas (ECC). Las implementaciones hardware de altas presentaciones de
criptoprocesadores RSA y EEC utilizan el algoritmo de Montgomery para llevar a cabo la
multiplicación modular, ya que con este algoritmo se realiza la multiplicación modular sin tener que
realizar la operación de división. El objetivo principal de este artículo es explorar las prestaciones de
varias estructuras que utilizan versiones modificadas del algoritmo de Montgomery para
implementaciones de alta velocidad. Presentamos multiplicadores con el algoritmo de Montgomery
con sumadores con ahorro de acarreo (CSA) y con diferentes bases, incluyendo esquemas con
recodificación de Booth. Las implementaciones llevadas a cabo en este trabajo simplifican la
generación de los productos parciales evitando almacenar en memoria los valores del producto parcial
que no se consiguen con desplazamiento de registros. Los resultados muestran que las estructuras de
alta base son mejores para aplicaciones de alta velocidad.
Reflexión sobre los contenidos que cubran la competencia "Conocimientos de los fundamentos de la Electrónica" en los títulos de Grado de Ingeniería Industrial
C.J. Jiménez-Fernández, G. Miró, C. León and A. López
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2012
abstract
pdf
En el desarrollo de los títulos de grado de Ingeniería Industrial aparecen un conjunto de competencias (básicas y comunes) que deben ser adquiridas por los alumnos que cursen cualquiera de sus cinco titulaciones. En esta comunicación se presenta una reflexión sobre los contenidos que debe presentar la asignatura que cubra la competencia ¿Conocimientos de los fundamentos de la Electrónica¿, analizando los contenidos de las asignaturas que desarrollan esta competencia en algunas de las universidades de España y presentando con detalle la asignatura que la desarrolla en la Escuela Politécnica Superior de la Universidad de Sevilla.
Reflections on content to be included in the "Basic Electronics" proficiency of Industrial Engineering degrees
C.J. Jiménez-Fernández, G. Miró, C. León and A. López
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2012
abstract
Industrial Engineering degree course syllabuses include a series of basic, common skills which must be acquired by those studying for any of the five qualifications that can be obtained in the subject. This paper presents a reflection on the content which should be included in the subject that cover the proficiency "Basic Electronics", analysing the content of the subjects taught to develop skills in this field in some Spanish universities and detailing the subject content offered by the "Escuela Politécnica Superior" (Advanced Polytechnic School) at the University of Seville. © 2012 IEEE.
Montaje de un amplificador de audio en las prácticas de electrónica analógica
C.J. Jiménez, A. López, C. León and M. Valencia
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2012
abstract
pdf
En esta comunicación se presenta el rediseño de las prácticas de laboratorio de la asignatura Electrónica Analógica con el objetivo de que el alumno monte un sistema de mediana complejidad. Estas prácticas son obligatorias y se realizan en sesiones de dos horas, por lo que el sistema ha de cumplir con las características de que sea modular y cubra gran parte de los contenidos de la asignatura. La asignatura Electrónica Analógica se imparte en el segundo curso de la titulación de Ingeniería Técnica Industrial, especialidad de Electrónica Industrial.
Metodologia orientada a la elección de FPGAs con prioridad en el consumo de potencia
J.M. Mora-Gutierrez, G. Sassaw-Teshome, C.J. Jiménez-Fernández and M.Valencia-Barrero
Conference · Iberchip XVI Workshop IWS 2010
abstract
pdf
En este trabajo se presenta una metodología de diseño orientada a explorar el cada vez más amplio conjunto de FPGAs con el fin de seleccionar la mejor opción. Los parámetros que se utilizan para realizar la exploración son los recursos consumidos, la frecuencia de operación y el consumo de potencia. Sobre este último parámetro, el más difícil de medir, se hace un especial énfasis. Se exploran dos fabricantes (Altera y Xilinx), dos familias diferentes de cada fabricante y dos subfamilias dentro de cada familia, una de la gama alta y otra de la gama baja. Esta exploración se ha realizado implementando dos circuitos que realizan la operación división de números de 64 bits usando dos algoritmos con plena vigencia.
Influencia de la caracterización en el flujo de diseño de circuitos CMOS nanometricos
G. Sassaw, C.J. Jiménez and M. Valencia
Conference · Iberchip XVI Workshop IWS 2010
abstract
Abstract not avaliable
High radix implementation of montgomery multipliers with CSA
G. Sassaw, C.J. Jiménez and M. Valencia
Conference · International Conference on Microelectronics ICM 2010
abstract
Modular multiplication is the key operation in systems based on public key encryption, both for RSA and elliptic curve (ECC) systems. High performance hardware implementations of RSA and ECC systems use the Montgomery algorithm for modular multiplication, since it allows results to be obtained without performing the division operation. The aim of this article is to explore various modified structures of the Montgomery algorithm for high speed implementation. We present the implementation of a modified Montgomery algorithm with CSA and with different radix. In order to optimize the implementation regarding operation speed, we considered carry save adders structures and the Booth recoding scheme. The structure used in this paper simplifies the computation of the partial products avoiding the use of memories to store pre-calculated data for partial products which cannot be achieved by the shifting operation. The result shows that high-radix implementations are better for high speed applications.
HEAPAN: Diseño y evaluación de arquitecturas ILP
D. Peñalosa, C.J. Jiménez and M. Valencia
Conference · II Simposio Internacional de Computación y Electrónica 2009
abstract
En la actualidad, los procesadores ASIP (Application-
Specific Instrucction set Processors) se utilizan
en el diseño de sistemas orientados a una aplicación
específica, debido a su flexibilidad y eficiencia.
Una forma de hacer estos computadores es
mediante el uso de herramientas ADL's (Architectures
Design Languages).
En este artículo presentaremos una herramienta
ADL llamada HEAPAN, la cual está especializada
en la resolución de conflictos que se dan en las
arquitecturas ILP (Instruction Level Processors).
Para ello, esta herramienta utiliza técnicas hardware
y planificaciones dinámicas a la hora de ejecutar
las instrucciones. HEAPAN puede simular, sintetizar
y evaluar arquitecturas de forma fácil y flexible.
Con el fin de mostrar las capacidades de esta
herramienta, hemos diseñado, simulado y evaluado
dos arquitecturas ILP.
Estudio comparativo de los divisores en la tecnología nanométrica CMOS
G. Sassaw, C.J. Jiménez, J.M. Mora and M. Valencia
Conference · II Simposio Internacional de Computación y Electrónica 2009
abstract
pdf
Son varios los algoritmos de divisores propuestos para su realización en hardware, sin que haya un 'mejor divisor'. La búsqueda de un diseño óptimo para cada aplicación específica hace que sea indispensable la investigación de los algoritmos existentes a medida que se produce el avance de la tecnología. En este trabajo se presentan los resultados de la caracterización en área, tiempo y consumo de potencia de varias implementaciones de divisores en tecnologías CMOS nanométricas de 90 y 65 nm. Para la implementación se ha utilizado el flujo de diseño ASIC semicustom con elección entre tres voltajes de umbrales.
Partitioning and characterization of high speed adder structures in deep-submicron technologies
A. Estrada, G. Sassaw, C.J. Jiménez and M. Valencia
Conference · Conference on VLSI Circuits and Systems III, 2007
abstract
The availability of higher performance (in area, time and power consumption) and greater precision binary adders is a constant requirement in digital systems. Consequently, the design and characterization of adders and, most of all, their adaptation to the requisites of present-day deep-submicron technologies, are today still issues of concern. The binary adder structures in deep-submicron technologies must be revised to achieve the best balance between the number of bits in the adder and its delay, area and power consumption. It is therefore very important to make an effort to carefully optimize adder structures, thus obtaining improvements in digital systems. This communication presents the optimization of adder structures for implementations in deep-submicron technologies through their partitioning into blocks. This partitioning consists of dividing the number of input bits to the adder into several subsets of bits that will constitute the inputs to several adder structures of the same. or of different types. The structures used to accomplish this study range from the more traditional types, such as the carry look ahead adder, the ripple carry adder or the carry select adder, to more innovative kinds, like the parallel prefix adders of the type proposed by Brent-Kung, Han-Carlson, Kogge-Stone or Ladner-Fischer. The analyses carried out allow the characterization of structures implemented in deep-submicron technologies for area, delay and power consumption parameters.
A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies
A. Estrada, C.J. Jiménez and M. Valencia
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract
Integration technologies have favored the design and implementation of more complex circuits. Thanks to this increased complexity, these circuits are capable of implementing algorithms which a few years ago were too expensive in both area and computational resources. However, they now offer interesting choices which should be considered. This new generation of integrated circuits nevertheless presents other kinds of restrictions that the designer should bear in mind. Parameters such as frequency of operation or power consumption are new restrictions that the designer has to deal with in order to fulfill the conditions established by the circuit functionality. Finally, the shrinking integration scale of current technologies makes the timing behavior of the design differ from previous technologies. Thus, a review of the timing behavior of the digital circuit should be done. So far, arithmetic circuits have been used as a benchmark for the analysis and design procedures of digital circuits. Therefore, it is our goal now to analyze both conventional and modem arithmetic circuits structures for different deep-submicron technologies. To achieve this goal, a good solution is to characterize a set of algorithmic circuits for several deep submicron processes, so that the designer can select the most suitable one depending upon the intended application and existing restrictions. In this paper, the first steps to attain such selection are presented. In particular, we propose a design and VHDL characterization methodology based on an RTL description of each component, on the utilization of an automated synthesis tool, and on the generation of logic characteristics from the logic level. This methodology is applied to a set of adders structures, the results of which are also presented.
Implementación sobre FPGAs de sistemas difusos programables
S. Sánchez-Solano, A. Cabrera, C.J. Jiménez, P. Brox, I. Baturone and A. Barriga
Conference · Workshop IBERCHIP 2003
abstract
El número de aplicaciones electrónicas que utilizan soluciones basadas en lógica difusa se ha incrementado considerablemente en los últimos años y, de forma paralela, se han desarrollado nuevas herramientas de CAD que contemplan diferentes técnicas de implementación para este tipo de sistemas. De entre ellas, el uso de arquitecturas específicas de procesado implementadas sobre FPGAs presenta como principales ventajas una buena relación 'coste-rendimiento' y un ciclo de desarrollo aceptablemente corto. En esta comunicación se analizan las distintas facilidades de síntesis que proporciona el entorno de diseño Xfuzzy para la implementación de sistemas difusos programables que aprovechen los recursos disponibles en las actuales familias de FPGAs.
Hardware/Software Codesign Methodology for Fuzzy Controller Implementation
A. Cabrera, S. Sánchez-Solano, R. Senhadji, A. Barriga, C.J. Jiménez-Fernández
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2002
abstract
pdf
This paper describes a HW/SW codesign methodology for the implementation of fuzzy controllers on a platform composed by a general-purpose microcontroller and specific processing elements implemented on FPGAs or ASICs. The different phases of the methodology, as well as the CAD tools used in each design stage, are presented, with emphasis on the fuzzy system development environment Xfuzzy. Also included is a practical application of the described methodology for the development of a fuzzy controller for a dosage system.
Development of level controllers based on fuzzy logic
A. Cabrera, R. Senhadji, S. Sánchez-Solano, A. Barriga, C.J. Jiménez-Fernández and O. Llanes
Conference · International ICSC-NAISO Congress on Neuro-Fuzzy Technologies NF 2002
abstract
pdf
This paper describes the development of different kinds of level controllers based on fuzzy logic. Designs and implementations were carried out using tools from xfuzzy, a development environment that eases the different stages in the design of fuzzy inference systems. Special emphasis has been put in the on-line verification of the controller over a physical plant by means of xflab tool. Different approaches of the knowledge base were tested using xflab. Then, the results were analyzed and selected those that gave the better performance. Controllers implementations with different number of bit for input/output resolution were also carried out and analyzed. The results provide a base for the incoming development of a hardware fuzzy logic controller by means of specific hardware or by an embedded codesign system.
Herramientas de CAD para la síntesis de sistemas de interferencia difusos mediante FPGAs
S. Sánchez-Solano, A. Cabrera, C.J. Jiménez Fernández and D.R. López
Conference · V Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2002
abstract
pdf
En esta comunicación se describe un flujo de diseño que permite automatizar el proceso de síntesis sobre FPGAs de sistemas de inferencia basados en lógica difusa. El entorno de CAD utilizado combina herramientas específicas desarrolladas por los autores con versiones educativas de herramientas comerciales de diseño de sistemas digitales. Todas las herramientas pueden ser ejecutadas sobre entornos MS-Windows, lo que facilita su utilización en aulas informáticas.
Prototyping of fuzzy logic-based controllers using standard FPGA development boards
S. Sánchez-Solano, R. Senhadji, A. Cabrera, I. Baturone, C.J. Jiménez and A. Barriga
Conference · IEEE International Workshop on Rapid System Prototyping RSP 2002
abstract
pdf
This paper describes a design methodology for fuzzy logic-based control systems. The methodology employs hardware/software codesign techniques according to an 'a priori' partition of the tasks assigned to the selected components. This feature makes it possible to tackle the control system prototyping as one of the design stages. In our case, the platform considered for prototyping has been a development board containing a standard microcontroller and an FPGA. Experimental results from an actual control application validate the efficiency of this methodology.
Books
No results
Book Chapters
Logic synthesis
A. Barriga-Barros, C.J. Jiménez-Fernández and M. Valencia-Barrero
Book Chapter · Encyclopedia of Computer Science and Engineering, pp 1753-1762, 2009
abstract
doi
This article addresses logic synthesis, which involves the generation of a circuit at the logic level based on an RT level design specification. The article deals with aspects associated with logic design such as data types, system components, and modes of operation. The hardware description languages will be presented as tools to specify digital systems. Two standard languages (VHDL and Verilog) will be examined in detail, and the use of VHDL for automatic synthesis will be explained to illustrate specific aspects of logic synthesis descriptions. The article ends with an illustrative example of the principal concepts discussed.
Formación de profesores noveles en tecnología electrónica: una primera aproximación
J. Barbancho-Concejero, D. Guerrero-Martos, C.J. Jiménez-Fernández and M. Valencia-Barrero
Book Chapter · La Formación del Profesorado Universitario: Programa de Equipos Docentes de la Universidad de Sevilla Curso 2003-2004, pp 75-84, 2005
abstract
Abstract not available
Other publications
No results
