Found results matching for:
Author: Manuel Delgado Restituto
Year: Since 2002
Journal Papers
A high-voltage floating level shifter for a multi-stage charge-pump in a standard 1.8 V/3.3 V CMOS process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 156, article 154389, 2022
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This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The proposed circuit has been used in a multi-stage charge pump for programming its voltage conversion ratio. Experimental results show that the level shifters successfully enable/disable the stages of the charge pump, thus modifying its output voltage between 5.35 V and 12.4 V for an output current of 3 mA.
A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · Sensors, vol. 22, no. 17, article 6429, 2022
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This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm(2). Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode-tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology's nominal supply, (2) residual charge-without passive discharging phase-was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.
A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System
N. Perez-Prieto, A. Rodriguez-Vazquez, M. Alvarez-Dolado and M. Delgado-Restituto
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 15, no. 5, pp 960-977, 2021
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This paper presents a high dynamic range, lowpower, low-noise mixed-signal front-end for the recording of local field potentials or electroencephalographic signals with invasive neural implants. It features time-multiplexing of 32 channels at the electrode interface for area saving and offers the ability to spatially delta encode signals to take advantage of the large correlations between nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information, thus effectively increasing the dynamic range of the system while avoiding the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro and shows an integrated input-referred noise in the 0.5200 Hz band of 1.4 Vrms for a spot noise of about 85 nV/Hz. The system draws 1.5 W per channel from 1.2 V supply and obtains 71 dB + 26 dB (with artifact compression) dynamic range, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios.
Recording Strategies for High Channel Count, Densely Spaced Microelectrode Arrays
N. Pérez-Prieto and M. Delgado-Restituto
Journal Paper · Frontiers in Neuroscience, vol. 15, article 681085, 2021
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Neuroscience research into how complex brain functions are implemented at an extra-cellular level requires in vivo neural recording interfaces, including microelectrodes and read-out circuitry, with increased observability and spatial resolution. The trend in neural recording interfaces toward employing high-channel-count probes or 2D microelectrodes arrays with densely spaced recording sites for recording large neuronal populations makes it harder to save on resources. The low-noise, low-power requirement specifications of the analog front-end usually requires large silicon occupation, making the problem even more challenging. One common approach to alleviating this consumption area burden relies on time-division multiplexing techniques in which read-out electronics are shared, either partially or totally, between channels while preserving the spatial and temporal resolution of the recordings. In this approach, shared elements have to operate over a shorter time slot per channel and active area is thus traded off against larger operating frequencies and signal bandwidths. As a result, power consumption is only mildly affected, although other performance metrics such as in-band noise or crosstalk may be degraded, particularly if the whole read-out circuit is multiplexed at the analog front-end input. In this article, we review the different implementation alternatives reported for time-division multiplexing neural recording systems, analyze their advantages and drawbacks, and suggest strategies for improving performance.
Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction
R. Fiorelli, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 3, pp 606-619,2020
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This paper presents a SAR converter based mixed-signal multiplier for the feature extraction of neural signals using quadratic operators. After a thorough analysis of design principles and circuit-level aspects, the proposed architecture is explored for the implementation of two quadratic operators often used for the characterization of neural activity, the moving average energy (MAE) operator and the nonlinear energy operator (NEO). Programmable chips for both operators have been implemented in a HV-180 nm CMOS process. Experimental results confirm their suitability for energy computation and action potential detection and the accomplished area×power performance is compared to prior art. The MAE and NEO prototypes, at a sampling rate of 30kS/s, consume 116 nW and 178 nW, respectively, and digitize both the input neural signal and the operator outcome, with no need for digital multipliers.
A Sub-µW Reconfigurable Front-End for Invasive Neural Recording that Exploits the Spectral Characteristics of the Wideband Neural Signal
J.L. Valtierra, M. Delgado-Restituto, R. Fiorelli and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp 1426-1437, 2020
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This paper presents a sub- µW ac-coupled reconfigurable front-end for invasive wideband neural signal recording. The proposed topology embeds filtering capabilities enabling the selection of different frequency bands inside the neural signal spectrum. Power consumption is optimized by defining specific noise targets for each sub-band. These targets take into account the spectral characteristics of wideband neural signals: local field potentials (LFP) exhibit l/f(x) magnitude scaling while action potentials (AP) show uniform magnitude across frequency. Additionally, noise targets also consider electrode noise and the spectral distribution of noise sources in the circuit. An experimentally verified prototype designed in a standard 180 nm CMOS process draws 815 nW from a 1 V supply. The front-end is able to select among four different frequency bands (modes) up to 5 kHz. The measured input-referred spot-noise at 500 Hz in the LFP mode (1 Hz - 700 Hz) is 55 nV/root Hz while the integrated noise in the AP mode (200 Hz - 5 kHz) is 4.1 µVrms. The proposed front-end achieves sub-µW operation without penalizing other specifications such as input swing, common-mode or power-supply rejection ratios. It reduces the power consumption of neural front-ends with spectral selectivity by 6.1x and, compared with conventional wideband front-ends, it obtains a reduction of 2.5x.
A comparative study of stacked-diode configurations operating in the photovoltaic region
R. Gómez-Merchán, D. Palomeque-Mangut, J.A. Leñero-Bardallo, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Sensors Journal, vol. 20, no. 16, pp 9105-9113, 2020
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This article presents a detailed comparative analysis of two possible stacked-diode configurations operating as solar cells. The performance of a single p-well - deep n-well diode is compared with the combination of such diode with a n-diff - pwell diode in parallel. Both configurations occupy the same area but offer different performance and, accordingly, they can have different application scopes. A test circuit to gauge the diodes performance and their spectral sensitivity has been integrated along with the two diode configurations in a 0.18 μm CMOS standard fabrication technology. The measured experimental results for the two diode configurations under study are validated with an analytical diode physical model.
Offset-calibration with time-domain comparators using inversion-mode varactors
R. Fiorelli, M. Delgado-Restituto and A Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Brief, vol. 67, no. 1, pp 47-51, 2020
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This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit SAR-ADC. The design, fabricated in a 0.18μm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.
Phase Synchronization Operator for on-chip Brain Functional Connectivity Computation
M. Delgado-Restituto, J.B. Romaine and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 5, pp 957-970, 2019
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This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters and adders. The processor, fabricated in a 0.18μm CMOS process, only occupies and consumes 15nW from a 0.5V supply voltage at a signal input rate of 1024S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.
Asynchronous spiking pixel with programmable sensitivity to illumination
J.A. Leñero-Bardallo, M. Delgado-Restituto, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp 3854-3863, 2018
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A spiking pixel to be used in image sensor arrays for asynchronous frame-based operation is presented. The pixel features both local and global adaptive sensitivity to the illumination level. Local adaptation is performed by adjusting the voltage stored in an embedded analog memory according to the average illumination within a neighborhood. Global adaptation to the overall illumination of the array is implemented by adjusting a voltage value common to all the pixels. These programming capabilities allow full control on the sensor sensitivity, pixel output data flow, and energy consumption, thus, overcoming the limitations observed in current image sensors based on spiking pixels. Experimental results validate the functionality of the proposal.
Highly Scalable Real Time Epilepsy Diagnosis Architecture Via Phase Correlation
J.B. Romaine, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · Procedia Technology, vol. 27, pp 55-56, 2017
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Epilepsy is at current the world´s second most common neurological disorder affecting an estimated 50 million people. While up to 70% of epileptic suffers are treated successfully with epileptic medication some 30% continue to suffer untreated. This gap could be filled by the implementation of implantable neural prostheses which are able to detect when a seizure is coming and eventually actuate in the brain to stop its progression.
Guest Editorial: Special Issue on Selected Papers From IEEE BioCAS 2016
M. Delgado-Restituto, P. Mohseni and J. Ohta
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 6, pp 1256-1257, 2017
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Abstract not avaliable
System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
M. Delgado-Restituto, A. Rodriguez-Perez, A. Darie, C. Soto-Sánchez, E. Fernandez-Jover and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 2, pp 420-433, 2017
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This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.
Enhanced Sensitivity of CMOS Image Sensors by Stacked Diodes
J.A. Lenero-Bardallo, M. Delgado-Restituto, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper · IEEE Sensors Journal, vol. 16, no. 23, pp 8448-8455, 2016
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We have investigated and compared the performance of photodiodes built with stacked p/n junctions operating in parallel versus conventional ones made with single p/n junctions. We propose a method to characterize and compare photodiodes sensitivity. For this purpose, a dedicated chip in the standard AMS 180-nm HV technology has been fabricated. Four different sensor structures were implemented and compared. Experimental results are provided. Measurements show sensitivity enhancement ranging from 55% to 70% within the 500-1100 nm spectral region. The larger increment is happening in the near infrared band (up to 62%). Such results make stacked photodiodes suitable candidates for the implementation of photosensors in vision chips designed for standard CMOS technologies.
A Low Noise Amplifier for Neural Spike Recording Interfaces
J. Ruiz-Amaya, A. Rodriguez-Perez and M. Delgado-Restituto
Journal Paper · Sensors, vol. 15, no. 10, pp 25313-25335, 2015
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This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz-7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.
A 515 nW, 0-18 dB Programmable Gain Analog-to-Digital Converter for In-Channel Neural Recording Interfaces
A. Rodriguez-Pérez, M. Delgado-Restituto and F. Medeiro
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 8, no. 3, pp 358-370, 2014
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This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter (PG-ADC) suitable for in-channel neural recording applications. The PG-ADC uses a novel implementation of the binary search algorithm that is complemented with adaptive biasing techniques for power saving. It has been fabricated in a standard CMOS 130 nm technology and only occupies 0.0326mm2. The PG-ADC has been optimized to operate under two different sampling modes, 27 kS/s and 90 kS/s. The former is tailored for raw data conversion of neural activity, whereas the latter is used for the on-the-fly feature extraction of neural spikes. Experimental results show that, under a voltage supply of 1.2 V, the PG-ADC obtains an ENOB of 7.56 bit (8-bit output) for both sampling modes, regardless of the gain setting. The amplification gain can be programmed from 0 to 18 dB. The power consumption of the PG-ADC at 90 kS/s is 1.52μW with a FoM of 89.49 fJ/conv, whereas at 27 kS/s it consumes 515 nW and obtains a FoM of 98.31 fJ/conv.
A 1.1-mW-RX -81.4 dBm sensitivity CMOS transceiver for bluetooth low energy
J. Masuch and M. Delgado-Restituto
Journal Paper · IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 4, pp 1660-1673, 2013
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This paper presents a fully integrated low-power 130-nm CMOS transceiver tailored to the Bluetooth low energy (BLE) standard. The receiver employs a passive front-end zero-IF architecture, which is directly driven by a quadrature voltage-controlled oscillator (QVCO) without any buffering stage. The QVCO, embedded in a fractional-N phase-locked loop (PLL), employs a passive RC network to cancel the parasitic magnetic coupling between the two cores so as to keep the quadrature phase error below 1.5°. The PLL exhibits a high loop bandwidth of 1 MHz to sufficiently reduce the frequency pulling effects due to close-by interferers. The transmitter uses a direct-modulation Gaussian frequency-shift keying scheme in which small PMOS-based cells modulate the output signal of one of the cores of the QVCO. In the baseband section, the transceiver employs a 4-bit phase-domain ADC based on novel linear-combiner topology to generate the required phase rotations. The proposed combiner operates in current domain and does not employ resistors, leading to a power- and area-efficient demodulator implementation. The complete receiver achieves a sensitivity of -81.4 dBm and fulfills the BLE requirements on interference blocking. It consumes 1.1 mW from a 1.0-V supply and has a similar power efficiency as recent super-regenerative receivers that are much more susceptible to interferers. The transmitter delivers 1.6-dBm output power to a differential 100 Ω and consumes 5.9 mW, which implies a total efficiency of 24.5%.
Co-integration of an RF energy harvester into a 2.4 GHz transceiver
J. Masuch, M. Delgado-Restituto, D. Milosevic and P. Baltus
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 48, no. 7, pp 1565-1574, 2013
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This paper presents an RF energy harvester embedded in a low-power transceiver (TRX) front-end. Both the harvester and the TRX use the same antenna and operate at the same frequency of 2.4GHz. To decouple the harvester from the TRX, different concepts are proposed regarding the transmitter (TX) and receiver (RX). To avoid loading the TX, the harvester is decoupled with an nMOS switch that can be enabled with a start-up rectifier. Concerning the RX, the decoupling mechanism relies on the nonlinear input impedance of the main RF-DC converter. The harvester also includes a supply management circuit for over-voltage protection and charging energy storage devices with a constant current or voltage. The energy harvester has been co-integrated with the low power TRX in a 130nm CMOS process and achieves a measured peak power conversion efficiency of 15.9%. For input power levels of at least -9dBm, it is able to charge up a supply capacitor to a regulated voltage of 1.34V. The impact of the harvester on the TRX performance is measured with respect to an identical TRX front-end without harvester, showing little impact on the TRX performance. Both TX output power and RX noise figure are degraded by less than 0.5dB. As an additional feature, the start-up rectifier is also used for demodulation of On-Off-Keying (OOK) signaling, which can be used as a secondary wake-up channel. Since the required area for the harvester is only 0.019mm2 (~2% of the total active TRX area), it can be added to the TRX at almost no cost.
Low-power quadrature generators for body area network applications
J. Masuch and M. Delgado-Restituto
Journal Paper · International Journal of Circuit Theory and Applications, vol. 41, no. 1, pp 33-43, 2013
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This paper presents different alternatives for the implementation of low-power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4-GHz frequency range. Both implementations have been designed in a 90-nm Complementary Metal-Oxide Semiconductor (CMOS) technology and operate at 1V of supply voltage. The first architecture uses a voltage-controlled oscillator (VCO) running at twice the desired output frequency followed by a divider-by-2 circuit. It experimentally consumes 335uW and achieves a phase noise of -110.2 dBc/Hz at 1MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210uW, and it obtains a phase noise of -111.9 dBc/Hz at 1MHz.
Impact of parasitics on even symmetric split-capacitor arrays
A. Rodríguez-Pérez, M. Delgado-Restituto and F. Medeiro
Journal Paper · International Journal of Circuit Theory and Applications, vol. 41, no. 9, pp 972-987, 2013
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This paper analyzes the impact of parasitic capacitances in the performance of split capacitive-based digital-to-analog converter arrays and presents a procedure for the optimal sizing of these structures for given linearity specifications. It also demonstrates that parasitics are often the main responsible for the nonlinear behavior of these arrays, particularly for low-to-medium resolution converters. In order to validate the analysis, two versions of a complete low-power, low-voltage successive-approximation register analog-to-digital converter (ADC), intended for a disposable multi-channel bio-medical monitoring system, have been fabricated in a 0.35um standard complementary metal-oxide-semiconductor technology. The only difference between these two prototypes is that in one of them, the capacitive array is surrounded by dummy capacitors, while in the other prototype is not. Hence, the former achieves better mismatch performance at the expense of increased parasitics. The experimental results demonstrate that the version without dummy capacitors obtains higher effective resolution than the ADC with dummies, the power consumption being essentially the same for both prototypes, namely: 130nW at 2kS/s from a 1-V supply. These results are in full agreement with the analysis reported in the paper and confirm the proposed sizing procedure. © 2012 John Wiley & Sons, Ltd.
A 190-μW zero-IF GFSK demodulator with a 4-b phase-domain ADC
J. Masuch and M. Delgado-Restituto
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 47, no. 11, pp 2796-2806, 2012
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This paper presents a zero-IF Gaussian frequency-shift keying (GFSK) demodulator based on a phase-domain analog-to-digital converter (Ph-ADC) which directly quantizes the phase information of the received complex baseband signal. The Ph-ADC linearly combines the in-phase and quadrature parts of the incoming signal, and the generated phase-shifted versions are fed to comparators to detect the zero-crossings and build a 4-b digital representation of the signal phase. Seeking for a low-area and low-power consumption realization, our proposal employs a resistor-less scheme which performs phase rotations in current domain. Together with the Ph-ADC, the fully integrated GFSK demodulator also includes a channel-filtering programmable gain amplifier and a symbol decision block. Altogether, the demodulator occupies 0.14 mm 2 in a 0.13-μm CMOS technology with a total power consumption of 190 μW from a 1-V supply. For a data rate of 1 Mbps and 0.5 modulation depth, the GFSK demodulator requires an E B/N 0 of 14.8 dB for a bit error rate of 0.1% considering a flicker noise corner of 150 kHz, obtains a dynamic range of 74 dB, and is able to tolerate carrier frequency offsets of ±170 kHz. This performance safely complies with the requirements of the Bluetooth Low Energy (BLE) standard. © 2012 IEEE.
Behavioral modeling of pipeline ADC building blocks
J. Ruiz-Amaya, M. Delgado Restituto and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications vol. 40, no. 6, pp 571-594, 2012
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This paper presents accurate behavioral models for the basic building blocks of pipeline data converters with emphasis on the MDAC circuit. These models take into account major circuit-level non-idealities, including small- and large-signal effects, as well as the impact of switch-on resistance effects and thermal noise contributions. The behavioral models have been validated against transistor-level simulations under different scenarios, showing in all cases a worst-case deviation of 0.3 bit effective resolution. Copyright © 2011 John Wiley & Sons, Ltd.
A sub-10 nJ/b +1.9-dBm output power FSK transmitter for body area network applications
J. Masuch and M. Delgado-Restituto
Journal Paper · IEEE Transactions on Microwave Theory and Techniques, vol 60, no. 50, pp 1413-1423, 2012
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This paper presents a low-power frequency shift keying (FSK) transmitter using a direct voltage-controlled oscillator (VCO) modulation scheme integrated in a 0.13-μm CMOS technology. The carrier frequency is set with a finite-modulo fractional-N phase-locked loop (PLL) in order to achieve a low start-up time of 5.5 μs. The LC-based VCO is directly modulated using simple pMOS transistors to change the tank capacitance. Measurements verify that the carrier frequency and the frequency deviation meet the requirements of the Bluetooth low energy standard up to 85 °C even considering supply voltage variations of 1.0 V ± 10%. The FSK synthesizer only consumes 600 μW and drives a power amplifier (PA) with a differential class-E output stage. An integrated step-up transformer is used to up-convert the antenna impedance to a load impedance of 840 Ω seen by the PA. The overall transmitter consumes 8.9 mA and delivers +1.9 dBm to the antenna, which means a total power efficiency of 17.4%. © 2012 IEEE.
A low-power programmable neural spike detection channel with embedded calibration and data compression
A. Rodríguez-Pérez, J. Ruíz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 6, no. 2, pp 87-100, 2012
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This paper reports a programmable 400 um pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 uVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 uW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 uW when the feature extraction mode is enabled.
A 1.2V 10-bit 60-MS/s 23mW CMOS pipeline ADC with 0.67 pJ/conversion-step and on-chip reference voltages generator
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 71, no. 3, pp 371-381, 2012
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A 1.2 V 10-bit 60 MS/s pipeline Analog-to-Digital Converter (ADC), fabricated in a 130 nm CMOS technology, is presented. The prototype is composed by five 3-bit pipeline stages and a Sample and Hold (S&H) circuit at the front. Two-stage Miller-compensated Operational Transconductance Amplifiers (OTAs), offset-compensated comparators and bootstrapping sampling switches have been used due to the low voltage supply requirements. Special attention has been paid to the reduction of the power consumption using a thorough design methodology. The converter only consumes 23 mW including on-chip reference voltages and bias current generators. The differential and integral nonlinearity of the ADC are below 0.60 and 0.61 LSBs, respectively. The pipeline converter achieves an effective resolution above 9 bits along the Nyquist bandwidth, and obtains 0.67 pJ energy consumption per conversion, making it one of the most energy-efficient 10-bit video-rate pipeline ADC reported to date. © 2011 Springer Science+Business Media, LLC.
IC-constrained optimization of continuous-time Gm-C filters
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 40, no. 2, pp 127-143, 2012
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This paper presents an automated synthesis procedure for integrated continuous-time fully-differential Gm-C filters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB (R) framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright (C) 2010 John Wiley & Sons, Ltd.
An ultralow-power mixed-signal back end for passive sensor UHF RFID transponders
J.A. Rodríguez-Rodríguez, M. Delgado-Restituto, J. Masuch, A. Rodríguez-Pérez, E. Alarcón and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Industrial Electronics, vol. 59, no. 2, pp 1310-1322, 2012
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This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35-mu m CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 x 10(-3) with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 mu A from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply.
Inaugural Editorial
M. Delgado-Restituto
Journal Paper · IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 1, pp1-3, 2011
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Abstract not avaliable
Transistor-level synthesis of pipeline analog-to-digital converters using a design-space reduction algorithm
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 58, no. 12, pp 2816-2828, 2011
abstract
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A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 mu m CMOS 10 bits@ 60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@ 1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 mW@ 1.2 V and an effective resolution of 9.47-bit@ 1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.
Accurate settling-time modeling and design procedures for two-stage miller-compensated amplifiers for switched-capacitor circuits
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 6, pp 1077-1087, 2009
abstract
doi
We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.
Bridging technology innovations to foundations, special issue ECCTD 2007
M. Delgado-Restituto, E. Alarcon and A. Rodríguez-Vázquez (Guest Eds.)
Journal Paper · International Journal of Circuit Theory and Applications, vol. 37, no. 2, pp 159-161, 2009
abstract
doi pdf
Abstract not available
Matrix methods for the dynamic range optimization of continuous-time G(m)-C filters
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 55, no. 9, pp 2525-2538, 2008
abstract
doi
This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential G(m)-C filters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. Using these methods, an analytical technique for the dynamic range optimization of weakly nonlinear G(m)-C filters under power dissipation constraints is presented. The procedure is first explained for general filter structures and then illustrated with a simple biquadratic section.
Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+
R. del Río, J.M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 1, pp 47-62, 2004
abstract
doi pdf
We present a 90-dB spurious-free dynamic range sigma-delta modulator (E AM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-mum CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB14 b respectively. The SigmaDelta modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the SigmaDelta modulator.
A modem in CMOS technology for data communication on the low-voltage power line
O. Guerra, C.M. Domínguez-Matas, S. Escalera, J.M. García-González, G. Liñán, R. del Río, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · Integration, the VLSI Journal, vol. 36, no. 4, pp 229-236, 2003
abstract
doi
This paper presents a CMOS 0.8 mum mixed-signal half-duplex Modem ASIC for data transmission on the low-voltage power line. It includes all the analog circuitry needed for input interfacing and modulation/ demodulation (low-noise amplifier, PLL-based frequency synthesis, tunable filter banks, and decision circuitry), logic circuitry for control purposes, and an output amplifier used as front-end for an off-chip line driver. The chip demodulates signals down to 283muV(rms) (these are worst case values among 30 randomly-selected samples used as vehicles for detailed electrical characterization; most of the samples featured 200 muV(rms), sensitivity; bit error rate (BER) is below 0.5 x 10(-5)) at 10 kbps, and operates correctly in the whole industrial temperature range, from -45degreesC to 80degreesC, under 5% variations of the 5V supply voltage. This ASIC is now in commercial production. (C)2003 Published by Elsevier B.V.
Integrated chaos generators
M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · Proceedings of the IEEE, vol. 90, no. 5, pp 747-767, 2002
abstract
doi
This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.
Conferences
Experimental Validation of a High-Voltage Compliant Neural Stimulator Implemented in a Standard 1.8V/3.3V CMOS Process
D. Palomeque-Mangut, A. Rodríguez-Vázquez and M Delgado-Restituto
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2022
abstract
This paper describes a neural stimulator with 4 × VDD compliance voltage, delivering up to 2.08 mA, and implemented in a standard 180nm 1.8V/3.3V CMOS Process. The wide range of stimulation currents and high compliance voltage makes it suitable for stimulation applications both in rodents and mammals. Besides, it can be configured both as electrical and optical stimulator. Stacked transistor cells with dynamic gate biasing have been used for withstanding voltages well above the nominal supply. The system has been fabricated, occupying an active area of 2.34mm2. The circuit has been experimentally tested by connecting it to a custom μelectrode array which was immersed into a phosphate-buffered saline solution.
Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils
D. Palomeque-Mangut, A. Schmid, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2022
abstract
This paper proposes a system to transfer both mWpower and Mbps-data over an inductive link using a single pair of coils. The system is able to handle a wide range of loads by implementing a load adapter block that divides the operation into two phases: a Power Transfer Phase (PTP) and a Data Transfer Phase (DTP). On the one hand, during PTP, a constant amount of power is drawn from the inductive link, regardless of the current demanded by the load. On the other hand, during DTP, the load is powered with external capacitors, allowing the inductive link to be used for data transmission. With this architecture, intended to be used in a neural implant, power can be delivered to a wide range of loads without affecting the uplink/downlink data communication reliability and with no need of extra coils. Thus, the proposed solution permits minimizing the overall size of the neural implant. An electrical mixed-signal model of the system is described and implemented in MATLAB Simulink through Simscape Electrical and Stateflow toolboxes. Simulations performed on the electrical model of the system are shown and discussed.
A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process
D. Palomeque-Mangut, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2022
abstract
A high-voltage (HV) floating level shifter which slides digital signals by varying the low supply rail from ground to VSSH while preserving the input signal swing is proposed. The cell is based on a periodically-refreshed charge pump circuit and it is suitable for non-HV CMOS processes. Input signals can be non-periodic. The circuit has been designed and implemented in a standard 180nm 1.8V/3.3V CMOS node, occupying 0.02mm2. Post-layout simulations show that VSSH voltage can safely range from 0.5V to 9.5V. The delay response of the circuit is 1.9 ns and it consumes 13.9 μW.
Spatial Encoding Techniques in Time-Multiplexed Neural Recording Front-Ends
N. Pérez-Prieto, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · IEEE International New Circuits and Systems Conference NEWCAS 2021
abstract
This paper reviews two spatial encoding techniques for time-multiplexed recording front-ends. These techniques use bipolar and monopolar recordings, respectively, and are aimed to compress neural data taking advantage of the large spatial correlation of LFPs/ECoGs measured from nearby electrodes. The pros and cons of both architectures are analyzed and demonstrated with experimental results from a 32-channel time-multiplexed spatially-encoded neural front-end designed in 0.18 µm technology.
A High TCMRR, Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation
J.L. Valtierra, R. Fiorelli, N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2019
abstract
This paper describes a multichannel bidirectional front-end for true closed-loop neuromodulation. Stimulation artefacts are reduced via a 4-channel H-bridge current source sharing stimulators to minimize residual charge drops in the electrodes. The 4-channel sensing front-end is capable of multichannel sensing in the presence of artefacts as a result of its high total common-mode rejection ratio (TCMRR) that accounts for CMRR drop due to electrode mismatch. Experimental verification of a prototype fabricated in 180 nm process shows a stimulator front-end with 0.059% charge balance and 0.275 nA DC current error. The recording front-end consumes 3.24 μW, tolerates common-mode interference up to 1 Vpp and shows a TCMRR > 66 dB for 500 mVpp inputs.
A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression
N. Pérez-Prieto, R. Fiorelli, J.L. Valtierra, P. Pérez-García, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2019
abstract
This paper describes a low-noise, low-power and high dynamic range analog front-end intended for sensing neural signals. In order to reduce interface area, a 32-channel multiplexer is implemented on circuit input. Furthermore, a spatial delta encoding is proposed to compress the signal range. A differential artifact compression algorithm is implemented to avoid saturation in the signal path, thus enabling reconstruct or suppressing artifacts in digital domain. The proposed design has been implemented using 0.18 μm TSMC technology. Experimental results shows a power consumption per channel of 1.0 μW, an input referred noise of 1.1 μVrms regarding the bandwidth of interest and a dynamic range of 91 dB.
A sub-μVRMS chopper front-end for ECOG recording
N. Pérez-Prieto, J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2019
abstract
This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path to reduce noise and avoid the implementation of a ripple rejection loop. The prototype was designed in 0.18μm CMOS technology with a 1V supply. Post-layout simulations were carried out showing a power consumption below 2μW and an integrated input-referred noise of 0.75μVrms, with a noise floor below 50 nV/Hz, over a bandwidth from 1 to 200Hz, for a noise efficiency factor of 2.7.
Artifact-aware analogue/mixed-signal front-ends for neural recording applications
N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2019
abstract
This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog front-ends for neural recording applications. These techniques are employed for handling Common-Mode (CM) Differential-Mode (DM) artifacts and include techniques such as Average Template Subtraction, Channel Blanking or Blind Adaptive Stimulation Artifact Rejection (ASAR), among others. Additionally, a new technique for DM artifacts compression is proposed. It allows to compress these artifacts to the requirements of the analog front-end and, afterwards, it allows to reconstruct the whole artifact or largely suppress it.
A Sub- µW Reconfigurable Front-End for Invasive Neural Recording
J.L. Valtierra, R. Fiorelli, M. Delgado-Restituto and A. Rodriguez-Vazquez
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2019
abstract
This paper presents a sub-microwatt ac-coupled neural amplifier for the purpose of neural signal sensing. A proposed reconfigurable topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180nm CMOS process draws 803nW from a 1V source. The measured input-referred spot-noise at 150Hz is 130nV / Hz while the integrated noise in the 200Hz-5kHz band is 3.6µV rms.
Highly scalable real time epilepsy diagnosis architecture via phase correlation and functional brain maps
J.B. Romaine, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2018
abstract
The complexity of biomedical neural processing is evident, with vast amounts of data needing to be handled and processed in order to reveal possible biomarkers which may lead to the early diagnosis of certain neurological disorders. One disorder in particular is epilepsy, which is one of the most common neurological disorder in the world today.Our proposed solution is a highly efficient, scalable and low powered device for the diagnosis and verification of epilepsy via the identification of changes in synchronicity between interictal neural signal segments.
System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
M. Delgado-Restituto, A. Rodríguez-Pérez, A. Darie, A. Rodríguez-Vázquez, C. Soto-Sánchez and E. Fernández-Jover
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract
This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an autocalibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data stream coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.
Dynamic range considerations for neural recording channels
M. Delgado-Restituto
Conference · IEEE CAS Singapore Chapter Workshop, 2018
abstract
Neural readout microelectronic interfaces are essential in implanted central nerve system prostheses aimed for brain-machine interfaces, the amelioration of disease effects, or the development of robotic mechanisms for the restitution/rehabilitation of abilities lost after injury or disease. Neural signals which can be recorded and used as biomarkers of the brain activity include local field potentials (LFPs) and action potentials (APs). They exhibit small amplitude (typically, below 1mV for LFPs and 100V for APs) and narrow band characteristics (0.5-200Hz for LFPs and 200Hz-7kHz for APs). A priori, these signals can be easily digitized with low-to-medium resolution ADCs, thus paving the way for neural prostheses with small area and power consumptions. However, along with the biomarkers, strong in band artifacts, which can be much larger that the signals of interest, may contaminate the recording or even preclude it altogether if the front-end saturates. Different causes can be at the origin of artifacts; for instance, they can be motion related or generated by electrical stimulations close to the recording sites. Coping with these large artifacts would demand for high dynamic range (of about 75dB) front-ends and data converters with large effective resolutions (beyond 13-14 bits). However, recent proposals for ADC resolution reduction techniques have demonstrated that modest ADCs can still be used for neural recording even in the presence of artifacts. This work reviews these proposals and also presents state-of-the-art techniques for the suppression of differential and common-mode artifacts from neural recordings.
A Sub-μVrms Chopper-Stabilized Local Field Potential Amplifier
N. Pérez-Prieto, J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2017
abstract
This paper describes a low-noise, low-power and fully differential amplifier intended for sensing neural signals. In order to reduce 1/f noise, the amplifier is chopper-stabilized. To palliate the up-modulated dc offset due to chopper-stabilization, an integrator with programmable duty-cycled resistors is implemented. A switched-capacitor common-mode feedback and a low pass filter, carried out using subthreshold-source-follower biquad, guarantee lower power consumption and lower distortion on the circuit. Transistor-level simulations were realized in a prototype designed in a 0.18 μm AMS CMOS technology with a 1V supply showing a low power consumption (1.67 μW) and a noise floor of 0.8 μVrms over a bandwidth from 1 to 200 Hz.
Real-time phase correlation based integrated system for seizure detection
J.B. Romaine, M. Delgado-Restituto, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · Bio-MEMS and Medical Microdevices III Conference 2017
abstract
This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18μm CMOS process, only occupies an area of 0.0625μm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain.
A Chaotic Switched-Capacitor Circuit for Characteristic CMOS Noise Distributions Generation
N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2017
abstract
A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise (hopping map) and the other generating white noise (Bernoulli map). Through a programmable weighted adder stage, the contribution of each map can be controlled and, thereby, the position of the corner frequency. Behavioural models simulations were carried on in Cadence Virtuoso in order to prove the correct functionality of the proposed approach.
A 2.2 μW analog front-end for multichannel neural recording
J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2017
abstract
In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised by a two-stage AC-coupled low-noise amplifier (LNA) and a one stage AC-coupled variable gain amplifier (VGA). The proposed architecture employs highly power-noise efficient current reuse fully differential OTAs in the LNA stage and a fully differential folded cascode for the VGA stage. Simulation results in AMS 0.18μm validate the proposed architecture under process corners variations with an estimated power consumption of 2.2μm and 3.1 μVrms in-band noise.
Neural Spike Recording for Brain-Machine Interfaces
M. Delgado-Restituto
Conference · International Workshop on uDSD (Ultra-small-sized Diagnostic Smart Devices), 2016
abstract
Abstract not available
Mixed-Signal Quadratic Operators for the Feature Extraction of Neural Signals
M. Delgado-Restituto, R. Fiorelli, M. Carrasco-Robles and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2016
abstract
This paper presents design principles for reusing charge-redistribution SAR ADCs as digital multipliers. This is illustrated with an 8-b fully-differential rail-to-rail SAR ADC/multiplier, designed in a 180nm HV CMOS technology. This reconfigurability property can be exploited for the extraction of product-related features in neural signals, such as energy content, or for the discrimination of spikes using the Teager operator.
A 76nw, 4ks/S 10-Bit SAR ADC with Offset Cancellation for Biomedical Applications
M. Delgado-Restituto, M. Carrasco Robles, R. Fiorelli, A.J. Gines-Arteaga and A. Rodríguez-Vázquez
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2016
abstract
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180 nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2 nW at 4 kS/s and achieves 9.5-b ENOB.
A Low-Energy 10-bit SAR ADC with Embedded Offset Cancellation
M. Delgado-Restituto, M. Carrasco-Robles, R. Fiorelli, A.J. Gines-Arteaga and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
abstract
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180 nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2 nW at 4 kS/s and achieves 9.5-b ENOB.
Integer-based digital processor for the estimation of phase synchronization between neural signals
J.B. Romaine, M. Delgado-Restituto, J.A. Lenero-Bardallo and A. Rodriguez-Vazquez
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2016
abstract
This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. The low area and power consumptions make the processor an extremely scalable device which would work well in closed loop neural prosthesis for the treatment of neural diseases.
A 4-Mode Reconfigurable Low Noise Amplifier for Implantable Neural Recording Channels
J.L. Valtierra, A. Rodriguez-Vazquez and M. Delgado-Restituto
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2016
abstract
In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture allows for an active feedback to set the high-pass corner in place of the commonly used pseudoresistor. Bandwidth selectivity is achieved by cicuit reconfigurability which changes the pole frequencies of the system without impacting the total power consumption. Simulation results in AMS 0.18μm technology validate the proposed architecture in both nominal and corner process conditions with an estimated total power consumption of 454nW.
Highly scalable real time epilepsy diagnosis architecture via phase correlation and functional brain maps
J.B. Romaine, L. Acasandrei, M. Delgado-Restituto, A. Rodríguez-Vázquez
Conference · World Congress on Biosensors BIOSENSORS 2016
abstract
The complexity of biomedical neural processing is evident, with vast amounts of data needing to be handled and processed in order to reveal possible biomarkers which may lead to the early diagnosis of certain neurological disorders. One disorder in particular is epilepsy which is the most common neurological disorder in the world today affecting an estimated 50 million people.
Our proposed architecture is a highly efficient, scalable and low powered solution for the diagnosis and verification of epilepsy via the identification of changes in synchronicity between inter-ictal neural recording signals and functional brain maps. This multipurpose diagnosis system is realized as a mixture of clever data handling and sixteen real time phase synchronization processors which have a total capability of calculating the phase correlation of an entire brain map set of 120 neural signal combinations, gathered from 16 inter-ictal recording electrode positions located around the brain. Such a design could eventually lead to prediction of epilepsy via the detection of complex biomarkers.
In order for real time calculations to be possible we use a combination of smart pipelining and control logic. The processors calculate the phase correlation over the brain map via the means of accumulative sample differences from minimum to minimum transition periods between neural signals on sample by sample basis. This performs extremely well when compared to other more intense diagnostic calculation methods such as extraction of instantaneous phase angles.
The proposed architecture favours an ASCI design that drastically reduces the number of phase correlation calculation elements and cluttered interconnects and in turn infers a potentially low powered system.
Neural Recording Prosthesis for Brain-Machine Interfaces
M. Delgado-Restituto
Conference · Seminar on Electronics and Advanced Design INAOE 2015
abstract
Abstract not avaliable
Hardware friendly algorithm for the calculation of phase synchronization between neural signals
J.B. Romaine and M. Delgado-Restituto
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2014
abstract
This paper reports a mathematically simple, hardware efficient algorithm for use in the detection of epileptic seizures via an approximation of synchronization between two neural EEG signals. The algorithm assumes that the signals are pre-filtered into a desired narrow band, spanning only several 10's of Hz. Using this narrow band it is possible to collect the discrete time stamps, which are represented as the number of samples between two consecutive minimum within a given signal. The difference between a discrete time stamp in one signal and in another, at a given period in time gives an indication as to the amount of frequency difference between the two signals. Once these differences are accumulated, it provides an estimate as to when large increases and decrease in frequency happen in the two signals, with respect to one another.
A 64-channel ultra-low power system-on-chip for local field and action potentials recording
A. Rodríguez-Pérez, M. Delgado-Restituto, A. Darie, C. Soto-Sánchez, E. Fernández-Jover and Á. Rodríguez-Vázquez
Conference · SPIE Micro Technologies, 2015
abstract
This paper reports an integrated 64-channel neural recording sensor. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other,feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330μW.
A 330μW, 64-Channel Neural Recording Sensor with Embedded Spike Feature Extraction and Auto-calibration
A. Rodríguez-Pérez, M. Delgado-Restituto, A. Darie, C. Soto-Sánchez, E. Fernández-Jover and Á. Rodríguez-Vázquez
Conference · IEEE Asian Solid-State Circuits Conference A-SSCC 2014
abstract
pdf
This paper reports a 64-channel neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results show that the power consumption of the complete system is 330μW.
In vivo measurements with a 64-channel extracellular neural recording integrated circuit
M. Delgado-Restituto, A. Rodríguez-Pérez, A.A. Darie, Á. Rodríguez-Vázquez, C. Soto-Sánchez and E. Fernández-Jover
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2014
abstract
This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific Integrated Circuit (ASIC) developed at IMSE and gives details of the computer interface used for real-time data acquisition. This interface connects the ASIC to a conventional 2.0 USB port by means of a Field Programmable Gate Array (FPGA). Communications are bidirectional and employ custom protocols both for delivering commands to the ASIC and for recording neural information under different channel selection and operation modes. The link is controlled by a user-friendly programming interface written in C++ which includes a built-in routine to efficiently index and store the captured data. Mesurements demonstrate the suitability of the ASIC for capturing local field and action potentials with two different microelectrode array platforms.
Mixed-signal energy feature extractor of EEG frequency bands
M. Carrasco-Robles and M. Delgado-Restituto
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2014
abstract
This paper proposes a SAR-based circuit suitable to obtain the amount of signal energy contained in EEG frequency bands. It uses a reconfigurable topology which, in a first stage, acts as a conventional data converter for the incoming neural signal and, in a second stage, performs the squaring operation needed for energy extraction. A simple digital circuit keeps track of the most recent outputs from the squarer and provides the accumulated value of the input signal energy. The system has been simulated in an XFAB 0.18μm technology showing correct measurement of the energy.
Far-field UHF remotely powered front-end for patient monitoring with wearable antenna
O. Kazanc, J.A. Rodriguez-Rodriguez, M. Delgado-Restituto, F. Maloberti and C. Dehollain
Conference · IEEE International New Circuits and Systems Conference NEWCAS 2013
abstract
The design of a wearable antenna for UHF band at 900 MHz with an integrated front-end for a wireless sensor system targeting remote patient monitoring is presented. A wearable antenna for human body with -7.2 dB gain is demonstrated using five layer torso model. The antenna can deliver 25 μW of power to the rectifier at 4.6 meters distance from the base station emitting P EIRP=4 W. Local power management circuitry consumes a total power of 4 μW while delivering 10 μW of power for the sensors of the wireless sensor system. The system designed with 0.18pm CMOS process demonstrates the performance of the frontend together with 3D electromagnetic simulation results of the wearable antenna.
A Battery-free 64-channel Neural Spike Wireless Sensor Array
A. Rodríguez-Pérez, J. Ruiz-Amaya, J. Masuch, J.A. Rodríguez-Rodríguez, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Bio-MEMS and Medical Microdevices Conference 2013
abstract
This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. Simulation results show that the power consumption of the complete system is 377μW.
An RF Energy Harvester with Supply Management for co-Integration Into a 2.4 GHz Transceiver
J. Masuch, M. Delgado-Restituto, D. Milosevic and P. Baltus
Conference · European Solid-State Circuits Conference ESSCIRC 2012
abstract
This paper presents an RF energy harvester embedded in a low-power transceiver (TRX) front-end. Both the harvester and the TRX use the same antenna and operate at the same frequency of 2.4 GHz using a new topology with a start-up rectifier and exploiting the nonlinear impedance of the RF-DC converter for decoupling the harvester from the TRX. The harvester also includes a supply management circuit for charging energy storage devices. It has been implemented in a 130 nm CMOS process and achieves a measured peak power conversion efficiency of 15.9% with little impact on the TRX performance (less than 0.5dB degradation of output power and noise figure). For input power levels of at least -9 dBm, it is able to charge up a supply capacitor to a regulated voltage of 1.34 V. The complete harvester occupies only 0.019 mm2.
A 1.1mW-Rx, 5.9mW-Tx Bluettoth low energy transceiver with -81.4 dBm sensitivity
J. Masuch and M. Delgado-Restituto
Conference · International Solid-State Circuits Conference ISSCC 2012
abstract
Abstract not available
An RF-to-DC energy harvester for co-integration in a low-power 2.4 GHz transceiver frontend
J. Masuch, M. Delgado-Restituto, D. Milosevic and P. Baltus
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
abstract
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A 2.4 GHz energy harvester for co-integration into a low-power transceiver (TRx) operating at the same frequency is presented. An RF switch decouples the harvester from the TRx and keeps the performance degradation of the TRx low, i.e. 0.2 dB reduced output power in Tx-mode and 0.4 dB reduced sensitivity in Rx-mode. In order to enable the harvester to operate without a DC power supply, an RF switch is used that is passively turned on. The circuit is implemented in a 130 nm CMOS process, and requires a minimum input RF power of 10 dBm. Based on post-layout simulation results the proposed energy harvester achieves a peak efficiency of 22.7% at an input power level of 3 dBm.
A self-calibration circuit for a neural spike recording channel
A. Rodríguez-Pérez, J. Ruiz-Amaya, M. Delgado-Restituto, M. Sawan and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2011
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This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. It also performs the adjustment of the Programmable Gain Amplifier (PGA) gain to maximize the input voltage range of the analog-to-digital conversion. The circuit, which consists on a frequency-controlled signal generator and a digital processor, operates in foreground, is completely autonomous and integrable in an estimated area of 0.026mm 2, with a power consumption around 450nW. The calibration procedure takes less than 250ms to select the configuration whose performance is closest to the required one. © 2011 IEEE.
A 350 μW 2.3 GHz integer-N frequency synthesizer for body area network applications
J. Masuch and M. Delgado-Restituto
Conference · IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems SiRF 2011
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This paper presents a low power integer-N synthesizer with an output frequency of 2.3 GHz. The complete PLL has been integrated in a 90 nm CMOS technology and operates from a 1 V supply voltage. The synthesizer has been optimized for power consumption by employing an efficient quadrature VCO and a phase-switching prescaler. It achieves a phase noise of -121 dBc/Hz @3MHz while consuming only 350 uW in the PLL core. The typical reference spur level is about -40 dBc. © 2011 IEEE.
A power efficient neural spike recording channel with data bandwidth reduction
A. Rodríguez-Pérez, J. Ruiz-Amaya, J.A. Rodríguez-Rodríguez, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2011
abstract
This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13 mu m and occupies 400 mu mx400 mu m. The overall power consumption of the channel during signal tracking is 2.8 mu W and increases to 3.0 mu W average when the feature extraction operation mode is programmed.
An auto-calibrated neural spike recording channel with feature extraction capabilities
A. Rodríguez-Pérez, J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · SPIE Microtechnologies for the New Millennium 2011
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This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a self-calibration operation mode and can be used both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a PWL approximation of the spikes in order to reduce data bandwidth on the RF-link). The neural threshold voltage is adaptively calculated during the spike detection period using basic digital operations. The neural input signal is amplified and filtered using a LNA, reconfigurable Band-Pass Filter, followed by a fully reconfigurable 8-bit ADC. The key element is the ADC architecture. It is a binary search data converter with a SC-implementation. Due to its architecture, it can be programmed to work either as a PGA, S&H or ADC. In order to allow power saving, inactive blocks are powered off depending on the selected operation mode, ADC sampling frequency is reconfigured and bias current is dynamically adapted during the conversion. Due to the ADC low input capacitance, the power consumption of the input LNA can be decreased and the overall power consumption of the channel is low. The prototype was implemented using a CMOS 0.13um standard process, and it occupies 400um x 400um. Simulations from extracted layout show very promising results. The power consumption of the complete channel for the signal tracking operations is 2.8uW, and is increased to 3.0uW when the feature extraction operation is performed, one of the lowest reported.
A 55 μW programmable gain amplifier with constant bandwidth for a direct conversion receiver
J. Masuch and M. Delgado-Restituto
Conference · SPIE Microtechnologies for the New Millennium 2011
abstract
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A fully differential programmable gain amplifier (PGA) with constant transfer characteristic and very low power consumption is proposed and implemented in a 130 nm CMOS technology. The PGA features a gain range of 4 dB to 55 dB with a step size of 6 dB and a constant bandwidth of 10-550 kHz. It employs two stages of variable amplification with an intermediate 2nd order low-pass channel filter.
The first stage is a capacitive feedback OTA using current-reuse achieving a low input noise density of 16.7 nV/√Hz. This stage sets the overall high-pass cutoff frequency to approximately 10 kHz. For all gain settings the high-pass cutoff frequency variation is within ±5%.
The low-pass channel filter is merged with a second amplifying stage forming a Sallen-Key structure. In order to maintain a constant transfer characteristic versus gain, the Sallen-Key feedback is taken from different taps of the load resistance. Using this new approach, the low-pass cutoff frequency stays between 440 kHz and 590 kHz for all gain settings (±14%). Finally, an offset cancelation loop reduces the output offset of the PGA to less than 5 mV (3 σ).
The PGA occupies an area of approximately 0.06 mm(2) and achieves a post-layout power consumption of 55 μW from a 1V-supply. For the maximum gain setting the integrated input referred noise is 14.4 μV(RMS) while the total harmonic distortion is 0.7 % for a differential output amplitude of 0.5 V.
Impact of Parasitic Capacitances on the Performance of SAR ADCs based on Capacitive Arrays
A. Rodriguez-Pérez, J.A. Rodríguez-Rodríguez, F. Medeiro and M. Delgado-Restituto
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2010
abstract
Abstract not avaliable
A review of low-noise amplifiers for neural applications
J. Ruiz-Amaya, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · Circuits and Systems for Medical and Environmental Applications Workshop CASME 2010
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This paper presents a comparative study of three low-noise amplifiers for neural recording applications. The topologies are thoroughly analysed in terms of area, power consumption and noise performance. Further, the theoretical results are confirmed by simulations of transistor-level implementations in a 0.13um CMOS technology at 1.2V supply voltage. © 2010 IEEE.
Transformer based front-end for a low power 2.4 GHz transceiver
J. Masuch, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Asia-Pacific Conference on Circuits and Systems APCCAS 2010
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A low power transceiver architecture for the 2.4 GHz ISM band using a 1.0 V supply is presented. It employs a transformer to convert the 100 Ohm antenna impedance to almost 1 kOhm and so facilitates a low power transmitter and receiver. The simulated post-layout output power of the differential class-E power amplifier is 2.0 dBm with a drain efficiency of 28.4%. The direct-conversion receiver achieves a very low power consumption of 420 uW and a noise figure of 15.0 dB. © 2010 IEEE.
A reconfigurable neural spike recording channel with feature extraction capabilities
A. Rodríguez-Pérez, J. Ruiz-Amaya, O. Guerra and M. Delgado-Restituto
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2010
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This paper describes the architecture of a neural spike recording channel with feature extraction capabilities and presents the design of one of its key elements, a reconfigurable 8-bit ADC. The ADC can be programmed for different conversion rates and embeds a 0-18dB programmable gain amplifier with discrete gain steps of 3dB. Simulation results from extracted layout of the ADC, designed in a 130nm CMOS technology, obtain almost 8-bit ENOB at 22.2kS/s and 90kS/s, with a power consumption of 500nW and 1.8uW, respectively. ©2010 IEEE.
Baseband-processor for a passive UHF RFID transponder
J.A. Rodríguez-Rodríguez, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · International Conference on Green Circuits and Systems ICGCS 2010
abstract
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This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID transponders, and proposes different techniques for reducing its power consumption. The processor has been implemented in a 0.35um CMOS technology process using automatic tools for both the logic synthesis and layout. Post-layout simulations confirm the fully functionality of the prototype and predict a worst-case power consumption of only 2.9uA at 1.2V supply. © 2010 IEEE.
A comparative study of low-noise amplifiers for neural applications
J. Ruiz-Amaya, A. Rodríguez-Pérez and M. Delgado-Restituto
Conference · International Conference on Microelectronics ICM 2010
abstract
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This paper presents a comparative study of three low-noise amplifiers for neural recording applications. The topologies are thoroughly analysed in terms of area, power consumption and noise performance. Further, the theoretical results are confirmed by simulations of transistor-level implementations in a 0.13 mu m CMOS technology at 1.2V supply voltage.
Low power 2.4 GHz quadrature generation for body area network applications
J. Masuch and M. Delgado-Restituto
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
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This paper presents two implementations of low-power quadrature generation for the new Bluetooth low energy standard in the 2.4 GHz ISM band. Both implementation have been designed in a 90 nm CMOS technology for a 1 V supply voltage and post-layout simulation results are presented. The first implementation is a quadrature voltage controlled oscillator (QVCO) with 180μW power consumption and a phase noise of -112.7 dBc/Hz @1MHz. It employs a new technique to reduce the influence of magnetic coupling between the two spiral inductors. The second implementation employs a VCO running at twice the frequency with a subsequent divide-by-2 stage. Its total power consumption is 320μW and the phase noise at the quadrature outputs is -115.7 dBc/Hz @1MHz.
A low-power reconfigurable ADC for biomedical sensor interfaces
A. Rodríguez-Pérez, M. Delgado-Restituto, F. Medeiro and A. Rodríguez-Vázquez
Conference · Biomedical Circuits and Systems Conference BIOCAS 2009
abstract
This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC can be tuned to handle a large variety of biopotential signals, with digitally selectable resolution and input signal amplitude. It achieves 10.4-bit of effective resolution sampling at 56kS/s, with a power consumption below 3 mu W from a 1V voltage supply.
Design constraints for the inductive power and data link of an implanted body sensor
J. Masuch and M. Delgado-Restituto
Conference · European Conference on Circuit Theory and Design ECCTD 2009
abstract
In this paper the basic system design constraints for the inductive power and data link are shown. The limiting factors for the choice of quality factors, coil inductance and carrier frequency are evaluated through analytical methods and simulations. The impact of the analysis on the required rectifier structure is also discussed. The analysis is focused on the development of a miniature biomedical sensor device whose outer dimensions shall not exceed 5-by-5 mm.
A low-voltage low-power successive approximation reconfigurable ADC based on SC techniques
A. Rodríguez-Pérez, M. Delgado-Restituto and F. Medeiro
Conference · Ph.D. Research in Microelectronics and Electronics PRIME 2009
abstract
This paper presents a 12-bit low-voltage low-power Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC is highly reconfigurable, with digitally selectable resolution and input signal amplitude, and achieves 11.4-bit of effective resolution at 500kHz clock frequency, with a power consumption below 3 mu W from a 1V voltage supply.
An EPC class-1 generation-2 baseband processor for passive UHF RFID tag
J.A. Rodríguez-Rodríguez, J. Masuch and M. Delgado-Restituto
Conference · Ph.D. Research in Microelectronics and Electronics PRIME 2009
abstract
Passive UHF RFID transponders (tags, in short) are mixed-signal Systems-on-Chip (SoCs) for remotely powered communications which must comply with stringent requirements on current consumption. This brief focuses on the design of a backend digital processor for UHF RFID tags targeting the Class-1 Generation-2 EPC Protocol, and proposes different techniques for reducing its power consumption. After code validation with an FPGA, the processor has been synthetised in a 0.35 mu m CMOS technology process and occupies 7mm(2) including pads. The design also incorporates a 10-b rail-to-rail SAR ADC for sensory applications. Under maximum digital activity conditions, post-layout simulations show that the power consumption of the processor below 2.8 mu W.
An ultra-low power consumption 1-V, 10-bit succesive approximation ADC
A. Rodríguez-Pérez, M. Delgado-Restituto, J. Ruiz-Amaya and F. Medeiro
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2008
abstract
An ultra-low power consumption 10-bit rail-to-rail input range succesive-approximation Analog-to-Digital Converter (ADC) for sensor network applications is presented. It is designed in a standard 0.13um CMOS process technology. The converter consists of a capacitor-based digital-to-analog converter, a two-stage voltage comparator, formed by a pre-amplifier and a dynamic-latch, a passive sample-and-hold circuit, a current reference generator and digital circuitry for switching and control. Post-layout simulations show that the ADC consumes less than 2uW at a conversion rate of 100kS/s from a 1V voltage supply. Proper operation is achieved down to a supply voltage of 0.8 V. © 2008 IEEE.
Electrical-level synthesis of pipeline ADCs
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
abstract
This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter specifications, such as the required effective resolution, onto electrical-level parameters, i.e., transistor sizes and biasing conditions. It is based on the combination of a behavioural simulator for performance evaluation, accurate models of the converter components, and an optimization algorithm to minimize the power and area consumption of the circuit solution. The design procedure is herein demonstrated with the complete design of a 0.13 mu m CMOS 10bits@60MS/s pipeline ADC, which only consumes 11.3mW from a 1.2V supply voltage. A close agreement between behavioural- and electrical-level simulations is obtained with only 0.2bit deviation on the measured ENOB.
A 5.3 mW, 2.4 GHz ESD protected low-noise amplifier in a 0.13 um RFCMOS technology
D. Brandano, M. Delgado-Restituto, J. Ruiz-Amaya and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2007
abstract
An Electrostatic Discharge (ESD) protected Low-Noise Amplifier (LNA) for the 2.4GHz ISM band designed in a 0.13 mu m standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8dB power gain, reflexion coeffcients S-11, S-22 <-30dB over the 2.4GHz ISM band, a peak noise figure of 1.8 dB, and an IIP3 of 1dBm, while drawing less than 4.5mA do biasing current from the 1.2V power supply. Further, the LNA withstands a Human Body Model (HBM) ESD stress up to +/- 2.0kV, by means of the additional custom protection circuitry.
Design procedure for optimizing the power consumption of two-stage Miller compensated amplifiers in SC circuits
J. Ruiz-Amaya, J.F. Fernández-Bootello and M. Delgado-Restituto
Conference · European Conference on Circuit Theory and Design ECCTD 2007
abstract
This paper presents a procedure for the design of two-stage Miller-compensated operational transconductance amplifiers in switched-capacitor circuit applications. The objective of this approach, implemented in MATLAB, is the electrical-level synthesis of amplifiers so that settling error specifications are satisfied with minimum power consumption. At the core of the tool, an accurate routine for parasitics estimation is used to guarantee a close agreement between high-level and electrical simulation results. The procedure and tool are demonstrated with the sizing of a 1.2V supply fully-differential two-stage Miller compensated amplifier in a 0.13 mu m technology.
Comparison of the DR of continuous time Gm-C filters using different structures
J.F. Fernández-Bootello, M. Delgado-Restituto, A. Rodríguez-Vázquez and D. Brandano
Conference · WSEAS International Conference on CIRCUITS 2006
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This paper presents design techniques to evaluate the noise and distortion of continuous time Gm-C filters. Also presents techniques to improve the dynamic range of such filters keeping a relation of integer numbers between the transconductors. Furthermore the comparison of the dynamic range for the same power using different structures is presented.
A 12-bit CMOS current steering D/A converter for embedded systems
J. Ruiz-Amaya, M. Delgado-Restituto, J.F. Fernández-Bootello, D. Brandano, R. Castro-López and J.M. de la Rosa
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2006
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This paper describes the design of a 12-bit digital-to-analog converter for a wireline modem chip implemented in a 0.13 mu m digital CMOS technology. Transistor-level simulations from extracted layout at the nominal modem data rate of 80MS/s show an Spurious-Free Dynamic-Range (SFDR) better than 62dB at Nyquist rate under industrial operation conditions (40 to 85 degrees temperature range and +/- 10% supply variations) and for all technology process corners. Additionally, the converter achieves a Multi-Tone Power Ratio (MTPR) higher than 59dB for different Discrete MultiTone (DMT) test patterns consisting of 1536 carriers that fall in the Nyquist band. Simulation results at a higher data rate of 200MS/s are also shown in the paper. The converter dissipates less than 150mW from a mixed 3.3/1.2V supply and occupies less than 1.7mm(2).
A 0.13μm CMOS Current Steering D/A Converter for PLC and VDSL Applications
J. Ruiz-Amaya, J.F. Fernández-Bootello, J.M. de la Rosa, M. Delgado-Restituto and R. del Río
Conference · XX Conference on Design of Circuits and Integrated Systems DCIS 2005
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This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The converter is segmented in an unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distributed in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Transistor-level simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher than 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 active area.
A 12-bit 80 MS/s A/D/A Interface for Power-Line Applications in 0.13μm Digital CMOS Technology
J. Ruiz-Amaya, J.F. Fernández-Bootello, J.M. de la Rosa, R. del Río and M. Delgado-Restituto
Conference · 5th Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
abstract
Abstract not available
Dynamic range optimization of continuous-time G(m)-C filters
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · European Conference on Circuit Theory and Design ECCTD 2005
abstract
This paper presents a fast procedure for the system-levcl evaluation of noise and distortion in continuous-time G(m)-C filters. The presented approach is based on Volterra's series expansion and matrix algebra manipulation. This procedure has been integrated in a constrained optimization routine to improve the dynamic range of filters while keeping the area and power consumption at a minimum. A seventh-order, elliptic, G(m)-C low-pass filter, realized in a 0.18 mu m CMOS technology, following the proposed procedure, demonstrates the suitability of the approach.
A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract
This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra's series theory and matrix algebra manipulation. This procedure has been integrated in a constrained optimization routine to improve the dynamic range of the filter while keeping the area and power consumption at a minimum. The proposed approach is demonstrated with the design, from system- to physical-level, of a seventh-order low-pass continuous-time elliptic filter for a high-performance broadband power-line communication receiver. The filter shows a nominal cut-off frequency of f(c) = 34MHz, less than 1 dB ripple in the pass-band, and a maximum stop-band rejection of 65 dB. Additionally, the filter features 12 dB programmable boost in the pass-band to counteract high frequency components attenuation. Taking into account its wideband transfer characteristic, the filter has been implemented using G(m)-C techniques. The basic building block of its structure, the transconductor, uses a source degeneration topology with local feedback for linearity improving and shows a worst-case intermodulation distortion of -70 dB for two tones close to the passband edge, separated by 1 MHz, with 70mV of amplitude. The filter combines very low noise (peak root spectral noise density below 56nV/root Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5V(pp) amplitude) properties. The filter has been designed in a 0.18 mu m CMOS technology and it is compliant with industrial operation conditions (40 to 85 degrees C temperature variation and 5% power supply deviation). The filter occupies 13 mm(2) and exhibits a typical power consumption of 450 mW from a 1.8V voltage supply.
Simulation-based high-level synthesis of nyquist-rate data converters using MATLAB/SIMULINK
J. Ruiz-Amaya, J.M. de la Rosa, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract
This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB (R). The embedded simulator uses SIMULINK (R) C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK (R) elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK (R) platform by using the MATLAB (R) engine library, so that the optimization core runs in background while MATLAB (R) acts as a computation engine. The implementation on the MATLAB (R) platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13 mu m CMOS 12-bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.
Design of a 12-bit 80 MS/s pipeline analog-to-digital converter for PLC-VDSL applications
J. Ruiz-Amaya, M. Delgado-Restituto, J.F. Fernández-Bootello and J.M. de la Rosa
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract
This paper describes the design of a 12-bit 80MS/s pipeline Analog-to-Digital converter implemented in 0.13 mu m CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation, synthesis and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is based on a 10-stage pipeline preceded by a sample/hold with bootstrapping technique. Each stage gives 1.5 effective bits, except for the first one which provides 2.5 effective bits to improve linearity. The Analog-to-Digital architecture uses redundant bits for digital correction, it is planned to be implemented without using calibration and employs a subranging pipeline look-ahead technique to increase speed. Substrate biased MOSFETs in the depletion region are used as capacitors, linearized by a series compensation. Simulation results show that the Multi-Tone Power Ratio is higher than 56dB for several DMT test signals and the estimated Signal-to-Noise Ratio yield is supposed to be better than 62 dB from DC to Nyquist frequency. The converter dissipates less than 150mW from a 3.3V supply and occupies less than 4 mm(2) die area. The results have been checked with all process corners from -40 degrees to 85 degrees and power supply from 3V to 3.6V.
A 0.18 μm CMOS low-noise elliptic low-pass continuous-time filter
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
abstract
This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline communication receiver. As an additional attribute, the filter provides programmable boost in the pass-band to counteract high frequency components attenuation. The filter shows a nominal cutoff frequency of f(c) = 34 MHz, less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. The filter also exhibits low noise feature (peak root spectral noise density below 56nV/root Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5V(pp) amplitude). It has been designed in a 0.18 mu m CMOS technology and it is compliant with industrial operation conditions (40 to 85 degrees C temperature variation and +/- 5% power supply deviation). Simulations show a typical power consumption of 450 mW @ 1.8V supply.
An embedded 12-bit 80 MS/s A/D/A interface for power-line communications in 0.13 um pure digital CMOS technology
M. Delgado-Restituto, J. Ruiz-Amaya, J.M. de la Rosa, J.F. Fernández-Bootello, L. Díez, R. del Río and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
abstract
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This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13 mu m pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band powerline communications. The A/D converter uses a pipelined structure, whereas the D/A stage is based on segmented current steering techniques. In both cases, specifications are 12-b resolution at 80MS/s and MTPR above 56dB.
Behavioral modeling simulation and high-level synthesis of pipeline A/D converters
J. Ruiz-Amaya, J.M. de la Rosa, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
abstract
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This paper presents a MATLAB (R) toolbox for the time-domain simulation and high-level sizing of pipeline analog-to-digital converters. SIMULINK (R) C-coded S-functions are used to describe the behavioral models of all building blocks, including their main circuit errors. This approach significantly speeds up system-level simulations while keeping high accuracy - verified with HSPICE - and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable CAD tool for the high-level design of broadband communication analog front-ends. As a case study, an embedded 0.13 mu m CMOS 12bit@80MS/s A/D interface for a PLC chipset is designed to show the capabilities of the presented tool.(dagger 1)
Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters
J. Ruiz Amaya, J.M. de la Rosa and M. Delgado-Restituto
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2004
abstract
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This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of pipeline analog-to-digital converters in MATLAB. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK as C-compiled S-functions. This approach significantly speeds up system-level simulations while keeping high accuracy -verified with HSPICE- and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s ADC for a PLC chipset is designed to show the capabilities of the presented tool.
Experimental Characterization of an Integrated Chaos-Based FM-DCSK Transmitter Chipset
M. Delgado-Restituto, A.J. Acosta-Jimenez and A. Rodriguez Vazquez
Conference · Experimental Chaos Conference 2004
abstract
Abstract not avaliable
A mixed-signal ASIC for FM-DCSK modulation
M. Delgado-Restituto, A.J. Acosta-Jimenez and A. Rodriguez-Vazquez
Conference · Design of Circuits and Integrated Systems Conference DCIS 2004
abstract
This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER =10(-3) for Eb/No lower than 28 dB.
A mixed-signal integrated circuit for FM-DCSK modulation
M. Delgado-Restituto, A.J. Acosta and A. Rodríguez-Vázquez
Conference · European Solid-State Circuits Conference ESSCIRC 2004
abstract
This paper presents a mixed-signal ASIC for a Frequency-Modulated Differential Chaos Shift Keying (FM-DCSK) communication system [1][2] which has been implemented in a 2P-3M 0.35mum CMOS technology. The prototype has been provided with several programming capabilities to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme. The operation of the integrated circuit is herein illustrated for a data rate of 500kb/s and a transmission bandwidth in the range of 17MHz. Based on experimental results, an estimation of the Bit Error Rate (BER) performance of the modulation scheme in a wireless environment at the 2.4GHz ISM band under different propagation conditions has been realized. Measured results confirm theoretical predictions.(dagger)
System-level optimization of baseband filters for communication applications
J.F. Fernández-Bootello, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems 2003
abstract
In this paper, a design approach for the high-level synthesis of programmable continuous-time baseband filters able to achieve optimum trade-off among dynamic range, distortion behavior, mismatch tolerance and power/area consumptions is presented. The proposed approach relies on building programming circuit elements as arrays of switchable unit cells and defines the synthesis as a constrained optimization problem with both continuous and discrete variables, this last rep-resenting the number of enabled cells of the arrays at each configuration. The cost function under optimization is; then, defined as a weighted combination of performance indices which are estimated from macromodels of the circuit elements. The methodology has been implemented in MATLAB(TM) and C++, and covers all the classical approximation techniques for filters, most common circuit topologies (namely, ladder simulation and cascaded biquad realizations) and both transconductance-C (G(m)-C) and active-RC implementation approaches. The proposed synthesis strategy is illustrated with a programmable equal-ripple ladder G(m)-C filter for a multi-band power-line communication modem.
Generation of technology-portable flexible analog blocks
R. Castro-López, F.V. Fernández, M. Delgado-Restituto, F. Medeiro and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
abstract
This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even to different technology processes. By careful integration of the tuning process of design parameters with layout generation, fully functional designs are generated in a few minutes of CPU time.
Books
Ultra Low Power Transceiver for Wireless Body Area Networks
J. Masuch and M. Delgado-Restituto
Book · ACSP, 122 p, 2013
abstract
link
This book describes the design of ultra low power transceivers for body area networks. Since these applications have very limited energy resources, typically powered only by tiny batteries or through energy harvesting techniques, this book describes an architecture for a Bluetooth low energy transceiver to overcome these limitations. Coverage includes not only the main concepts for achieving low power consumption, but also the details of the circuit design and its implementation in a standard CMOS technology.
Device-level modeling and synthesis of high-performance pipeline ADCs
J. Ruiz-Amaya, M. Delgado-Restituto and A. Rodríguez-Vázquez
Book · 209 p, 2011
abstract
link
This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations. As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.
Book Chapters
Neural Recording Interfaces for Intracortical Implants
M. Delgado-Restituto and A. Rodríguez-Pérez
Book Chapter · Implantable Biomedical Microsystems, pp 251-279, 2015
abstract
doi
This chapter reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized, and compressed in the channels. Additionally, each channel implements a local autocalibration mechanism that configures the transfer characteristics of the recording site. The system has two operation modes; in one case, the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. The power consumption of the complete system is 377 μW.
A low-power baseband processor for passive RFID tags employing low-power design techniques
J.A. Rodríguez-Rodríguez and M. Delgado-Restituto
Book Chapter · Advances in RFID Tags, 2011
abstract
This chapter focuses on the design of the baseband processing section of a passive UHF RFID tag for half-duplex communications in the 860-960 MHz range, which implements the EPC(TM) Class-1 Generation-2 (Gen2) protocol. Besides serving identification purposes, the tag also includes a 10-bit, 2kS/s generic signal acquisition interface to allow for signal readouts from the environment (e.g., temperature, pressure, optical or chemical variables). This ability to monitor, record and even react to ambient conditions is expected to promote a new world of applications for RFIDs.
Given the complexity of the protocol and the lack of external batteries, as in the case of active transponders, design efforts has been directed towards minimizing the power consumption of the processor. To this end, different power saving techniques has been considered in the implementation. They include the use of clock gating and power down control strategies or the synthesis of dedicated clocks per processor task. Additionally, most of the blocks of the decoding section of the processor are operated by means of simple trigger pulses at a rate defined by the incoming data (much slower than the master clock signal). The combined effect of these techniques is that every element of the processor always operates at the lowest clock frequency possible and it is only active when strictly required. A sophisticated timing unit able to generate the different clock signals, block operation windows and trigger pulses is the responsible for the application of the aforementioned low-power design techniques.
The processor, which implements all the commands/actions defined by the Gen-2 protocol, has been implemented in a 0.35μm CMOS technology process using automatic tools for both the logic synthesis and layout. It operates from a 1.2V supply voltage and uses a nominal master clock frequency of 1.92 MHz, enough to comply with the Gen2 requirements. Besides, the processor also includes a simple protocol for handling the signal captured from the sensor interface. This protocol takes advantage of commands already defined in the standard, namely, the Write command for reading and storing the captured data into the nonvolatile memory of the tag, and the Read command, for transferring the sensory information to the interrogator. The signal acquisition interface consists of a rail-to-rail input band-limited programmable gain amplifier followed by a capacitive DAC based Successive Approximation Register (SAR) ADC.
The power consumption of the processor has been measured assuming maximum bit-rates for the forward and backward links. During a communication link involving five consecutive commands, the processor consumes less than 2.9μA, assuming worst-case timing conditions. Further, the signal acquisition interface consumes 130nA at 2kS/s and obtains 9.4 bits ENOB (58.4dB SNDR) for a full-scale 300Hz input tone.
Power efficient ADCs for biomedical signal acquisition
A. Rodríguez-Pérez, M. Delgado-Restituto and F. Medeiro
Book Chapter · Biomedical Engineering, Trends in Electronics, Communications and Software, pp 171-192, 2011
abstract
doi pdf
Rapid technological developments in the last century have brought the field of biomedical engineering into a totally new realm. Breakthroughs in materials science, imaging, electronics and, more recently, the information age have improved our understanding of the human body. As a result, the field of biomedical engineering is thriving, with innovations that aim to improve the quality and reduce the cost of medical care. This book is the first in a series of three that will present recent trends in biomedical engineering, with a particular focus on applications in electronics and communications. More specifically: wireless monitoring, sensors, medical imaging and the management of medical information are covered, among other subjects. Summary of the book.
Synthesis and design of nonlinear circuits
A. Rodríguez-Vázquez, M. Delgado-Restituto, J.L. Huertas-Díaz and F. Vidal-Verdú
Book Chapter · Nonlinear and Distributed Circuits, pp 2-1, 2-36, 2005
abstract
doi
Abstract not available
PGAs and filters
M. Delgado-Restituto and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 481-521, 2003
abstract
doi
Amplifiers and filters are commonplace devices in the analog front-end (AFE) of communication transmitters-receivers (transceivers, in short). In a general sense, these devices provide the necessary adaptation, in terms of power adjustment and signal isolation, between the transmission media (e.g., atmosphere, free space, cable, twisted-pair, optic fiber) and the digital signal processor (DSP) which performs most of the algorithmic tasks needed to guarantee a reliable transmission/reception of the information. In some cases as, for instance, in wireless transceivers, amplification and filtering may take place at multiple steps along the AFE; often using different technologies (CMOS, silicon bipolar, GaAs) or external passive components (e.g., surface-acoustic wave filters) depending on the frequency range at which operations are realized. In this chapter, following the main stream of the book, we focus on the realization of those amplifiers and filters which are used to drive signals to/from the AFE data converters at the interface with the DSP block, paying special attention on their implementation in inexpensive CMOS technologies. Such amplifiers and filters are symbolically shown in Fig. 14.1, where preceding/following circuits for reception/transmission have been globally called Rx/Tx medium interface, respectively.
CMOS comparators
R. Domínguez-Castro, M. Delgado-Restituto, A. Rodríguez-Vázquez, J.M. de la Rosa and F. Medeiro
Book Chapter · CMOS Telecom Data Converters, pp 149-182, 2003
abstract
doi
abstract not available
Trade-offs in the design of CMOS comparators
A. Rodríguez-Vázquez, M. Delgado-Restituto and J.M. de la Rosa-Utrera
Book Chapter · Trade offs in analog circuit design, pp 407-441, 2002
abstract
doi
This chapter first presents an overview of CMOS voltage comparator architectures and circuits. Starting from the identification of the comparator behavior, Section 14.2 introduces several comparator architectures and circuits. Then, Section 14.3 assumes these topologies, characterizes high-level attributes, such as static gain, unitary time constant, etc., and analyzes the resolution-speed trade-off for each architecture. Such analysis provides a basis for comparison among architectures. These previous sections of the chapter neglect the influence of circuit dissymmetries. Dissymmetries are covered in Section 14.4 and new comparator topologies are presented to overcome the offset caused by dissymmetries. Related high-level trade-offs for these topologies are also studied in this section.
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