Found results matching for:
Author: Laurentiu Acasandrei
Year: Since 2002
Journal Papers
AMBA bus hardware accelerator IP for Viola-Jones face detection
L. Acasandrei and A. Barriga
Journal Paper · IET Computers and Digital Techniques, vol. 7, no. 5, pp 200-209, 2013
abstract
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Face detection is an important aspect for biometrics, video surveillance and human computer interaction. Owing to the complexity of the detection algorithms any biometric system requires a huge amount of computational and memory resources. A direct software-like implementation of any detection algorithm on a low speed, low resource, low power system on chip (SoC) is not feasible. Instead, a software-hardware codesign approach can be used to build hardware accelerators for the most computational consuming parts of the detection algorithms. Therefore the authors propose a compliant advanced microcontroller bus architecture (AMBA) bus hardware IP, a modularised, highly configurable, low power and technology independent core written in an hardware description language (HDL) language. The IP core accelerates Viola-Jones algorithm considered to be one of the most used algorithms for face detection. The hardware accelerator IP is used in an embedded face detection system built around the LEON3 Sparc V8 processor. The authors present the methodology, challenges and performance results for software, hardware and system level design. For the mentioned system the authors have obtained an acceleration factor of 10-12 when using the hardware accelerator in comparison with the software only traditional approach.
Conferences
SHORES: Software and Hardware Open Repository for Embedded Systems
L. Acasandrei and A. Barriga
Conference · World Congress on Engineering and Computer Science WCECS 2017
abstract
This communication describes an open source repository for embedded software and hardware designs. Its main goal is to make available to everyone, in an open-source
style, the designs and results from academia/research community. SHORES hosts the source code of various software and hardware design projects, that combined with the newest
algorithms proposed by academia, give birth to embedded solutions to the most challenging obstacles in the fields of vision, bio-cryptography, signal processing, etc. SHORES resources are distribute under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the license, or any later version.
Experiencia en desarrollo de sistemas empotrados hardware-software como Trabajo Fin de Grado
J.M. Calahorro, L. Acasandrei, A. Barriga and M.J. Avedillo
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
abstract
Se presenta en esta comunicación el desarrollo de un Trabajo Fin de Grado (TFG) de la Titulación de Ingeniería Informática-Ingeniería de Computadores. El objetivo es mostrar la experiencia en el desarrollo de un TFG que aúne aspectos multidisciplinares, que permitan desarrollar en el alumno las capacidades adquiridas durante el proceso educativo en el Grado en Ingeniería de Computadores. En concreto se plantea la especificación de un sistema empotrado hardware-software dentro del campo de aplicación del reconocimiento de caras en imágenes y/o video, competitivo en términos de velocidad respecto a una implementación puramente software.
Hardware-Software Embedded Face Recognition System
M.J. Avedillo, A. Barriga, L. Acasandrei and J.M. Calahorro
Conference · International Conferences in Central Europe on Computer Graphics, Visualization and Computer Vision WSCG 2016
abstract
This paper describes the design and implementation of a hardware-software embedded system for face recognition applications in images and/or videos. The system has hardware components to speed up the face detection and recognition stages. It is a system suitable for applications requiring real-time, due that the response times are deterministic and bounded. The system is based on a previous implementation that had accelerated the image capturing process, and the face detection. This paper will focuses in the face recognition acceleration.
Highly scalable real time epilepsy diagnosis architecture via phase correlation and functional brain maps
J.B. Romaine, L. Acasandrei, M. Delgado-Restituto, A. Rodríguez-Vázquez
Conference · World Congress on Biosensors BIOSENSORS 2016
abstract
The complexity of biomedical neural processing is evident, with vast amounts of data needing to be handled and processed in order to reveal possible biomarkers which may lead to the early diagnosis of certain neurological disorders. One disorder in particular is epilepsy which is the most common neurological disorder in the world today affecting an estimated 50 million people.
Our proposed architecture is a highly efficient, scalable and low powered solution for the diagnosis and verification of epilepsy via the identification of changes in synchronicity between inter-ictal neural recording signals and functional brain maps. This multipurpose diagnosis system is realized as a mixture of clever data handling and sixteen real time phase synchronization processors which have a total capability of calculating the phase correlation of an entire brain map set of 120 neural signal combinations, gathered from 16 inter-ictal recording electrode positions located around the brain. Such a design could eventually lead to prediction of epilepsy via the detection of complex biomarkers.
In order for real time calculations to be possible we use a combination of smart pipelining and control logic. The processors calculate the phase correlation over the brain map via the means of accumulative sample differences from minimum to minimum transition periods between neural signals on sample by sample basis. This performs extremely well when compared to other more intense diagnostic calculation methods such as extraction of instantaneous phase angles.
The proposed architecture favours an ASCI design that drastically reduces the number of phase correlation calculation elements and cluttered interconnects and in turn infers a potentially low powered system.
SRAM-based Physical Unclonable Keys for BLE Smart Lock Systems
I. Baturone, M.A. Prada-Delgado, A. Vázquez-Reyes, L. Acasandrei, D. Fernández-Barrera and J. Prada-Delgado
Conference · Design, Automation and Test in Europe DATE 2016
abstract
Nowadays, several smart lock systems use Bluetooth Low Energy (BLE) to recognize when a smartphone, conveniently authenticated by a digital key, is near. The keys can be shared and are managed by web apps, so that system security depends on how the software prevents an attacker from discovering the keys. In order to increase security by a two-factor method (‘something you have’ in addition to ‘something you know’), the BLE smart lock system prototype shown in this demonstrator recognizes when a user wearing an authenticated BLE chip (in a key fob, wristband, etc.) is near. The digital keys are not stored but they are regenerated on the fly by only the trusted chip. This is possible by using the start-up values of the SRAM in the BLE chip, which act as a physical unclonable function (PUF), so that the chip cannot be cloned. The SRAM start-up values of the BLE chip are also exploited as true random numbers to derive fresh keys for each transaction with the lock.
Repositorio de componentes hardware y software de código abierto para sistemas empotrados
L. Acasandrei and A. Barriga
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2015
abstract
En este trabajo se describe un repositorio de diseños hardware y software empotrados de código abierto. El objetivo principal del repositorio es poner a disposición del público, en un estilo de código abierto, diseños y resultados de la comunidad académica/investigadora. SHORES (Software and Hardware Open Repository for Embedded Systems) aloja el código fuente de varios proyectos software y de diseño hardware que permiten dar soluciones empotradas a algunos problemas complejos en los campos de visión, bio-criptografía, procesamiento de señal, etc. Los recursos de SHORES están distribuidos bajo los términos de GNU General Public License, publicada por la Fundación para el Software Libre; ya sea la versión 2 de la licencia, o cualquier versión posterior.
Open Library of IP Module Interfaces for AMBA Bus
L. Acasandrei and A. Barriga
Conference · World Congress on Engineering WCE 2015
abstract
This paper describes the design of Intellectual Property (IP) modules of the most widely used communication standard interfaces, the AMBA bus. There is described the design of masters and slaves interface modules for APB, AHB, AXI and AXI-Stream buses. The IP modules presented can be used in systems with a variety of design constraints (low speed to high speed applications, low power consumption, etc). For the slave APB bus interfaces and the master/slave AHB a development environment for design and simulation based on the GRLIB library is provided.
Embedded Face Detection Application based on Local Binary Patterns
L. Acasandrei and A. Barriga
Conference · IEEE International Conference on Embedded Software and Systems ICESS 2014
abstract
pdf
In computer vision during the recent years a new paradigm for object detection has stimulated researchers and designers interest. The foundation of this new paradigm is the Local Binary Pattern (LBP) which is a nonparametric operator that efficiently extracts the features of local structures in images. This communication describes a software embedded implementation of LBP based algorithm for object detection, in particular targeting frontal face detection.
Diseño de una librería de módulos IP de interfaces con el bus AMBA
L. Acasandrei and A. Barriga
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2014
abstract
Esta comunicación describe el diseño de módulos IP (Intellectual Property) de la interfaz estándar de comunicación más utilizada, el bus AMBA. Se plantea el diseño de interfaces de módulos maestros y esclavos, para los buses APB, AHB, AXI y AXI-Stream. Los módulos IP que se presentan pueden emplearse en sistemas con una gran variedad limitaciones de diseño (baja velocidad hasta aplicaciones de alta velocidad de transmisión, bajo consumo de potencia, etc). Para las interfaces de bus APB esclavo y bus AHB maestro/esclavo se proporciona un entorno de desarrollo para el diseño y simulación basado en la librería GRLIB.
Hardware-Software Face Detection System based on Multi Block Local Binary Patterns
L. Acasandrei and A. Barriga
Conference · International Conference on Image, Vision and Computing ICIVC 2014
abstract
Face detection is an important aspect for biometrics, video surveillance and human computer interaction. Due to the complexity of the detection algorithms any face detection system requires a huge amount of computational and memory resources. In this communication an accelerated implementation of MB LBP face detection algorithm targeting low frequency, low memory and low power embedded system is presented. The resulted implementation is time deterministic and uses a customizable AMBA IP hardware accelerator. The IP implements the kernel operations of the MB-LBP algorithm and can be used as universal accelerator for MB LBP based applications. The IP employs 8 parallel MB-LBP feature evaluators cores, uses a deterministic bandwidth, has a low area profile and the power consumption is ~95 mW on a Virtex5 XC5VLX50T. The resulted implementation acceleration gain is between 5 to 8 times, while the hardware MB-LBP feature evaluation gain is between 69 and 139 times.
Face Identification Implementation in a Standalone Embedded System
L. Acasandrei, A. Barriga, M. Quintero and A. Ruiz
Conference · IEEE International Symposium on Industrial Electronics ISIE 2014
abstract
In this paper is described an embedded system for face identification. The system, running on FPGA, is built around LEON3 processor and consists of several IP Intellectual Property) modules designed as AMBA bus peripherals. The face detection is accelerated with the help of a hardware module while the face recognition is entirely executed in software. The face detection hardware accelerator module is reconfigurable and can share its internal resources (memory, multiplier, integer square root unit) with the LEON3 processor. The system has been designed on the criteria of resources optimization, low power consumption and improved operation speed.
Design Methodology for Face Detection Acceleration
L. Acasandrei and A. Barriga
Conference · IEEE Industrial Electronics Conference IECON 2013
abstract
pdf
A design methodology to accelerate the face detection for embedded systems is described, starting from high level (algorithm optimization) and ending with low level (software and hardware codesign) by addressing the issues and the design decisions made at each level based on the performance measurements and system limitations. The implemented embedded face detection system consumes very little power compared with the traditional PC software implementations while maintaining the same detection accuracy. The proposed face detection acceleration methodology is suitable for real time applications.
Sistema empotrado reconfigurable para aplicaciones de identificación de caras
L. Acasandrei, M. Quintero-Rodríguez, A. Ruiz-Ribes and A. Barriga-Barros
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2013
abstract
Se presenta un sistema empotrado sobre FPGA para detección/reconocimiento de caras basado en el procesador LEON3. El sistema está constituido por varios módulos IP (Intelectual Property) diseñados como periféricos del bus AMBA. El módulo de detección de caras es reconfigurable pudiendo operar en un modo de detección de caras o bien en un modo en el que sus recursos (memoria y operadores aritméticos) son utilizados por el procesador como componentes genéricos. El sistema ha sido diseñado aplicando criterios de optimización de consumo de potencia y velocidad de operación.
Embedded Face Detection Implementation
L. Acasandrei and A. Barriga
Conference · International Conference of the Biometrics Special Interest Group BIOSIG 2013
abstract
In this communication an embedded implementation of the Viola-Jones face detection algorithm targeting low frequency, low memory, and low power consumption, is presented. The design methodology, performance analysis and algorithm optimization in order to accelerate the face detection process, will be described.
Implementación sobre FPGA de un sistema de detección de caras basado en LEON3
L. Acasandrei and A. Barriga-Barrios
Conference · Iberchip XVIII Workshop IWS 2012
abstract
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En esta comunicación se presenta un sistema empotrado de detección de caras sobre FPGA. Con objeto de disponer de aceleración en el proceso de detección de caras se propone un sistema basado en técnicas de codiseño hardware/software. Se detalla el mecanismo de aceleración en la detección de caras. También se describe la implementación de un módulo IP que permite la aceleración hardware así como los resultados obtenidos.
FPGA implementation of an embedded face detection system based on LEON3
L. Acasandrei and A. Barriga-Barrios
Conference · International Conference on Image Processing, Computer Vision & Pattern Recognition IPCV 2012
abstract
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In this paper we present an FPGA face detection embedded system. In order achieve acceleration in the face detection process a hardware-software codesign technique is proposed. The paper describes the face detection acceleration mechanism. It also describes the implementation of an IP module that allows hardware acceleration.
Power-efficient focal-plane image representation for extraction of enriched Viola-Jones features
J. Fernández-Berni, L. Acasandrei, R. Carmona-Galán, A. Barriga-Barrios and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
abstract
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This paper describes the use of a reconfigurable focal-plane processing array in order to achieve an image representation which dramatically reduces the computational load of the Viola-Jones object detection framework. Additionally, such representation provides richer information than the simple sum of pixels within rectangular regions originally defined in this framework. As a result, more elaborated features could be devised to speed up the execution of the subsequent attentional cascade, boosting thus the performance of the whole algorithm. The proposed circuitry has been successfully implemented in a CMOS prototype smart imager. Experimental results are given, demonstrating the suitability of the approach presented to efficiently deliver enriched Viola-Jones features.
Accelerating Viola-Jones face detection for embedded and SoC environments
L. Acasandrei and A. Barriga
Conference · International Conference on Distributed Smart Cameras ICDSC 2011
abstract
pdf
In this communication a speed optimized implementation of Viola-Jones Face Detection Algorithm based on the baseline OpenCV face detection application is presented. The baseline OpenCV face detection application is analyzed. Then the necessary modifications and improvements are described in order to accelerate the execution speed in an embedded or SoC (System-on-Chip) environments. © 2011 IEEE.
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