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Author: Valentín Gutiérrez Gil
Year: Since 2002
Journal Papers
An adaptive simulation framework for AMS-RF test quality
V. Gutierrez ang G. Leger
Journal Paper · Integration, vol. 73, pp 10-17, 2020
abstract
doi pdf
Ensuring the quality of a circuit implies ensuring the quality of test. Despite the fact that performance-based testing has been the golden standard for Analog, Mixed-Signal and RF test for decades, high-reliability markets like automotive have found that functional test leaves some potential defects undetected that can produce in-field failure. There is thus a push towards defect-oriented testing which, in turn, calls for an efficient defect simulation framework. This paper presents a statistical adaptive defect simulation based on likelihood-weighted random sampling to evaluate the quality of AMS-RF tests in terms of defect coverage and fault escape. The adaptive loop takes a decision at each new defect simulation on whether it is more efficient to assess the defect coverage or the fault escape rate of the test under evaluation, as a function of the desired targets for these two metrics. Several decision criteria are proposed and validated by simulation of a complete IC for different tests.
Assessing AMS-RF test quality by defect simulation
V. Gutierrez, A. Gines and G. Leger
Journal Paper · IEEE Transactions on Device and Materials Reliability, vol. 19, no. 1, pp 55-63, 2019
abstract
doi
In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on practical cases of study that it is beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality. The computational burden of defect and fault simulations is taken into account and accurate statistical estimates of defect and fault escapes are provided to allow safe early stopping of the simulations.
Conferences
On the importance of bias-dependent charge injection for SET evaluation in AMS Circuits
V. Gutierrez and G. Leger
Conference · IEEE International New Circuits and Systems Conference NEWCAS 2020
abstract
Single Event Transients have become a serious issue in safety-critical applications of Analog and Mixed-Signal (AMS) circuits. Therefore, an evaluation must be carried out in order to diagnose the critical nodes but also to get an idea of the global sensitivity of the circuit, as a proxy to its experimental cross-section. In this work we evaluate two different top-down approaches considering or not the biasing of the impacted transistor to compute the injected charge. Performing an exhaustive evaluation campaign on a high performance buffer as a case of study, it will be shown that the error committed by the charge difference is greater than the one committed by simulating with the simple schematic without layout parasitics. However, the correlation between both approaches is high, so the critical nodes appear in the same order.
Adaptive defect simulation flow for Defect-oriented Test evaluation
V. Gutierrez and G. Leger
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
abstract
For AMS-RF circuits, functional test is usually considered the best way to test a circuit. By construction, it should detect any fault (i.e. performance loss) and consequently it does not require a-priori validation. However, defect-oriented strategies require an evaluation of the test quality prior to their implementation. This implies resorting to computationally intensive defect simulation campaigns. In this work, we propose an adaptive defect simulation loop that evaluates at each step the defect coverage and the fault escape rate of the test under validation and determines the best way to employ the computational power as a function of the test target metrics. That is to say, if it is better to simulate the performance setup to update the fault escape metric or, conversely, to simulate the proposed test setup to update the defect coverage metric.
SET sensitivity evaluation, a comparison before and after layout
V. Gutierrez and G. Leger
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
abstract
Single Events Transient can be a serious issue in safety-critical applications. Therefore, before the manufacturing process, an evaluation of the sensitivity of the whole circuit must be carried out to diagnose the most sensitive nodes and to assess the global sensitivity of the circuit. In this work we evaluate the importance of layout parasitics on the results of such an evaluation. Relying on a high performance buffer as a case of study, it will be shown that SET simulations at schematic level can be used for diagnosis and hardening purpose but that simulations should include both resistive and capacitive parasitics to reliably assess the global circuit sensitivity.
Single Event Transient injection in large mixed-signal circuits
V. Gutierrez and G. Leger
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2018
abstract
Abstract not avaliable
AMS-RF test quality: Assessing defect severity
V. Guiterrez, A. Gines and G. Leger
Conference · IEEE Int. Symposium on On-Line Testing and Robust System Design IOLTS 2018
abstract
In safety critical applications there is a demand for
estimating defect coverage in order to meet stringent quality
levels. However, defect simulation of complex AMS-RF circuits
is computationally expensive since achieving good confidence
interval requires sampling many defects. In this paper, we
show on a practical case of study that it may be beneficial to
complement defect coverage with fault coverage and assess the
severity of defect escapes to get a complete picture of test quality.
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