The project aims to develop a complete, open-source Electronic Design Automation (EDA) flow for the digital design of Systems-on-Chip (SoCs), targeting advanced technology nodes in the 65-28 nm range. This project will reduce Europe’s reliance on costly EDA tools provided by Asian and North American companies, creating accessible alternatives for research and SMEs while lowering costs associated with industrial design flows. The primary objective is to provide an integrated design flow-spanning from high-level specifications to GDSII-that enables the automated generation of ASICs, taking the process from C/C++ code to physical design. To achieve this, the project will enhance the quality, stability, and reliability of core EDA tools, providing more accurate timing models and dynamic power estimates. Tool interoperability and flow orchestration will be improved through standardized APIs, ensuring sustainable and reproducible design flows. The CSIC team will play an active role, contributing significantly in the areas of advanced packaging and chip-to-chip communication through open Application Design Kits (ADKs) and physical demonstrators. Furthermore, the CSIC team will lead the validation of the tools through rigorous testing and two chip fabrication runs (tapeouts).
