Since its inception in 1989, the Institute of Microelectronics of Seville (IMSE) has specialized in the design and testing of integrated circuits for a wide range of applications and technologies. Experience has shown that designing an Application-Specific Integrated Circuit (ASIC) is not always justified, as it demands significant human effort and long development times (often spanning years)-resources that R&D&I stakeholders frequently cannot commit, usually due to the need for rapid product development. To reduce these timeframes, the industry has developed System-in-Package (SiP) technology, which involves configuring a complete system from basic building blocks-such as ICs based on the same or different technologies-and assembling and packaging them as a single chip. This approach strikes a balance between discrete electronics (characterized by short development times but low integration levels) and ASIC design (offering extremely compact size but requiring much longer development cycles). Leveraging funding from the PERTE-CHIP initiative, the IMSE has established an Advanced Packaging Prototyping Line to equip the Spanish semiconductor ecosystem with the infrastructure and tools needed to design, manufacture, and validate these types of systems. The project aims to address all aspects of the complete System-in-Package (SiP) manufacturing workflow-ranging from initial circuit schematic conception and electrical, mechanical, and thermal verification (utilizing open-source tools whenever possible) to final fabrication and validation. Systems-in-Package allow for multiple configurations depending on the application, available primitives (bare dies), and interconnection geometries and substrates; examples include 2.5D and 3D integration, Chiplets, MCMs, and COB (Chip-on-Board) technologies. Interconnection methods-utilizing organic substrates, ceramics, interposers, etc.-offer numerous variations to explore and will constitute a key objective of the project. The system design process will require exploring various simulation tools capable of addressing issues such as thermal dissipation and proper power distribution-factors not typically encountered in standard ASIC design flows-given the high level of integration involved. Managing the interplay between tools and multiphysics variables throughout the design flow will be a critical challenge to address during the project. The project also plans to delve deeply into device validation, as the semiconductor industry lacks a universal paradigm for validating this type of system during manufacturing. While final validation does not differ significantly from that of an ASIC or conventional system, the method for breaking validation down into a step-by-step process during assembly remains unresolved; the degree of optimization will depend heavily on the system configuration and the assembly techniques employed. The specific steps of this process will also be determined by the assembly and validation equipment available on the Prototyping Line. The project aims to gain expertise in optimizing the partitioning process from the early design stages by planning an integrated approach to the three fundamental aspects of SiP conception. Two SiP demonstrators will be developed, incorporating various assembly alternatives to address the challenges identified during the design, assembly, and validation phases.
