Found results matching for:
Author: Santiago Sánchez Solano
Year: Since 2002
Journal Papers
Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management
S. Sánchez-Solano, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 24, no. 17, article 5674, 2024
abstract
doi
The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4
configurable logic blocks (CLBs) to accommodate the RO bank.
Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 7, no.2, article 29, 2023
abstract
doi
The advent of quantum computing with high processing capabilities will enable brute force attacks in short periods of time, threatening current secure communication channels. To mitigate this situation, post-quantum cryptography (PQC) algorithms have emerged. Among the algorithms evaluated by NIST in the third round of its PQC contest was the NTRU cryptosystem. The main drawback of this algorithm is the enormous amount of time required for the multiplication of polynomials in both the encryption and decryption processes. Therefore, the strategy of speeding up this algorithm using hardware/software co-design techniques where this operation is executed on specific hardware arises. Using these techniques, this work focuses on the acceleration of polynomial multiplication in the encryption process for resource-constrained devices. For this purpose, several hardware multiplications are analyzed following different strategies, taking into account the fact that there are no possible timing information leaks and that the available resources are optimized as much as possible. The designed multiplier is encapsulated as a fully reusable and parametrizable IP module with standard AXI4-Stream interconnection buses, which makes it easy to integrate into embedded systems implemented on programmable devices from different manufacturers. Depending on the resource constraints imposed, accelerations of up to 30-45 times with respect to the software-level multiplication runtime can be achieved using dedicated hardware, with a device occupancy of around 5%.
On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 23, no. 8, article 4070, 2023
abstract
doi
The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive set of on-line tests to obtain the metrics that determine its quality in terms of uniqueness, reliability, and entropy characteristics. The results obtained prove that the proposed module is a suitable candidate for various security applications. As an example, an implementation that uses less than 5% of the resources of a low-cost programmable device is capable of obfuscating and recovering 512-bit cryptographic keys with virtually zero error rate.
True Random Number Generation Capability of a Ring Oscillator PUF for Reconfigurable Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Electronics, vol. 11, no. 23, article 4028, 2022
abstract
doi
This paper presents the validation of a novel approach for a true-random number generator (TRNG) based on a ring oscillator-physical unclonable function (RO-PUF) for FPGA devices. The proposal takes advantage of the different noise sources that affect the electronic implementation of the RO-PUF to extract the entropy required to guarantee its function as a TRNG, without anything more than minimal changes to the original design. The new RO-PUF/TRNG architecture has been incorporated within a hybrid HW/SW embedded system designed for devices from the Xilinx Zynq-7000 family. The degree of randomness of the generated bit streams was assessed using the NIST 800-22 statistical test suite, while the validation of the RO-PUF proposal as an entropy source was carried out by fulfilling the NIST 800-90b recommendation. The features of the hybrid system were exploited to carry out the evaluation and validation processes proposed by the NIST publications, online and on the same platform. To establish the optimal configuration to generate bit streams with the appropriate entropy level, a statistical study of the degree of randomness was performed for multiple TRNG approaches derived from the different implementation modes and configuration options available on the original RO-PUF design. The results show that the RO-PUF/TRNG design is suitable for secure cryptographic applications, doubling its functionality without compromising the resource-efficiency trade-off already achieved in the design.
Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems
M.C. Martínez-Rodríguez, L.F. Rojas-Muñoz, E. Camacho-Ruiz, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 6, no.4, article 51, 2022
abstract
doi
The generation of unique identifiers extracted from the physical characteristics of the underlying hardware ensures the protection of electronic devices against counterfeiting and provides security to the data they store and process. This work describes the design of an efficient Physical Unclonable Function (PUF) based on the differences in the frequency of Ring Oscillators (ROs) with identical layout due to variations in the technological processes involved in the manufacture of the integrated circuit. The logic resources available in the Xilinx Series-7 programmable devices are exploited in the design to make it more compact and achieve an optimal bit-per-area rate. On the other hand, the design parameters can also be adjusted to provide a high bit-per-time rate for a particular target device. The PUF has been encapsulated as a configurable Intellectual Property (IP) module, providing it with an AXI4-Lite interface to ease its incorporation into embedded systems in combination with soft- or hard-core implementations of general-purpose processors. The capability of the proposed RO-PUF to generate implementation-dependent identifiers has been extensively tested, using a series of metrics to evaluate its reliability and robustness for different configuration options. Finally, in order to demonstrate its utility to improve system security, the identifiers provided by RO-PUFs implemented on different devices have been used in a Helper Data Algorithm (HDA) to obfuscate and retrieve a secret key.
Hardware/Software Co-Design of a Circle Detection System based on Evolutionary Computing
L.F. Rojas-Munoz, H. Rostro-Gonzalez, C.H. Garcia-Capulin and S. Sanchez-Solano
Journal Paper · Electronics, vol. 11, no. 17, article 2686, 2022
abstract
doi
In recent years, the strategy of co-designing Hardware/Software (HW/SW) systems has been widely adopted to exploit the synergy between both approaches thanks to technological advances that have led to more powerful devices providing an increasingly better cost-benefit trade-off. This paper presents an HW/SW system for the detection of multiple circles in digital images based on a genetic algorithm. It is implemented on an Ultra96-v2 development board, which contains a Xilinx Zynq UltraScale+ MPSoC device and supports a Linux operating system that facilitates application development. The design is powered by developing an interactive computing environment by means of the Jupyter Notebook platform, in which different programming languages coexist. The specific advantages of each of these languages have been used to describe the hardware component that accelerates the evolutionary computation for circle detection (VHDL), to execute SW-HW interaction functions, as well as the pre- and post-processing of the images (ANSI-C) and to code, evaluate, and document the system execution process (Python). As a result, a computationally efficient application was obtained, with high accuracy in the detection of circles in synthetic and real images, and with a high degree of reconfigurability that provides the user with the necessary tools to incorporate it in a specific area of interest.
Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems
S. Sánchez-Solano, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 22, no. 5, article 2057, 2022
abstract
doi
Concern for the security of embedded systems that implement IoT devices has become a crucial issue, as these devices today support an increasing number of applications and services that store and exchange information whose integrity, privacy, and authenticity must be adequately guaranteed. Modern lattice-based cryptographic schemes have proven to be a good alternative, both to face the security threats that arise as a consequence of the development of quantum computing and to allow efficient implementations of cryptographic primitives in resource-limited embedded systems, such as those used in consumer and industrial applications of the IoT. This article describes the hardware implementation of parameterized multi-unit serial polynomial multipliers to speed up time-consuming operations in NTRU-based cryptographic schemes. The flexibility in selecting the design parameters and the interconnection protocol with a general-purpose processor allow them to be applied both to the standardized variants of NTRU and to the new proposals that are being considered in the post-quantum contest currently held by the National Institute of Standards and Technology, as well as to obtain an adequate cost/performance/security-level trade-off for a target application. The designs are provided as AXI4 bus-compliant intellectual property modules that can be easily incorporated into embedded systems developed with the Vivado design tools. The work provides an extensive set of implementation and characterization results in devices of the Xilinx Zynq-7000 and Zynq UltraScale+ families for the different sets of parameters defined in the NTRUEncrypt standard. It also includes details of their plug and play inclusion as hardware accelerators in the C implementation of this public-key encryption scheme codified in the LibNTRU library, showing that acceleration factors of up to 3.1 are achieved when compared to pure software implementations running on the processing systems included in the programmable devices.
Embedded system implementation of an evolutionary algorithm for circle detection on programmable devices
L.F.Rojas-Muñoz, S. Sánchez-Solano, C.H.García-Capulín and H. Rostro-González
Journal Paper · Computers & Electrical Engineering, vol. 99, article 107714, 2022
abstract
doi
Programmable devices combine powerful processing systems with a rich infrastructure of general-purpose and specific logic blocks, making it possible the efficient implementation of embedded systems to perform complex tasks by facilitating hardware acceleration of critical stages to improve their performance. Based on these characteristics, a hardware implementation of a genetic algorithm for circle detection in digital images is described in this paper. The detection system has been designed for Xilinx Zynq-7000 and Zynq UltraScale+ family devices and implemented on two low-cost development boards that reach acceleration factors of 33.12 and 37.3, respectively, when compared to the fully software implementation. Detection results from both development boards have been compared using synthetic and real images from different scenarios. The accuracy and performance achieved demonstrate the suitability of this proposal to design embedded systems with restricted size, resources and energy consumption for applications in Internet of Things, Industry 4.0 and other related paradigms.
Módulo de inferencia difuso con base de conocimientos variable sobre hardware reconfigurable
A.J. Cabrera-Sarmiento, S. Sánchez-Solano and Y. García-Guirola
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 42, no. 2, pp 34-54, 2021
abstract
En este artículo se presenta el desarrollo de un módulo de inferencia difuso (FIM, por sus siglas en inglés) implementado sobre hardware reconfigurable con capacidad de modificar dinámicamente su base de conocimientos. El FIM original se diseña utilizando el entorno de desarrollo de sistemas difusos Xfuzzy, el cual permite la generación de código en lenguaje de descripción de hardware VHDL para la arquitectura del FIM. Posteriormente se modifica el código VHDL para añadir sendos puertos con las señales de dirección, datos y control de lectura/escritura a las memorias de antecedentes y de reglas que contienen la base de conocimientos. El FIM modificado se encapsula en un módulo de propiedad intelectual siguiendo dos posibles opciones, realizando en cada caso las interconexiones correspondientes, de forma tal que desde un sistema de procesamiento empotrado en el mismo dispositivo se pueda acceder a estas memorias a través de los puertos añadidos, posibilitando la modificación de sus contenidos en tiempo de operación. Las implementaciones fueron realizadas sobre dos tipos de dispositivos de hardware reconfigurable: un FPGA Spartan-3E1600, utilizando un sistema de procesamiento basado en el softcore Microblaze y el entorno de desarrollo ISE/EDK; así como sobre un SoC-FPGA Zynq-7Z010, utilizando su sistema de procesamiento hardcore basado en ARM y el entorno de desarrollo Vivado, comprobándose la modificación dinámica de la base de conocimientos del FIM. Las modificaciones realizadas facilitan el ajuste de la base de conocimientos de un controlador difuso híbrido hardware/software durante su etapa de desarrollo así como la implementación de un controlador difuso adaptativo.
A Configurable RO-PUF for Securing Embedded Systems Implemented on Programmable Devices
M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Brox and S. Sánchez-Solano
Journal Paper · Electronics, vol. 10, no. 16, article 1957, 2021
abstract
doi pdf
Improving the security of electronic devices that support innovative critical services (digital administrative services, e-health, e-shopping, and on-line banking) is essential to lay the foundations of a secure digital society. Security schemes based on Physical Unclonable Functions (PUFs) take advantage of intrinsic characteristics of the hardware for the online generation of unique digital identifiers and cryptographic keys that allow to ensure the protection of the devices against counterfeiting and to preserve data privacy. This paper tackles the design of a configurable Ring Oscillator (RO) PUF that encompasses several strategies to provide an efficient solution in terms of area, timing response, and performance. RO-PUF implementation on programmable logic devices is conceived to minimize the use of available resources, while operating speed can be optimized by properly selecting the size of the elements used to obtain the PUF response. The work also describes the interface added to the PUF to facilitate its incorporation as hardware Intellectual Property (IP)-modules into embedded systems. The performance of the RO-PUF is proven with an extensive battery of tests, which are executed to analyze the influence of different test strategies on the PUF quality indexes. The configurability of the proposed RO-PUF allows establishing the most suitable ‘cost/performance/security-level’ trade-off for a certain application.
Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm
E. Camacho-Ruiz, S. Sánchez-Solano, P. Brox and M.C. Martínez-Rodríguez
Journal Paper · ACM Journal on Emerging Technologies in Computing Systems, vol. 17, no. 3, article 35, 2021
abstract
doi
Post-quantum cryptographic algorithms have emerged to secure communication channels between electronic devices faced with the advent of quantum computers. The performance of post-quantum cryptographic algorithms on embedded systems has to be evaluated to achieve a good trade-off between required resources (area) and timing. This work presents two optimized implementations to speed up the NTRUEncrypt algorithm on a system-on-chip. The strategy is based on accelerating the most time-consuming operation that is the truncated polynomial multiplication. Hardware dedicated modules for multiplication are designed by exploiting the presence of consecutive zeros in the coefficients of the blinding polynomial. The results are validated on a PYNQ-Z2 platform that includes a Zynq-7000 SoC from Xilinx and supports a Python-based programming environment. The optimized version that exploits the presence of double, triple, and quadruple consecutive zeros offers the best performance in timing, in addition to considerably reducing the possibility of an information leakage against an eventual attack on the device, making it practically negligible.
Speeding up elliptic curve arithmetic on ARM processors using NEON instructions
R. Cuiman-Márquez, A.J. Cabrera Sarmiento and S. Sánchez-Solano
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 41, no. 3, pp 1-20, 2020
abstract
This paper studies the use of NEON instructions for the implementation of elliptic curve cryptographic primitives on ARM Cortex-A processors. Starting from the analysis of point arithmetic formulas in different coordinate systems it was possible to identify several operations with no data dependency. Then, these operations were conveniently grouped in pairs to perform them in parallel using the NEON engine. Following this approach, dual NEON-based multiplications and squarings in the finite field ¿¿¿¿ are proposed. Furthermore, these dual ¿¿¿¿ operations are also used to speed up multiplications and squarings over the field extension ¿¿¿¿2. Finally, after integrating them into the point addition and point doubling formulas, we measure their impact on the execution time of scalar multiplications on elliptic curves defined over both finite fields. By using a mixed C/NEON implementation approach our solution is easily scalable at run time to support different curve sizes. Experiments conducted on the ARM Cortex-A9 processing system embedded in the Xilinx XC7Z020 device reported performance improvements of the NEON-based scalar multiplication between 32% and 38% and between 9% and 34% compared to a conventional implementation of the same operation on 254-bit, 384-bit and 510-bit curves over ¿¿¿¿ and ¿¿¿¿2 respectively.
Implementación de un detector de movimiento para cámaras inteligentes sobre sistemas embebidos
L.M. Garcés-Socarrás, R. Sánchez-Correa, A.J. Cabrera Sarmiento, S. Sánchez-Solano and P. Brox Jiménez
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 41, no. 13, pp 53-65, 2020
abstract
Este artículo describe la implementación sobre hardware reconfigurable de un detector de movimiento para cámaras inteligentes el cual puede ser empleado en varios campos de aplicación. El sistema propuesto detecta el movimiento en una secuencia de vídeo identificando la región de interés para reducir el tiempo de procesado de los algoritmos de análisis e identificación posteriores. Como parte de este trabajo se realizan tres módulos de detección de movimiento basados en el modelo planteado por Reichardt & Hassenstein para la detección bioinspirada de movimiento elemental, así como otros módulos auxiliares. Estos bloques han sido incorporados a la biblioteca de procesado de imágenes y vídeos XIL XSGImgLib, la cual permite simplificar y reducir el tiempo de diseño de las aplicaciones de procesado de imágenes y vídeos sobre los FPGA y SoC FPGA de Xilinx. Para la comprobación de los detectores se presenta una aplicación de detección de movimiento para un flujo espaciotemporal de vídeo, proveniente de un punto de control de tráfico vehicular, en un FPGA Spartan-6 LX45, arrojando mejoras en el tiempo de ejecución de la implementación del bloque de detección de movimiento elemental comparado con desarrollos similares reportados en la literatura consultada.
Hardware Implementation of Authenticated Ciphers for Embedded Systems
M.C. Martínez-Rodríguez, S. Sauro, P. Brox and S. Sánchez-Solano
Journal Paper · IEEE Latin America Transactions, vol. 18, no. 9, pp 1581-1591, 2020
abstract
The demand for embedded systems in applications that handle critical or private information has strongly focused designers' attention on the security aspects of this kind of system. Using the C programs and HDL descriptions available in the repositories of the CAESAR Competition and the ATHENa Project, this work presents a design flow that eases the development and evaluation of different solutions for the hardware implementation of authenticated ciphers and their incorporation as accelerating peripherals in embedded systems for different application cases. Three ciphers, finalists in the different categories established in the contest, have been analyzed, although the described approaches can be applied to any of the proposals submitted to the CAESAR Competition. A Zybo-Z7 development board that incorporates a Zynq-7000 device from Xilinx, which combines programmable logic from the FPGAs of the 7-Series with a dual-core Cortex-A9 ARM processing system, has been used as hardware platform in all the designs. The Vivado environment has been employed to perform the different stages of synthesis and verification necessary to carry out the implementation of the cipher, its conversion into an IP module, and its integration in an embedded system using different interconnection schemes that allow establishing cost/performance tradeoffs for different applications.
Implementing Cryptographic Pairings on ARM dual-core Processors
R. Caiman, A. Cabrera and S. Sanchez-Solano
Journal Paper · IEEE Latin America Transactions, vol. 18, no. 2, pp 232-240, 2020
abstract
doi
In this paper, we explore the parallelization capabilities of the ARM processing system embedded in a Zynq device for a software implementation of the optimal Ate pairing. First, the use of the NEON coprocessor was evaluated. It was found that on ARM v7 Cortex-A9 processors the computation of the optimal Ate pairing based on NEON does not perform better than an optimized ARM-assembly equivalent implementation. Therefore, we moved to explore the parallelization of pairing computation using a dual-core processing approach. By organizing operations of line evaluation and point arithmetic formulas to have little data dependency, it was possible to schedule independent operations to be perfomed simultaneously in separate cores of an ARM dual-core Cortex-A9 processor. The same principle was applied in the arithmetic procedures of the extension fields. In this way, our software is able to perform 25.6% and 6.6% faster than the best two implementations previously reported on ARM Cortex-A9 processors.
Self-modifiable image processing library for model-based design on FPGAs
L. Garces-Socarras, A. Cabrera, S. Sanchez-Solano, P. Brox, E. Ieno and T. Pimenta
Journal Paper · IEEE Latin America Transactions, vol. 17, no. 5, pp 742-750, 2019
abstract
doi
This paper describes highly configurable hardware modules, included in XIL XSGImgLib library, capable of speed up the hardware implementation of video and image processing systems using the model-based design flow provided by Xilinx System Generator. As part of this work, generic architectures were developed to exploit specific characteristics of some processing blocks, which can be self-modified using a novel software procedure developed for MATLAB (R). This procedure, along with the generic architecture and the configuration options, allows the abstraction about the specific details of the hardware implementation, as well as the adjustment of the resources consumption of the high-speed image and video processing application for embedded systems with weight, volume and power consumption constrains like smart cameras, video surveillance and autonomous vehicles. The use of this video and image processing library is illustrated by the development of a segmentation application on a Spartan-6 LX45 FPGA although any Xilinx's FPGA is supported.
Memory Tampering Attack on Binary GCD Based Inversion Algorithms
A.C. Aldaya, B.B. Brumley, A.J.C. Sarmiento and S. Sánchez-Solano
Journal Paper · International Journal of Parallel Programming, vol. 47, no. 4, pp 621-640, 2019
abstract
doi
In the field of cryptography engineering, implementation-based attacks are a major concern due to their proven feasibility. Fault injection is one attack vector, nowadays a major research line. In this paper, we present how a memory tampering-based fault attack can be used to severely limit the output space of binary GCD based modular inversion algorithm implementations. We frame the proposed attack in the context of ECDSA showing how this approach allows recovering the private key from only one signature, independent of the key size. We analyze two memory tampering proposals, illustrating how this technique can be adapted to different implementations. Besides its application to ECDSA, it can be extended to other cryptographic schemes and countermeasures where binary GCD based modular inversion algorithms are employed. In addition, we describe how memory tampering-based fault attacks can be used to mount a previously proposed fault attack on scenarios that were initially discarded, showing the importance of including memory tampering attacks in the frameworks for analyzing fault attacks and their countermeasures.
Model-based implementation of self-configurable intellectual property modules for image histogram calculation in FPGAs
L.M. Garcés-Socarrás, D.A. Romero, A.J. Cabrera, S. Sánchez-Solano and P. Brox
Journal Paper · Ingeniería e Investigación, vol. 37, no. 2, pp 74-81, 2017
abstract
doi pdf
This work presents the development of self-modifiable Intellectual Property (IP) modules for histogram calculation using the modelbased design technique provided by Xilinx System Generator. In this work, an analysis and a comparison among histogram calculation architectures are presented, selecting the best solution for the design flow used. Also, the paper emphasizes the use of generic architectures capable of been adjustable by a self configurable procedure to ensure a processing flow adequate to the application requirements. In addition, the implementation of a configurable IP module for histogram calculation using a model-based design flow is described and some implementation results are shown over a Xilinx FPGA Spartan-6 LX45.
SPA vulnerabilities of the binary extended Euclidean algorithm
A. Cabrera Aldaya, A.J. Cabrera Sarmiento and S. Sánchez-Solano
Journal Paper · Journal of Cryptographic Engineering, vol. 7, no. 4, pp 273-285, 2017
abstract
doi
The execution flow of the binary extended Euclidean algorithm (BEEA) is heavily dependent on its inputs. Taking advantage of that fact, this work presents a novel simple power analysis (SPA) of this algorithm that reveals some exploitable power consumption-related leakages. The exposed leakages make it possible to retrieve some bits of the algorithm´s secret input without profiling the target device. The identified vulnerabilities can be exploited in many cryptographic protocols where the modular inversion operation is applied to a secret argument. In this work, the ECDSA protocol is used to exemplify how the presented SPA can be used to disclose in about 2 min all standardized private key sizes using less than 800 traces. In the context of ECDSA, a countermeasure previously proposed to mitigate a timing leakage during scalar multiplication is also analyzed, showing that, when it is improperly implemented, it enhances the proposed bit recovery method. Three countermeasures for removing SPA leakages from a BEEA implementation are also analyzed.
Side-channel analysis of the modular inversion step in the RSA key generation algorithm
A. Cabrera Aldaya, R. Cuiman Márquez, A.J. Cabrera Sarmiento and S. Sánchez-Solano
Journal Paper · International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 199-213, 2017
abstract
doi pdf
This paper studies the security of the RSA key generation algorithm with regard to side-channel analysis and presents a novel approach that targets the simple power analysis (SPA) vulnerabilities that may exist in an implementation of the binary extended Euclidean algorithm (BEEA). The SPA vulnerabilities described, together with the properties of the values processed by the BEEA in the context of RSA key generation, represent a serious threat for an implementation of this algorithm. It is shown that an adversary can disclose the private key employing only one power trace with a success rate of 100 % - an improvement on the 25% success rate achieved by the best side-channel analysis carried out on this algorithm. Two very different BEEA implementations are analyzed, showing how the algorithm's SPA leakages could be exploited. Also, two countermeasures are discussed that could be used to reduce those SPA leakages and prevent the recovery of the RSA private key.
Modificación automática de arquitecturas de módulos hardware de procesado de imágenes
L.M. Garcés-Socarrás, A.J. Cabrera-Sarmiento, S. Sánchez-Solano, P. Brox-Jiménez, E. Ieno and T. Cleber-Pimenta
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 37, no. 3, pp 21-23, 2016
abstract
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El presente artículo describe el empleo del flujo de diseño basado en modelos para el desarrollo de bloques reconfigurables automáticamente para el procesado de imágenes sobre FPGA. Para ello se han concebido arquitecturas hardware que aprovechan características específicas de algunos algoritmos de procesado y que pueden ser modificadas a través de un novedoso procedimiento software. Este aspecto, unido a las restantes opciones de parametrización de los diferentes módulos, permite liberar al diseñador de los detalles específicos de las implementaciones hardware así como adaptar el consumo de recursos del FPGA a las necesidades de la aplicación. El proceso de reconfiguración automática se ilustra con el bloque de convolución genérico.
Low-cost dedicated hardware IP modules for background subtraction in embedded vision systems
E. Calvo-Gallego, P. Brox and S. Sanchez-Solano
Journal Paper · Journal of Real-Time Image Processing, vol. 12, no. 4, pp 681-695, 2016
abstract
doi
This paper presents the design and implementation of dedicated hardware IP modules for background subtraction, which are suitable to be implemented in embedded vision systems and are efficient in terms of performance, resource consumption, and operational speed. To achieve this goal, a comprehensive experimental study of different algorithms has been carried out by evaluating a wide range of quality parameters. From the results of this analysis, five candidate algorithms were selected and implemented using a model-based design methodology supported by Matlab and Xilinx FPGA tools. Using only the internal block memory available in the FPGA, they provide adequate solutions for processing low-resolution images with CIF and QCIF formats.
AES T-Box tampering attack
A. Cabrera-Aldaya, A.J. Cabrera-Sarmiento and S. Sánchez-Solano
Journal Paper · Journal of Cryptographic Engineering, vol. 6, no. 1, pp 31-48, 2016
abstract
doi pdf
The use of embedded block memories (BRAMs) in Xilinx FPGA devices makes it possible to store the T-Boxes that are employed to implement the AES block cipher's SubBytes and MixColumns operations. Several studies into BRAM resistance to side-channel attacks have been reported in the literature, whereas this paper presents a novel attack based on tampering the BRAMs storing the T-Boxes. This approach allows recovering the key using a ciphertext-only attack for all AES key sizes. The complexity of the attack makes it completely feasible. The attack was mounted against previously reported FPGA-based AES implementations, taking into account the different design criteria used in each case and focusing mainly on the implementation of the final round of the AES algorithm, which plays a crucial role in the analysis. Three different final round implementations extracted from well-known existing architectures are analyzed in this work. The paper also discusses some countermeasures with regard to security, performance and FPGA resource utilization. The attack is presented against FPGA-based implementations but it can be extended to software architectures as well.
Edge-adaptive spatial video de-interlacing algorithms based on fuzzy logic
P. Brox, I. Baturone, S. Sánchez-Solano and J. Gutiérrez-Ríos
Journal Paper · IEEE Transactions on Consumer Electronics, vol. 60, no. 3, pp. 375-383, 2014
abstract
doi pdf
Since the human visual system is especially sensitive to image edges, edge-dependent spatial interpolators have been proposed in literature as a means of successfully restoring edges while avoiding the staircase effect of linear spatial algorithms. This paper addresses the application of video de-interlacing, which constitutes an indispensable stage in video format conversion. Classic edge-adaptive de-interlacing algorithms introduce annoying artifacts when the edge directions are evaluated incorrectly. This paper presents two ways of exploiting fuzzy reasoning to reinforce edges without an excessive increase in computational complexity. The performance of the proposed algorithms is analyzed by deinterlacing a wide set of test sequences. The study compares the two proposals both with each other and with other edge-adaptive de-interlacing methods reported in the recent literature.
Fuzzy logic-based embedded system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · Applied Soft Computing, vol. 14, part C, pp 338-346, 2014
abstract
doi pdf
Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time.
Prototipado rápido de sistemas de procesado de vídeo basados en el VFBC de Xilinx
L.M. Garcés, S. Sánchez-Solano, P. Brox and A.J. Cabrera
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. XXXIV, no. 1, pp 100-109, 2013
abstract
pdf
This paper develops hardware modules for rapid prototyping of video processing systems based on the Xilinx video frame buffer controller (VFBC). This implementation allows the storage of video frames in memory external to the programmable device, as well as its proper handle for designing spatio-temporal processing systems using the Xilinx System Generator model-based design flow. The hardware modules are responsible for the configuration and control of writing and reading VFBC interfaces, as well as the manipulation of video synchronization signals for interconnecting input and output peripherals.
The article also include the description of the elaborated modules and the analysis of the results of its use for the development of a temporal video processing demonstrator using a simple motion detector on a Spartan-6 SP605 Evaluation Platform board.
Library for model-based design of image processing algorithms on FPGAs
L.M. Garcés-Socarrás, S. Sánchez-Solano, P. Brox and A.J. Cabrera
Journal Paper · Revista Facultad de Ingenieria, no. 68, pp 36-47, 2013
abstract
pdf
This paper describes a library (XSGImgLib) that includes parameterizable blocks to implement low-level image processing tasks on FPGAs. A modelbased design technique provided by Xilinx System Generator (XSG) has been used to design the blocks, which implement point operation (binarization) and neighborhood operations (linear and non-linear filtering) in grayscale images. The blocks are parameterizable for input/output data precision, window size, normalization strategy, and implementation options (area versus speed optimization). The paper includes the implementation results obtained after fixing these options and exemplifies the combination of several blocks of the library to build a complete design for image segmentation purposes.
Model-Based Design Methodology for Rapid Development of Fuzzy Controllers on FPGAs
S. Sánchez-Solano, M. Brox, E. del Toro, P. Brox and I. Baturone
Journal Paper · IEEE Transactions on Industrial Informatics, vol. 9, no. 3, pp 1361-1370, 2013
abstract
doi pdf
The complexity reached by current applications of industrial control systems has motivated the development of new computational paradigms, as well as the employment of hybrid implementation techniques that combine hardware and software components to fulfill system requirements. On the other hand, continuous improvements in field-programmable devices today make possible the implementation of complex control systems on reconfigurable hardware, although they are limited by the lack of specific design tools and methodologies to facilitate the development of new products. This paper describes a model-based design approach for the synthesis of embedded fuzzy controllers on field-programmable gate arrays (FPGAs). Its main contributions are the proposal of a novel implementation technique, which allows accelerating the exploration of the design space of fuzzy inference modules, and the use of a design flow that eases their integration into complex control systems and the joint development of hardware and software components. This design flow is supported by specific tools for fuzzy systems development and standard FPGA synthesis and implementation tools, which use the modeling and simulation facilities provided by the Matlab environment. The development of a complex control system for parking an autonomous vehicle demonstrates the capabilities of the proposed procedure to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy controllers for industrial applications.
CAD Tools for Hardware Implementation of Embedded Fuzzy Systems on FPGAs
M. Brox, S. Sánchez-Solano, E. del Toro, P. Brox and F.J. Moreno-Velo
Journal Paper · IEEE Transactions on Industrial Informatics, vol. 9, no. 3, pp 1635-1644, 2013
abstract
doi pdf
This paper describes two computer-aided design (CAD) tools for automatic synthesis of fuzzy logic-based inference systems. The tools share a common architecture for efficient hardware implementation of fuzzy modules, but are based on two different design strategies. One of them is focused on the generation of standard VHDL code, which can be later implemented on a reconfigurable device [field-programmable gate array (FPGA)] or as an application-specific integrated circuit (ASIC). The other one uses the Matlab/Simulink environment and tools for development of digital signal processing (DSP) systems on Xilinx's FPGAs. Both tools are included in the last version of Xfuzzy, which is a specific environment for designing complex fuzzy systems, and they provide interfaces to commercial VHDL synthesis and verification tools, as well as to conventional FPGA development environments. As demonstrated by the included design example, the proposed development strategies speed up the stages of description, synthesis, and functional verification of embedded fuzzy inference systems.
Implementación híbrida hardware software del algoritmo de detección de rostros de Viola-Jones sobre FPGA
E. del Toro, A. Cabrera and S. Sánchez-Solano
Journal Paper · Universidad Ciencia y Tecnología, vol. 16, no. 63, pp 114-124, 2012
abstract
En este trabajo se describe el diseño e implementación de un sistema que se utilizará para realizar la detección de rostros siguiendo el algoritmo propuesto por P. Viola y M. Jones. En el diseño se ha utilizado una placa que contiene un FPGA Virtex-II Pro acoplado con un sensor de visión tipo CMOS. Se han implementado estructuras hardware que permiten la aceleración de la ejecución de este algoritmo en un 37%. Una de las ventajas de este diseño radica en la posibilidad de utilizar imágenes con un tamaño variable para realizar la detección de rostros.
Enabling fuzzy technologies in high performance networking via an open FPGA-based development platform
F.M. Pouzols, A. Barriga-Barros, D.R. López and S. Sánchez-Solano
Journal Paper · Applied Soft Computing, vol. 12, no. 4, pp 1440-1450, 2012
abstract
doi pdf
Soft computing techniques and particularly fuzzy inference systems are gaining momentum as tools for network traffic modeling, analysis and control. Efficient hardware implementations of these techniques that can achieve real-time operation in high-speed networking equipment as well as other highly time-constrained application fields is however an open problem. We introduce a development platform for fuzzy inference systems with applications to network traffic analysis and control. The platform addresses the current requirements and constraints of high performance networking equipment. For the development process, we set up a methodology and a CAD tool chain that span the entire design process from initial specification in a high-level language to implementation on FPGA devices. An FPGA development board with PCI/PCIe interface is employed to support an open platform that comprises CAD tools as well as IP cores. PCI compatible fuzzy inference modules are implemented as System-on-Programmable-Chip (SoPC). We present satisfactory experimental results from the implementation of fuzzy systems for a number of applications in analysis and control of Internet traffic. These systems are shown to satisfy operational and architectural requirements of current and future high performance routing equipment. The platform proposed allows for the development of prototypes while avoiding large investments and complicated management procedures which constrain the testing and adoption of soft computing techniques in high performance networking. © 2011 Elsevier B.V. All rights reserved.
Characterization and Modelling of Circular Piezoelectric Micro Speakers for Audio Acoustic Actuation
J. Mendoza-López, S. Sánchez-Solano and J.L. Huertas-Díaz
Journal Paper · ISRN Mechanical Engineering, vol. 2012, article ID 635268, 2011
abstract
doi
A study of circular piezoelectric micro speakers is presented for applications in the audio
frequency range, including values for impedance, admittance, noise figures, transducer gain
and acoustic frequency responses. The micro speakers were modelled based on piezoelectric
micro ultrasonic transducer (pMUT) design techniques and principles. In order to reach the
audio frequency range, transducer radii were increased to the order of one centimetre whilst
piezoelectric layer thicknesses ranged the order of several .m. The micro actuators presented
might be used for a variety of electroacoustic applications including noise control, hearing
aids, earphones, sonar and medical diagnostic ultrasound. This work main contribution is the
characterization of the design space and transducer performance as a function of transducer
radius, piezoelectric layer thickness and frequency range, with views towards an optimized
fabrication process.
Diseño de bloques de convolución para procesado de imágenes con FPGA
L.M. Garcés-Socarrás, A.J. Cabrera-Sarmiento, S. Sánchez-Solano and P. Brox
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. XXXII 3/2011 pp 56-69, 2011
abstract
pdf
Este trabajo analiza distintas opciones de realización de bloques para procesado lineal de imágenes implementados sobre FPGA,
así como los efectos de la elección de diferentes parámetros de diseño. Los bloques han sido desarrollados empleando un flujo de
diseño basado en modelos que se apoya en el entorno MATLAB/Simulink y la herramienta System Generator de Xilinx. Su
implementación física se ha llevado a cabo sobre una placa de desarrollo Spartan-3A DSP 1800 de Xilinx.
Fuzzy motion adaptive algorithm and its hardware implementation for video de-interlacing
J. Gutiérrez-Rios, P. Brox, F. Fernández-Hernández, I. Baturone and S. Sánchez-Solano
Journal Paper · Applied Soft Computing, vol. 11, no. 4, pp 3311-3320, 2011
abstract
doi pdf
Interlacing techniques were introduced in the early analog TV transmission systems as an efficient mechanism capable of halving the video bandwidth. Currently, interlacing is also used by some modern digital TV transmission systems, however, there is a problem at the receiver side since the majority of modern display devices require a progressive scanning. De-interlacing algorithms convert an interlaced video signal into a progressive one by performing interpolation. To achieve good de-interlacing results, dynamical and local image features should be considered. The gradual adaptation of the de-interlacing technique as a function of the level of motion detected in each pixel is a powerful method that can be carried out by means of fuzzy inference. The starting point of our study is an algorithm that uses a fuzzy inference system to evaluate motion locally (FMA algorithm). Our approach is based on convolution techniques to process a fuzzy rulebase for motion-adaptive de-interlacing. Different strategies based on bi-dimensional convolution techniques are proposed. In particular, the algorithm called 'single convolution algorithm' introduces significant advantages: a more accurate measurement of the level of motion using a matrix of weights, and a unique fuzzification process after the global estimation, which reduces the computational cost. Different architectures for the hardware implementation of this algorithm are described in VHDL language. The physical realization is carried out on a RC100 Celoxica FPGA development board. (C) 2010 Elsevier B.V. All rights reserved.
Soft computing techniques for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · IEEE Journal of Selected Topics in Signal Processing, vol. 5, no. 2, pp 285-296, 2011
abstract
doi pdf
This paper presents the application of soft computing techniques to video processing. Especially, the research work has been focused on the de-interlacing task. It is necessary whenever the transmission standard uses an interlaced format but the receiver requires a progressive scanning, as happens in consumer displays such as LCDs and plasma. A simple hierarchical solution that combines three simple fuzzy logic-based constituents (interpolators) is presented in this paper. Each interpolator is specialized in one of three key image features for de-interlacing: motion, edges, and possible repetition of picture areas. The resulting algorithm offers better results than others with less or similar computational cost. A very interesting result is that our algorithm is competitive with motion-compensated algorithms.
Fuzzy motion-adaptive interpolation with picture repetition detection for deinterlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 58, no. 9, pp 2952-2958, 2009
abstract
doi
A novel fuzzy motion-adaptive deinterlacing algorithm is presented in this paper. It uses fuzzy logic to interpolate between two processing modes, i.e., a spatial (IS) and a temporal (IT) interpolator. Furthermore, the temporal interpolator employs a very simple fuzzy inference system to implement a smart temporal interpolation that locally adapts to the features of the television (TV) material, such as possible picture repetition modes in the fields or in part of the fields (hybrid material). The combination of both systems provides effective results with a low cost in terms of computational resources.
FPGA implementation of embedded fuzzy controllers for robotic applications
S. Sánchez-Solano, A.J. Cabrera, I. Baturone, F.J. Moreno-Velo and M. Brox
Journal Paper · IEEE Transactions on Industrial Electronics, vol. 54, no. 4, pp 1937-1945, 2007
abstract
doi pdf
Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/soffivare solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle.
Automatic tuning of complex fuzzy systems with xfuzzy
F.J. Moreno-Velo, I. Baturone, A. Barriga and S. Sánchez-Solano
Journal Paper · Fuzzy Sets and Systems, vol. 158, no. 18, pp 2026-2038, 2007
abstract
doi
Tuning a fuzzy system to meet a given set of requirements is usually a difficult task that involves many parameters. Since doing it manually is often cumbersome, several CAD tools have been reported to automate this process. The tool we have developed, xfsl, tries to reduce the limitations of other tools. In this sense, it includes a wide set of supervised learning algorithms and is able to cope with complex fuzzy systems. In particular, xfsl is able to adjust hierarchical fuzzy systems; systems that employ fuzzy functions defined freely by the user, like membership or connective functions, defuzzification methods, or even linguistic hedges; and fuzzy systems with continuous outputs (such as fuzzy controllers) as well as categorical outputs (such as fuzzy classifiers). Several examples included in this paper illustrate all these issues. Another relevant advantage is that xfsl is integrated into the fuzzy system development environment Xfuzzy 3, and, hence, it can be easily employed within the design flow of a fuzzy system. (c) 2007 Elsevier B.V. All rights reserved.
A fuzzy edge-dependent motion adaptive algorithm for de-interlacing
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutierrez-Ríos and F. Fernández-Hernández
Journal Paper · Fuzzy Sets and Systems, vol. 158, no. 3, pp 337-347, 2007
abstract
doi pdf
De-interlacing algorithms are required to convert interlaced video into progressive scan format. They perform an interpolation technique which doubles the vertical sampling density. This paper presents a de-interlacing algorithm which employs fuzzy logic to adapt the interpolation strategy to the presence of motion and edges. Extensive simulations of video sequences prove the advantages of this novel approach. (c) 2006 Elsevier B.V. All rights reserved.
Modelling and implementation of fuzzy systems based on VHDL
A. Barriga, S. Sánchez-Solano, P. Brox, A. Cabrera and I. Baturone
Journal Paper · International Journal of Approximate Reasoning, vol. 41, no. 2, pp 164-178, 2006
abstract
doi pdf
The number of electronic applications using fuzzy logic-based solutions hits increased considerably in the last few years. Concurrently, new CAD tools that explore different implementation technologies for this type of systems have been developed. In this paper we illustrate a fuzzy logic system design strategy based on a high level description. Employing this high level description, the knowledge base is translated to a format in appearance close to the natural language with the particularity that it uses a hardware description language (VHDL) directly synthesizable on an FPGA circuit.]it addition, we analyze different approaches for FPGA implementations of fuzzy systems in order to characterize them in terms of area and speed. Among them, the use of specific processing architectures implemented oil FPGAs presents as main advantages a good "cost-performance" ratio and an acceptably short development time. The different synthesis facilities provided by the Xfuzzy design environment for the implementation of programmable fuzzy systems, which take advantage of the available resources in the current FPGA families, are also analyzed in this paper. (C) 2005 Elsevier Inc. All rights reserved.
Hardware/software codesign of configurable fuzzy control systems
A. Cabrera, S. Sánchez-Solano, P. Brox, A. Barriga and R. Senhadji
Journal Paper · Applied Soft Computing, vol. 4, no. 3, pp 271-285, 2004
abstract
doi pdf
Fuzzy inference techniques are an attractive and well-established approach for solving control problems. This is mainly due to their inherent ability to obtain robust, low-cost controllers from the intuitive ( and usually ambiguous or incomplete) linguistic rules used by human operators when describing the control process. This paper focuses on the hardware/software codesign of configurable fuzzy control systems. Two prototype systems implemented on general-purpose development boards are presented. In both of them, hardware components are based on specific and configurable fuzzy inference architecture whereas software tasks are supported by a microcontroller. The first prototype uses an off-the-shelf microcontroller and a low-complexity Xilinx XC4005XL field programmable gate array (FPGA). The second one is implemented as a system on programmable chip (SoPC), integrating the microcontroller together with the fuzzy hardware architecture and its interface circuits into a Xilinx Spartan2E200 FPGA. (C) 2004 Elsevier B.V. All rights reserved.
Automatic design of fuzzy controllers for car-like autonomous robots
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano and A. Ollero
Journal Paper · IEEE Transactions on Fuzzy Systems, vol. 12, no. 4, pp 447-465, 2004
abstract
doi pdf
This paper describes the design and implementation of a fuzzy control system for a car-like autonomous vehicle. The problem addressed is the diagonal parking in a constrained space, a typical problem in motion control of nonholonomic robots. The architecture proposed for the fuzzy controller is a hierarchical scheme which combines seven modules working in series and in parallel. The rules of each module employ the adequate fuzzy operators for its task (making a decision or generating a smoothly varying control output), and they have been obtained from heuristic knowledge and numerical data (with geometric information) depending on the module requirements (some of them are constrained to provide paths of near-minimal lengths). The computer-aided design tools of the environment Xfuzzy 3.0 (developed by some of the authors) have been employed to automate the different design stages: 1) translation of heuristic knowledge into fuzzy rules; 2) extraction of fuzzy rules from numerical data and their tuning to give paths of near-minimal lengths; 3) offline verification of the control system behavior; and 4) its synthesis to be implemented in a true robot and be verified on line. Real experiments with the autonomous vehicle ROMEO 4R (designed and built at the Escuela SupeRíor de Ingenieros, University of Seville, Seville, Spain) demonstrate the efficiency of the described controller and of the methodology followed in its design.
Arquitectura eficiente para la implementación hardware de sistemas de inferencia difusos
A. Cabrera, S. Sánchez-Solano, C.J. Jimémez, A. Barriga and I. Baturone
Journal Paper · Ingeniería Electrónica, Automática y Comunicaciones, vol. XXIII, no. 1, pp. 59-66, 2003
abstract
Se describen los elementos integrantes de una arquitectura de bajo costo y alto desempeño para la implementación hardware de sistemas de inferencia difusos, la cual se basa en el procesado de reglas activas, la limitación del grado de solapamiento de las funciones de pertenencia de las entradas y la utilización de métodos de defusificación simplificados. También se expone el entorno de desarrollo de sistemas difusos Xfuzzy, con énfasis en la herramienta XFVHDL, la cual permite la generación de código VHDL para los diferentes elementos de la arquitectura descrita.
Conferences
Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
abstract
doi
This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.
Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
P. Navarro-Torrero, L.F. Rojas-Muñoz, P. Brox and S. Sánchez-Solano
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
abstract
Abstract not available
A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem
E. Camacho-Ruiz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Tena-Sánchez and P. Brox
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
abstract
Abstract not available
HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip
A. Karmakar, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
abstract
Abstract not available
A complete SHA-3 hardware library based on a high efficiency Keccak design
E. Camacho-Ruiz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2023
abstract
Hash functions are a crucial part of the cryptographic primitives. So much so that in 2007 a new competition was launched to select new standards for the SHA-3 function, which was won by Keccak. Since then, many software and hardware implementations have been submitted, claiming to reduce the number of operation cycles or increase design efficiency. Thus, this work aims to present a new hardware solution for the Keccak function, which forms the core of SHA-3, that achieves a high degree of tunability and is competitive with the state of the art. In addition, this work presents the integration of these designs into a hardware IP module together with the relevant drivers and functions that allow their use in software environments. Preliminary tests have shown an acceleration of up to 10 times compared to pure software code.
Root of Trust Components to Increase Security of RISC-V Based Systems on Chips
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · RISC-V Summit Europe 5-9 June, 2023
abstract
Abstract not available
Análisis y evaluación de un RO-PUF como TRNG
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2023
abstract
Abstract not available
True Random Number Generator based on RO-PUF
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · Conference on Design of Circuits and Integrated Circuits DCIS 2022
abstract
The implementation of true random number generators is of vital importance to preserve the reliability of cryptographic systems. The lack of entropy can compromise their integrity, affecting the security of the entire chain of applications. Ensuring the effectiveness of a random number generator can be understood as reducing the risk of information loss due to possible attacks by third parties. This paper presents a novel approach for a true random number generator based on a Ring Oscillator- Physical Unclonable Function. Since the principle of operation of physical unclonable functions is based on the physical properties of each device, they can be used for security applications such as device identification, counterfeit prevention and increase the robustness of cryptographic functions. In addition, increasing the versatility of the design to use them as a source of entropy, they can also fulfill tasks such as generation of initialization vectors or nonces and keys for symmetric cryptography. The system incorporates multiple operating configurations, which allows a complete analysis of its performance to adapt it to different application scenarios. The randomness and correct operation of the proposed design have been evaluated online, by incorporating it into a hybrid HW/SW embedded system able to run the official test suite published by the National Institute of Standards and Technology without any need for post-processing. The architecture has been designed for Xilinx Zynq-700 family devices and implemented on the Pynq-Z2 development board.
Hardware dedicado para la optimización temporal del algoritmo NTRU
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and Piedad Brox
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
abstract
Los actuales algoritmos criptográficos se encuentran amenazados por la inminente llegada de la computación cuántica, por lo que los organismos internacionales, especialmente aquellos relacionados con la ciberseguridad, están potenciando el estudio e implementación de algoritmos que permitan volver a establecer entornos seguros de comunicación. En concreto, se plantean los algoritmos criptográficos post-cuánticos. Dentro de los algoritmos propuestos se encuentra el NTRU. Su principal inconveniente es el excesivo tiempo que requiere la multiplicación de polinomios usada en el proceso de cifrado. Por ello, este trabajo tiene como principal objetivo estudiar la posibilidad de utilizar hardware dedicado para acelerar la multiplicación. El uso de técnicas de codiseño hardware/software permite una implementación eficiente del criptosistema, donde las partes más costosas se ejecutan a nivel hardware. Este breve resumen recoge las últimas aportaciones que el grupo de investigación ha realizado en esta línea.
Diseño y evaluación de las prestaciones de funciones físicas no clonables basadas en osciladores en anillo sobre FPGAs
M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Brox and S. Sánchez-Solano
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
abstract
Los esquemas de seguridad basados en funciones físicas no clonables aprovechan las características intrínsecas del hardware para mejorar la seguridad de los dispositivos electrónicos. Este resumen presenta dos trabajos para diseñar y caracterizar funciones físicas no clonables basados en osciladores en anillo propuestas por nuestro grupo de investigación. El primero se centra en el flujo de diseño y caracterización basado en una herramienta incluida en el entorno de Matlab, mientras que el segundo presenta y caracteriza una función física no clonable basada en osciladores en anillo muy compacta y altamente configurable usando un flujo de diseño para sistemas empotrados basado en el entorno PYNQ.
SoPC Implementation of a Genetic Algorithm for Circle Detection
L.F. Rojas-Muñoz, S. Sánchez-Solano, C.H. García-Capulín and H. Rostro-González
Conference · IEEE International Autumn Meeting on Power, Electronics and Computing ROPEC 2021
abstract
This article presents a system-on-programable-chip implementation of a genetic algorithm for circle detection. The use of this implementation technique allows the development of an efficient, decentralized and embedded system with high scalability and robustness, in addition to providing it with an effective and easy-to-use interface. The hardware components of the system implement the evolutionary process and the software elements perform image pre-processing tasks and provide the user interface. The SoPC was implemented on a Zybo-Z7 development board equipped with a Xilinx Zynq-7000 family device and it has been numerically validated on synthetic and real images. Detection rates obtained for both types of images demonstrate the suitability of this proposal to design embedded systems with size, resources and power consumption limitations for applications in Industry 4.0 and other related paradigms.
Implementación en SoC de un Sistema Embebido para la Detección de Círculos en Imágenes Digitales
Luis F. Rojas-Muñoz, S. Sánchez-Solano, C.H. García-Capulín and H. Rostro-González
Conference · Congreso Internacional de Investigación Academia Journals Celaya CELAYA 2021
abstract
Los dispositivos basados en lógica programable que incorporan potentes sistemas de procesamiento permiten la implementación eficiente de sistemas embebidos que realizan tareas complejas, facilitando la aceleración en hardware de sus etapas críticas para mejorar su eficiencia. En este artículo se presenta el diseño de un sistema de detección de círculos en imágenes digitales basado en un algoritmo genético e implementado en la placa de desarrollo Pynq-Z2. Esta placa contiene un dispositivo Zynq-7000 SoC de Xilinx que incluye un procesador ARM Cortex-A9 de doble núcleo. Los beneficios que brindan la lógica programable y el
sistema de procesado son aprovechados para acelerar el algoritmo genético mediante su implementación en hardware y llevar a cabo las etapas de pre- y post-procesamiento de la imagen en software. La aplicación Jupyter Notebook, incorporada en el entorno de desarrollo PYNQ (Phython productivity for Zynq), permite utilizar funciones y librerías en Python para controlar de manera interactiva el flujo de datos entre los componentes software/hardware del sistema y los periféricos de entrada/salida. Los resultados obtenidos en precisión y rendimiento demuestran la idoneidad de esta propuesta para diseñar sistemas embebidos con tamaño, recursos y consumo de energía restringidos.
Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs
M.C. Martínez-Rodríguez, E. Camacho-Ruiz, S. Sánchez-Solano and P. Brox
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2021
abstract
This work presents a unified framework to design, implement and evaluate the performance of Ring Oscillator Physical Unclonable Functions (RO PUFs) on FPGAs. The design flow uses a Digital Signal Processing (DSP) tool integrated into the Matlab environment. The use of this tool eases the evaluation of the PUF performance. The DSP tool provides an environment to apply the challenges to the RO PUF, acquire the responses by using hardware (HW) co-simulation, and compute a set of metrics to quantify the stability, probability and entropy of the PIF response. Additionally, the robustness of the PUF response is proved in the generation of secret keys. The design flow was applied to evaluate the performance of RO PUFs implemented on 17 Basys 3 Artix-7 FPGA Boards.
Accelerating the Development of NTRU Algorithm on Embedded Systems
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and P. Brox
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
abstract
The advent of quantum computers represents a serious threat to current public key cryptosystems. To face this problem the so-called Post-Quantum (PQ) cryptographic solutions are being developed, many of which have been presented to the competition launched by NIST to evaluate proposals of PQ cryptography for standardization and deployment. This paper addresses the implementation of the NTRU PQ cryptographic algorithm on embedded systems. Using a Python-based development framework to accelerate the design process, software-only and hybrid (HW/SW) implementations of NTRU are evaluated in terms of operation speed and resource consumption on a System-on-Chip (SoC). Results show that hardware implementation of critical operations in conjuction with a Python+C programming allows an increase in performance that ranges from 130 to 450 depending on the selected scenario to use the algorithm.
Hardware implementation of fuzzy inference systems for real-time video processing applications
S. Sánchez-Solano, M. Brox, E. Calvo-Gallego, A. Gersnoviez and P. Brox
Conference · XVIII Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2016
abstract
As a consequence of its ability to handle inaccurate or incomplete information and its capacity to mimic the human reasoning schema, Fuzzy Logic-based techniques have been widely used in many image processing algorithms [1] [2]. Incorporating these algorithms into current embedded video processing systems requires the use of specific hardware designs capable of providing the data-transfer rates demanded by existing applications [3]. This paper presents a hardware architecture for fuzzy inference systems which is able to provide an inference in each clock cycle, thus allowing the usage of fuzzy techniques in low- and middle-level video processing tasks. Even though the architecture imposes some limitations on the membership functions and inference mechanisms that can be used, it may be suitable for hardware implementation of many fuzzy solutions proposed in the literature.
FPGA Implementation of the Two-Dimensional Fuzzy-ELA Algorithm for Image Enlargement
M. Brox, S. Sánchez-Solano, P. Brox, A. Gersnoviez and I. Baturone
Conference · XVIII Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2016
abstract
Resolution improvement of images is today required for many applications, as medical or satellite imaging, where it is very important to distinguish details [1]. The interpolation capability provided by Fuzzy Logic, in addition to its effectivity to incorporate heuristic knowledge into numeric procedures, has motivated its usage in recent algorithms for image enlargement [2]. This paper presents the hardware implementation of the two-dimensional Fuzzy-ELA algorithm proposed in [3]. The 2D Fuzzy-ELA method is a generalization of the basic Fuzzy-ELA algorithm [4], which uses a fuzzy system to adapt the interpolation to the presence of edges in images, achieving better results than many other approaches. The hardware implementation described in this paper includes parameters to allow selecting different scale factors for the image enlargement. In order to simplify the description, Fig.1a illustrates the process when a factor of two is chosen.
Bloques de detección de matrículas sobre hardware reconfigurable
J.C. Gutiérrez, E. Augusto-Perdomo, L.M. Garcés-Socarrás, A.J. Cabrera Sarmiento, S. Sánchez-Solano and P. Brox-Jiménez
Conference · XVI Convención de Ingeniería Eléctrica CIE 2015
abstract
El presente trabajo aborda la implementación de un sistema de localización de regiones de interés sobre hardware reconfigurable, espec'ifico para determinar la ubicación de la matr'icula de un auto para su posterior identificación. Se realiza un estudio de los sistemas de visión, enfocándose en los sistemas de detección de regiones de matrículas, analizando las arquitecturas y algoritmos de procesado que los componen para desarrollar el algoritmo propuesto. En la implementación se emplean bloques de procesado de imágenes de la biblioteca XSGImgLib así como bloques diseñados para etiquetado de la imagen y análisis de selección de matrículas basados en la herramienta Xilinx System Generator. El sistema fue implementado sobre una placa Spartan-6 LX45, cumpliendo con los requerimientos de procesado en tiempo real de las aplicaciones de visión computarizada, con una frecuencia máxima de operación de 30.79 MHz para una imagen de 320x240 pixeles y un máximo de 100 etiquetas. El consumo de recursos del sistema, implementado es de un 10.55% de slices ocupados, dejando recursos suficientes para implementar otras funcionalidades en el dispositivo programable.
Cryptographic algorithms integration in FPGA-based embedded systems
A. Cabrera Aldaya, A.J. Cabrera-Sarmiento and S. Sánchez-Solano
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2015
abstract
This paper describes hardware implementations of cryptographic algorithms that are integrated into the OpenSSL library, which is used by Linux operating system embedded applications to protect TCP/IP networks. Because of their widespread use, the selected algorithms are AES and the hash functions SHA-1 and SHA-256. These algorithms are implemented in hardware as coprocessors of Xilinx MicroBlaze soft processor core using the FSL interface for data exchange. The coprocessors are integrated into the OpenSSL library considering Linux operating system multitasking feature, so a synchronization technique is selected to synchronize the access to the hardware coprocessors. The speed gain is measured using the OpenSSL's speed utility. Finally, a virtual private network is configured using OpenVPN in order to compare the transmission rate achieved by the coprocessors.
Hardware/Software co-design of video processing applications on a reconfigurable platform
J. Cerezuela-Mora, E. Calvo-Gallego and S. Sánchez-Solano
Conference · IEEE International Conference on Industrial Technology ICIT 2015
abstract
The use of a reconfigurable platform, based on the Zynq-7000 Xilinx family, for hardware/software co-design of video processing applications is described in this work. The computing capability of ARM processors included in the device allows performing I/O and processing task by using conventional software libraries. On the other hand, the possibility to accelerate certain tasks through specific hardware implementation on the available programmable logic makes it easier to compare different design alternatives. The advantages of the proposed platform are demonstrated by using different design flows to implement some spatial filters usually required in video processing systems.
Hardware implementation of a background substraction algorithm in FPGA-based platforms
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · IEEE International Conference on Industrial Technology ICIT-2015
abstract
Different strategies for the implementation of a fuzzy logic-based background subtraction algorithm are presented in this paper. The goal of this contribution is to obtain an efficient implementation suitable to be integrated into hardware platforms with limited resources. In order to find an adequate performance-resources trade-off, the design space is explored taken into account several strategies and implementation options. The final implementation is encapsulated within an IP core that has been used in a demonstrator, built on a Spartan-3A-DSP FPGA development board, suitable for processing VGA (640x480P) @ 60 Hz.
Codiseño hardware/software de aplicaciones de procesado de vídeo sobre una plataforma reconfigurable
J. Cerezuela-Mora and S. Sánchez-Solano
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2014
abstract
Esta comunicación describe el codiseño hardware/software de aplicaciones de procesado de vídeo mediante una plataforma de desarrollo que incorpora un dispositivo programable de la familia Zynq-7000 de Xilinx. La potencia de cómputo del procesador ARM incluido en este dispositivo, así como la posibilidad de acelerar determinadas tareas implementándolas mediante hardware específico sobre la lógica programable disponible, facilita la comparación de distintas alternativas de diseño. En el trabajo se discuten, asimismo, una serie de técnicas que permiten la optimización del sistema frente a desarrollos similares propuestos por otros autores.
Hardware implementation of smart embedded vision systems
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · Int. Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications VISIGRAPP 2014
abstract
The research presented in this contribution is focused on the efficient hardware implementation of image processing algorithms that are present at different levels of a smart vision system. The system is conceived as a reconfigurable embedded device which, in turn, will be a node of a collaborative sensor network.
The inclusion of fuzzy logic techniques is explored to improve the performance of conventional vision algorithms.
FPGA based embedded systems for video processing
P. Brox, E. Calvo-Gallego and S. Sanchez-Solano
Conference · Workshop on the the Architecture of Smart Cameras WASC 2013
abstract
Abstract not available
A Fuzzy System for Background Modeling in Video Sequences
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · International Workshop on Fuzzy Logic and Applications WILF 2013
abstract
Many applications in video processing require the background modeling as a first step to detect the moving objects in the scene. This paper presents an approach that calculates the updating weight of a recursive adaptive filter using a fuzzy logic system. Simulation results prove the advantages of the fuzzy approach versus conventional methods such as temporal filters.
Real-Time FPGA Connected Component Labeling System
E. Calvo-Gallego, A. Cabrera-Aldaya, P. Brox and S. Sánchez-Solano
Conference · IEEE Int. Conf. on Electronics, Circuits, and Systems ICECS 2012
abstract
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The implementation of a connected component labeling algorithm (CCL) for real-time operation is presented in this paper. The algorithm, which was designed and implemented following a model-based methodology centered on Matlab/Simulink and Xilinx-System Generator, uses horizontal and vertical blanking periods to improve the quality of labeling and increase the operation speed. Its performance, with a VGA 640 x 480 P @ 60 Hz video, is shown by means of its integration on a complete video processing system over a Spartan-3A DSP 3400 development board.
Implementación sobre FPGA de un algoritmo de etiquetado en tiempo real
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA2012
abstract
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En esta comunicación se presenta una implementación de un algoritmo de etiquetado de componentes conexos en tiempo real que aprovecha los intervalos de supresión horizontal y vertical en la fuente de la imagen para mejorar la calidad del etiquetado y acelerar la frecuencia de trabajo. El diseño se ha llevado a cabo usando la herramienta System Generator de Xilinx lo que ha permitido reducir los tiempos de implementación y verificación lógica y funcional del modelo.
Un algoritmo en tiempo real para etiquetado de componentes conectados en imágenes
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · Iberchip XVIII Workshop IWS 2012
abstract
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Esta comunicación presenta un algoritmo de dos pasadas para el etiquetado en tiempo real de los componentes conexos en una imagen. El algoritmo propuesto es una buena opción frente a otras alternativas de dos y múltiples pasadas ya que ha sido diseñado considerando que su implementación en FPGAs ofrezca un buen compromiso entre recursos ocupados y velocidad de operación. Se describen dos implementaciones hardware de este algoritmo, cuyo desarrollo se ha llevado a cabo siguiendo un flujo de diseño basado en la herramienta System Generator de Xilinx.
XFSML: An XML-based modeling language for fuzzy systems
F.J. Moreno-Velo, A. Barriga, S. Sánchez-Solano and I. Baturone
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2012
abstract
This paper presents a new modeling language for fuzzy systems called XFSML. It is an XML-based language and it is proposed as a starting point for the definition of a standard modeling language in the fuzzy community. The main features of the language are its high expressiveness and its independence from specific platforms, tools or programming languages.
Síntesis automática de sistemas difusos mediante xfuzzy
S. Sánchez-Solano and M. Brox
Conference · XVI Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2012
abstract
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En esta comunicación se describen las dos herramientas para síntesis hardware de sistemas de inferencia difusos incluidas en el entorno Xfuzzy. Ambas herramientas comparten una arquitectura de implementación común, aunque están basadas en metodologías de diseño diferentes. Xfvhdl (Xfuzzy to VHDL) genera código VHDL estándar que puede ser posteriormente implementado mediante un ASIC o una FPGA. Xfsg (Xfuzzy to SysGen) se apoya en el entorno Matlab/Simulink y las herramientas de desarrollo de sistemas de procesado digital de señal sobre FPGAs de Xilinx. Como demuestran los ejemplos considerados, el empleo de estas herramientas permite acelerar considerablemente las etapas de descripción, verificación y síntesis de sistemas de control basados en lógica difusa.
Librería de módulos IP para la implementación sobre FPGA de algoritmos de procesado de imágenes
L.M. Garcés, P. Brox, S. Sánchez-Solano and A. Cabrera
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2011
abstract
En esta comunicación se presenta una librería de módulos IP dedicada a la implementación de algoritmos básicos de procesado de imágenes sobre FPGA. La librería está compuesta por módulos que implementan filtros lineales y no-lineales en el dominio del espacio así como operadores morfológicos.
Herramientas de CAD para síntesis de sistemas difusos
M. Brox, L.L. Delgado and S. Sánchez-Solano
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2011
abstract
En esta comunicación se presentan dos técnicas de diseño que permiten la síntesis automática de sistemas de control difusos. Una de ellas se basa en la generación de código VHDL genérico que después puede ser implementado en una FPGA o un ASIC, mientras que la segunda utiliza la herramienta SysGen del entorno Matlab/Simulink para el diseño de sistemas de procesado digital de señal (DSP) sobre FPGA de Xilinx. Ambas estrategias aceleran las etapas de descripción, síntesis y verificación funcional de los sistemas bajo desarrollo.
Characterization and Modeling of Piezoelectric Integrated Micro Speakers for Audio Acoustic Actuation
J. Mendoza-López, S. Sánchez-Solano and J.L. Huertas-Díaz
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2011
abstract
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An array of piezoelectric micro actuators can be used for radiation of an ultrasonic carrier signal modulated in amplitude with an acoustic signal, which yields audio frequency applications as the air acts as a self-demodulating medium. This application is known as the parametric array. We propose a parametric array with array elements based on existing piezoelectric micro ultrasonic transducer (pMUT) design techniques. In order to reach enough acoustic output power at a desired operating frequency, a proper ratio between number of array elements and array size needs to be used, with an array total area of the order of one cm square. The transducers presented are characterized via impedance, admittance, noise figure, transducer gain and frequency responses.
XFVHDL4: A hardware synthesis tool for fuzzy systems
M. Brox, S. Sánchez-Solano and L. Delgado
Conference · International Conference on Intelligent Systems Design and Applications ISDA 2011
abstract
This paper presents a design technique that allows the automatic synthesis of fuzzy inference systems and accelerates the exploration of the design space of these systems. It is based on generic VHDL code generation which can be implemented on a programmable device (FPGA) or an application specific integrated circuit (ASIC). The set of CAD tools supporting this technique includes a specific environment for designing fuzzy systems, in combination with commercial VHDL simulation and synthesis tools. As demonstrated by the analyzed design examples, the described development strategy speeds up the stages of description, synthesis, and functional verification of fuzzy inference systems.
Digital implementation of hierarchical piecewise-affine controllers
I. Baturone, M.C. Martínez-Rodríguez, P. Brox, A. Gersnoviez and S. Sánchez-Solano
Conference · IEEE International Symposium on Industrial Electronics ISIE 2011
abstract
pdf
This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the hierarchical solution have fewer inputs and/or coarser partitions, so that they can reduce considerably the hardware resources required and/or the time response of the controller. A design methodology aided by CAD tools is employed to design the parameters of the controller, implement its architecture in an FPGA, and verify the static and dynamic behavior of the digital implementation by applying hardware-in-the-loop testing. © 2011 IEEE.
Aplicación de XFuzzy 3 al procesado de imágenes basado en reglas
I. Baturone, P. Brox and R. Arjona
Conference · XIV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2010
abstract
Los entornos de desarrollo de sistemas fuzzy se han empleado normalmente para diseñar sistemas de control y de toma de decisiones pero apenas para diseñar sistemas de procesado de imágenes, a pesar de que este campo cuenta ya con numerosas soluciones basadas en Lógica Fuzzy. En este artículo se muestra cómo el entorno Xfuzzy 3 desarrollado en el Instituto de Microelectrónica de Sevilla posee la versatilidad necesaria para abordar el diseño de estos sistemas, facilitando su descripción, verificación, ajuste y síntesis.
Tuning of a hierarchical fuzzy system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2010
abstract
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The tuning of hierarchical fuzzy systems are not supported by the majority of CAD tools available at the market currently. The XFSL tool integrated into Xfuzzy 3 allows the tuning of complex fuzzy systems, for instance, hierarchical systems with modules in cascade. The authors propose the use of this tool for tuning a complex fuzzy system for video de-interlacing in this paper. The parameters obtained after tuning are proven by de-interlacing a wide battery of sequences. The use of tuning techniques improves the quality of de-interlacing and provides an algorithm simplification that facilitates its hardware implementation.
Metodología para el diseño multilenguaje de sistemas de control empotrados sobre FPGAs
E. del Toro, S. Sánchez-Solano, A. Cabrera and A. Barriga
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2010
abstract
pdf
Abstract not avaliable
Codiseño hardware-software de sistemas de control difusos sobre FPGAs
S. Sánchez-Solano, M. Brox, E. del Toro and A.J. Cabrera
Conference · Iberchip XVI Workshop IWS 2010
abstract
Abstract not avaliable
Hardware-software codesign of fuzzy control systems using FPGAs
E. del Toro, S. Sánchez-Solano, M. Brox and A.J. Cabrera
Conference · International Conference on Informatics in Control, Automation and Robotics ICINCO 2010
abstract
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This paper describes a hardware/software codesign strategy for fuzzy control systems implementation using FPGAs. The main contribution of the paper consists of a methodology for joint development of hardware and software components intended for rapid and verifiable design of a fuzzy control system. The design flow combines specific tools for fuzzy inference systems included in the XFuzzy environment, simulation and modelling tools from Matlab and FPGA synthesis, and implementation tools provided by Xilinx. The advantages of this proposal are described in section 4 as it is used for the control system development of an autonomous vehicle.
Microelectronics implementation of directional image-based fuzzy templates for fingerprints
R. Arjona, I. Baturone and S. Sánchez-Solano
Conference · International Conference on Microelectronics ICM 2010
abstract
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Fingerprint orientation image, also called directional image, is a widely used method in fingerprint recognition. It helps in classification (accelerating fingerprint identification process) as well as in preprocessing or processing steps (such as fingerprint enhancement or minutiae extraction). Hence, efficient storage of directional image-based information is relevant to achieve low-cost templates not only for "match on card" but also for "authentication on card" solutions. This paper describes how to obtain a fuzzy model to describe the directional image of a fingerprint and how this model can be implemented in hardware efficiently. The CAD tools of the Xfuzzy 3 environment have been employed to accelerate the fuzzy modeling process as well as to implement the directional image-based template into both an FPGA from Xilinx and an ASIC.
Tuning of a hierarchical fuzzy system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE World Congress on Computational Intelligence WCCI 2010
abstract
The tuning of hierarchical fuzzy systems are not supported by the majority of CAD tools available at the market currently. The XFSL tool integrated into Xfuzzy 3 allows the tuning of complex fuzzy systems, for instance, hierarchical systems with modules in cascade. The authors propose the use of this tool for tuning a complex fuzzy system for video de-interlacing in this paper. The parameters obtained after tuning are proven by de-interlacing a wide battery of sequences. The use of tuning techniques improves the quality of de-interlacing and provides an algorithm simplification that facilitates its hardware implementation.
A design environment for synthesis of embedded fuzzy controllers on FPGAs
S. Sánchez-Solano, E. del Toro, M. Brox, I. Baturone and A. Barriga
Conference · IEEE World Congress on Computational Intelligence WCCI 2010
abstract
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This paper presents a design environment for the synthesis of embedded fuzzy controllers on FPGAs. It provides a novel implementation technique that allows accelerating the exploration of the design space of fuzzy control modules, as well as a codesign flow that eases their integration into complex control systems and the joint development of hardware and software components. The set of CAD tools supporting this environment includes specific fuzzy logic design tools provided by Xfuzzy, FPGA synthesis and implementation tools from Xilinx, and modeling and simulation facilities from Matlab. As demonstrated by the analyzed design examples, the described development strategy takes advantage of flexibility and ease of configuration offered by the different tools to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy control systems.
An automated design flow from linguistic models to piecewise polynomial digital circuits
I. Baturone, S. Sánchez-Solano, A.A. Gersnoviez and M. Brox
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
abstract
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This paper describes how the different CAD tools of the environment Xfuzzy 3, developed in Microelectronics Institute of Seville and University of Seville, allow to translate expressive linguistic models into mathematical ones, in particular, into a combination of piecewise polynomial systems that can be implemented efficiently in hardware. The new synthesis tool of Xfuzzy 3 automates communication with Xilinx System Generator in Matlab, thus facilitating implementation of the linguistic model into an FPGA from Xilinx. This is illustrated with the design of a navigation controller for an autonomous robot.
Un algoritmo de desentrelazado adaptativo con la repetición de imágenes basado en lógica difusa
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Iberchip XV Workshop IWS 2009
abstract
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Esta comunicación presenta un interpolator temporal basado en lógica difusa que es utilizado para el desentrelazado de la señal de vídeo. El objetivo es que dicho interpolador sea capaz de aprovechar una caracterísctica que cada vez es más frecuente en las secuencias, debido a los estándares de conversión entre distintos formatos de transmisión, como es la repetición de imágenes. Este nuevo interpolador es incluido en un algoritmo adaptativo en función del movimiento, obteniendo una técnica de desentrelazado muy competitiva frente a otros algoritmos que son actualmente utilizados en ASICs de dispositivos comerciales de altas prestaciones. Los resultados de simulación obtenidos al desentrelazar secuencias de distintos materiales (film, vídeo e híbrido) muestran la superioridad del algoritmo propuesto.
XfuzzyLib: una librería de módulos para la síntesis hardware de sistemas de inferencia difusos
S. Sánchez-Solano, M. Brox, I. Baturone and A. Barriga
Conference · XIV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2008
abstract
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Esta comunicación presenta una nueva técnica de implementación de sistemas difusos que está basada en el uso de una librería de módulos específicos, denominada XfuzzyLib, y cuyo flujo de diseño combina las herramientas de modelado y simulación del entorno Matlab con las de síntesis e implementación de FPGAs de Xilinx. La estrategia propuesta, que constituye la base de una nueva herramienta de síntesis hardware del entorno Xfuzzy, aprovecha las ventajas de flexibilidad y facilidad de configuración que brindan las diferentes herramientas de Matlab y Xilinx, permitiendo acelerar considerablemente las etapas de descripción, síntesis y verificación funcional de los sistemas bajo desarrollo.
Síntesis hardware de módulos de inferencia difusos mediante herramientas de diseño de DSP
M. Brox, S. Sánchez-Solano, P. Brox, I. Baturone, A. Barriga and A. Gersnoviez
Conference · VIII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2008
abstract
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En esta comunicación se describe una nueva estrategia de desarrollo de sistemas de control basados en lógica difusa mediante un flujo de diseño que combina las herramientas de modelado y simulación del entorno Matlab y las herramientas de síntesis e implementación de FPGAs de Xilinx. Apoyada en el uso de una librería de módulos específicos para sistemas difusos, esta estrategia acelera las etapas de descripción, síntesis y verificación funcional de los sistemas bajo desarrollo.
Síntesis de sistemas de control difusos mediante herramientas de diseño de DSP sobre FPGAs
S. Sánchez-Solano, M. Brox and A. Cabrera
Conference · Iberchip XIV Workshop IWS 2008
abstract
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En esta comunicación se describe una nueva técnica de implementación de sistemas difusos, basada en el uso de una librería de módulos específicos, cuyo flujo de diseño combina las herramientas de modelado y simulación del entorno Matlab y las herramientas de síntesis e implementación de FPGAs de Xilinx. La estrategia propuesta aprovecha las ventajas de flexibilidad y facilidad de configuración que brindan las diferentes herramientas de Matlab y Xilinx, permitiendo acelerar considerablemente las etapas de descripción, síntesis y verificación funcional de los sistemas difusos bajo desarrollo.
Nuevos algoritmos de clasificación integrados en Xfuzzy 3
F.J. Moreno-Velo, I. Baturone and S. Sánchez-Solano
Conference · XIV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2008
abstract
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El entorno Xfuzzy 3 está formado por un amplio conjunto de herramientas dedicadas a dar soporte a las diferentes etapas del desarrollo de sistemas difusos. Entre estas herramientas se encuentra Xfdm, dedicada a la extracción de conocimiento difuso a partir de conjuntos de datos. Este trabajo presenta las últimas modificaciones realizadas en esta herramienta, que consisten en la integración de los algoritmos de clasificación difusos FuzzyID3 y FuzzConRI.
A motion and edge adaptive interlaced-to-progressive conversion using fuzzy logic-based systems
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Information Processing and Management of Uncertainty in Knowledge-based Systems IPMU 2008
abstract
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This paper presents an algorithm for video de-interlacing. The approach uses three fuzzy logic-based systems to adapt the interpolation strategy to the presence of motion and edges. Furthermore, the algorithm is able to deal with any kind of TV material independently of the source used to acquire the scene. Extensive simulations of standard and real sequences prove the efficiency of the proposed algorithm.
Linguistic summarization of network traffic flows
F.M. Pouzols, A. Barriga, D.R. López and S. Sánchez-Solano
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2008
abstract
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We address, by means of fuzzy linguistic summaries, two related problems: summarizing network flow statistics and making these statistics human-readable. Two complementary summarization methods are developed. First, a fixed set of protoforms of interest is defined, and the ones with a higher truth value are shown to the user as simple on-line summaries. This first method is suitable for real-time monitoring. Then, an association rules mining process is carried out in order to find hidden relations in flow records. Both approaches are implemented in a tool capable of real-time and off-line processing of network flow records. Experimental results for a number of heterogeneous NetFlow records show the usefulness of linguistic summaries to both network practitioners and users. © 2008 IEEE.
Open FPGA-Based Development Platform for Fuzzy Systems with Applications to Communications
F. Montesino, A. Barriga, D.R. López and S. Sánchez-Solano
Conference · XXII Conference on Design of Circuits and Integrated Systems DCIS 2007
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Soft computing techniques are gaining momentum as tools for network traffic modeling, analysis and control. Efficient hardware implementations of these techniques that can achieve real-time operation in high-speed communications equipment is however an open problem. This paper describes a platform for the development of fuzzy systems with applications to communications systems, namely network traffic analysis and control. An FPGA development board with PCI interface is employed to support an open platform that comprises open CAD tools as well as IP cores. For the development process, we set up a methodology and a CAD tools chain that cover from initial specification in a high-level language to implementation on FPGA devices. PCI compatible fuzzy inference modules are implemented as SoPC based on the open WISHBONE interconnection architecture. We outline results from the design and implementation of fuzzy analyzers and regulators for network traffic. These systems are shown to satisfy operational and architectural requirements of current and future high-performance routing equipment.
FPGA-based implementation of a fuzzy motion adaptive de-interlacing algorithm
P. Brox, S. Sánchez-Solano and I. Baturone
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2007
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This paper surveys the hardware implementation of a de-interlacing algorithm on Field-Programmable Technology for real-time processing. The algorithm presented evaluates the level of motion at each pixel, and determines the interpolation between a spatial and a temporal method according to the presence of motion. To achieve it the algorithm employs an hierarchical structure with three simple fuzzy systems. The first one performs a set of fuzzy rules to apply reasoning in order to detect motion; the second one selects the most convenient direction to implement an edge-dependent line average method; and the third one is used to choose the most adequate temporal method.
The hardware implementation of this algorithm combines pipeline architecture with a parallel processing of fuzzy rules to accelerate the computation. As result an efficient implementation is developed in terms of computational time and hardware cost.
Aplicación de técnicas de interpolación basadas en lógica difusa al procesado de imágenes de video
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Iberchip XIII Workshop IWS 2007
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Muchas tareas básicas de procesado de imágenes requieren la manipulación de grandes volúmenes de información que, en ocasiones, puede resultar ambigua y/o imprecisa como consecuencia de las características propias de las imágenes (gran cantidad de detalles con grandes contrastes de valores de luminancia y secuencias con un elevado grado de movimiento) o de los defectos de las mismas (presencia de ruido, falta de nitidez, etc.). En esta comunicación se analizan nuevas técnicas de interpolación basadas en lógica difusa que proporcionan soluciones eficaces para dos aplicaciones típicas de procesado de imágenes: el desentrelazado de señales de vídeo y el incremento de resolución de imágenes.
A fuzzy motion adaptive de-interlacing algorithm capable of detecting field repetition patterns
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE International Symposium on Intelligent Signal Processing WISP 2007
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A new motion adaptive algorithm for de-interlacing video is proposed in this paper. It employs two fuzzy systems to interpolate the missing lines of the transmission. One fuzzy system is used to evaluate the motion level at the current pixel, and a second one selects the most adequate temporal interpolation method. The combination of both systems provides an effective result with a low cost in term of hardware resources.
Using xfuzzy environment for the whole design of fuzzy systems
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano, A. Barriga, P. Brox, A.A. Gersnoviez and M. Brox
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2007
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Since 1992, Xfuzzy environment has been improving to ease the design of fuzzy systems. The current version, Xfuzzy 3, which is entirely programmed in Java, includes a wide set of new featured tools that allow automating the whole design process of a fuzzy logic based system: from its description (in the XFL3 language) to its synthesis in C, C++ or Java (to be included in software projects) or in VHDL (for hardware projects). The new features of the current version have been exploited in different application areas such as autonomous robot navigation and image processing.
New features of the fuzzy logic development environment Xfuzzy
A. Barriga, S. Sánchez-Solano, I. Baturone, D.R. López, F.J. Moreno-Velo, F. Montesino, P. Brox and N.M. Hussein
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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The characteristics of the new version of the fuzzy systems development environment Xfuzzy is presented. The environment covers the aspects related to the specification, verification, adjustment and implementation of fuzzy systems. It is an open environment (in the sense that the user can define many functional and structural aspects) and a free distribution tool that allows proving new formalisms and helps the definition and implementation of complex systems.
Intelligent Scheduling of Aggregate Traffic in Internet Routers by Means of Fuzzy Systems
F. Montesino Pouzol, D.R. López, A. Barriga and S. Sánchez-Solano
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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A major research problem in Internet transport and network layers is the development of traffic regulation mechanisms that can cope with the requirements of a growing diversity of technologies, applications and services. This paper presents novel mechanisms for intelligent traffic scheduling in Internet routers by means of fuzzy logic based systems. A systematic design methodology, interpretability principles, evaluation over a broad range of network scenarios as well as practical implementation constraints have been considered. A comparative evaluation of results obtained by means of our fuzzy controllers as compared to that of traditional approaches is outlined.
Image Enlargement using the Fuzzy-ELA Algorithm
P. Brox, I. Baturone, S. Sánchez-Solano and A. Barriga
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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The increase of resolution is one of the most important tasks in image processing. Traditional interpolation algorithms perform a linear interpolation between the closest pixels in the image. This strategy may introduce mistakes specially in the reconstruction of edges and zones with high contrast luminance values. The use of a novel interpolation algorithm for image enlargement is presented in this paper. It employs a fuzzy logic-system to adapt the interpolation to the presence of edges in the image, achieving good results at expense of a low increment in the computational cost.
Fuzzy Motion Adaptive Algorithm for Video De-interlacing
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutiérrez-Ríos and F. Fernández-Hernández
Conference · International Conference on Knowledge-Based and Intelligent Information and Engineering Systems KES 2006
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A motion adaptive algorithm for video de-interlacing is presented in this paper. It is based on a fuzzy inference system, which performs an interpolation between two linear techniques as a function of the motion level. Fuzzy systems with different number of 'if-then' rules have been analyzed and compared in terms of complexity as well as efficiency in de-interlacing benchmark video sequences.
FPGA Based Implementation of Fuzzy Controllers for Internet Traffic
F. Montesino, A. Barriga, D.R. López and S. Sánchez-Solano
Conference · Iberchip XII Workshop IWS 2006
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Recent research results propose and show the usefulness of a fuzzy control based approach to the development of intelligent systems for congestion control in Internet routers. However, adoption of this new technology is handicapped because of operational requirements, mostly in terms of inference speed, a hard constrain on the practical implementation of key traffic controlling systems. We report on the implementation of intelligent fuzzy controllers for Internet traffic using an FPGA based prototyping platform. A development methodology and a tool chain, a flexible and open prototyping platform, a set of fuzzy controllers and implementation results for a number of traffic controllers are presented. Our prototypes are shown to satisfy the requirements of high performance routing hardware deployed in the current Internet.
Desarrollo de Módulos-IP de Controladores Difusos para el Diseño de Sistemas Empotrados sobre FPGAs
M. Brox, A. Gersnoviez, S. Sánchez-Solano, A.J. Cabrera and I. Baturone
Conference · VII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2006
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En esta comunicación se describe el diseño de controladores basados en lógica difusa como módulos de Propiedad Intelectual (IP) compatibles con los sistemas de procesado disponibles en las familias de FPGAs de Xilinx. El trabajo fue propuesto como caso práctico de un curso de postgrado de diseño de sistemas empotrados sobre FPGAs. Su realización permitió reforzar los conocimientos de los alumnos en disciplinas relacionadas con: diseño de sistemas digitales, arquitectura de computadores, codiseño hardware-software y aplicaciones de control.
Control difuso de la tasa de transferencia de extremo a extremo en protocolos de transporte de Internet
F. Montesino, D.R. López, A. Barriga and S. Sánchez-Solano
Conference · XIII Congreso Español de Tecnologías y Lógica Fuzzy ESTYLF 2006
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La dinámica del tráfico de extremo a extremo en Internet es un problema complejo para el cual los modelos disponibles son, en el mejor de los casos incompletos. Esta comunicación describe nuevos mecanismos para regulación de la tasa de transferencia de extremo a extremo en la capa de transporte por medio de sistemas difusos. Se describen una generalización basada en lógica difusa de los mecanismos de control de flujo y congestión de TCP (Transport Control Protocol), el diseño de un regulador difuso basado en mecanismo de ventana para TCP, así como la metodología de diseño empleada para simular e implementar de manera experimental el sistema. Se resume un estudio comparativo del regulador difuso presentado frente a los mecanismos tradicionales. El regulador difuso resulta útil como enfoque de modelado y proporciona significativas mejoras de prestaciones respecto a un conjunto de criterios.
Controladores difusos adaptativos como módulos de propiedad intelectual para FPGAs
S. Sánchez-Solano, A.J. Cabrera, M. Brox and A.J. González
Conference · Iberchip XII Workshop IWS 2006
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La continua demanda por parte del mercado microelectrónico de aplicaciones novedosas, con elevados niveles de complejidad y tiempos de desarrollo cortos ha motivado el impulso de las técnicas de diseño basadas en el concepto de 'reusabilidad' y el desarrollo de elementos de sistemas como módulos de propiedad intelectual o módulos IP. En esta comunicación se describe la implementación de controladores difusos como módulos IP para FPGAs. Los controladores operan como periféricos conectables al bus OPB para los procesadores disponibles en las FPGAs de Xilinx. El empleo de las memorias internas de las FPGAs para almacenar las bases de conocimiento permite definir o ajustar la funcionalidad en tiempo de operación.
Controlador difuso para problemas de navegación en presencia de obstáculos fijos
M. Brox, A. Gersnoviez, S. Sánchez-Solano and I. Baturone
Conference · XIII Congreso Español de Tecnologías y Lógica Fuzzy ESTYLF 2006
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En esta comunicación se describe un sistema de control difuso para aplicaciones de navegación de robots móviles autónomos en presencia de obstáculos fijos. Las herramientas de CAD del entorno Xfuzzy 3, desarrollado en el IMSE, han facilitado el diseño del controlador. En la comunicación se procede a la verificación del controlador diseñado operando en un lazo cerrado con el modelo del robot móvil autónomo eléctrico Romeo 4R, diseñado y construido en la Escuela Superior de Ingenieros de la Universidad de Sevilla. Las simulaciones realizadas demuestran la eficiencia del controlador desarrollado.
Algoritmo adaptativo con el grado de movimiento para el desentrelazado de vídeo
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutiérrez-Ríos and F. Fernández-Hernández
Conference · XIII Congreso Español de Tecnologías y Lógica Fuzzy ESTYLF 2006
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En esta comunicación se presenta un algoritmo adaptativo con el movimiento para el desentrelazado de vídeo. Se basa en un sistema de inferencia difuso, que realiza una interpolación entre dos técnicas lineales en función del grado de movimiento. Se ha realizado un estudio de diferentes sistemas difusos con distinto número de funciones de pertenencia, analizándose el grado de complejidad de los mismos frente a su eficacia desentrelazando varias secuencias de vídeo.
A Fuzzy Motion Adaptive Algorithm for Interlaced-to-Progressive Conversion
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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Interlaced-to-progressive algorithms are currently required by video format conversion systems in order to display a progressive scanning used in modern visualization equipments. Deinterlacing algorithms use interpolation techniques to calculate missing pixels in transmitted fields. A motion adaptive algorithm which employs fuzzy logic to adapt the interpolation strategy to the presence of motion in the images is proposed in this paper. The performance of this new approach is evaluated by extensive simulation of different video sequences.
Fuzzy end-to-end rate control for Internet transport protocols
F. Montesino, D.R. López, A. Barriga and S. Sánchez-Solano
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2006
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End-to-end Internet packet dynamics is a complex problem for which models available to date are at best incomplete. A major research problem in Internet transport layer protocols is the development of rate control mechanisms that can cope with the requirements of a growing diversity of technologies, applications and services. This paper describes novel mechanisms for intelligent end-to-end traffic rate control in Internet by means of fuzzy systems. We first outline a fuzzy logic based generalization of TCP (Transport Control Protocol) rate control principles. The design of a fuzzy TCP-like window-based rate controller is then described. A systematic fuzzy systems design methodology is used in order to simulate and implement the system as an experimental tool. A comparative evaluation of simulation and implementation results from the fuzzy rate controller as compared to that of traditional controllers is outlined. Besides being a useful modelling approach, the fuzzy rule based rate controller is shown to outperform other approaches with regards to a number of criteria.
Development of IP modules of fuzzy controllers for the design of embedded systems on FPGAs
M. Brox and S. Sánchez-Solano
Conference · IEEE Int. Conference on Field Programmable Logic and Applications FPL 2006
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This paper describes the design of fuzzy logic-based controllers as IP modules compatible with the processing systems available in the current families from Xilinx. These modules can be used as standard peripherals connectable to the OPB bus for the processors available in FPGAs, such as MicroBlaze or Power PC. The use of inference techniques based on fuzzy logic allows the development of complex control systems from the linguistic description of the knowledge of an expert operator, without any need to employ mathematical models, and provides good robustness in the face of changing operational conditions.
Directional motion adaptive fuzzy method for video de-interlacing
J. Gutiérrez-Ríos, F. Fernández-Hernández, P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Conference · Artificial Neural Networks in Engineering ANNIE 2005
abstract
The procedure employed to make de-interlacing of video sequences has great influence in the quality of the obtained image. Reaching good results is not possible if dynamical characteristics of the processed image are not considered. On the other hand, the gradual adjust of the de-interlacing procedure as a function of the motion detected in each pixel of the image is a powerful method that is able to be realised by means of fuzzy inference. Detection of motion direction in each pixel of a frame becomes important in order to choose inclination in the spatial interpolation operations. In this paper we start from a fuzzy algorithm proposed by Van de Ville et al. to succeed in a family of more efficient algorithms under the point of view of execution speed and quality. These algorithms are based on convolution techniques (in substitution of the sum-prod norms) that are able to create a good emphasising distribution on the input variables.
Progressive scan conversion based on edge-dependent interpolation using fuzzy logic
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Conf. of the European Society for Fuzzy Logic and Technology & 11th French Days on Fuzzy Logic and Applications EUSFLAT-LFA 2005
abstract
De-interlacing algorithms realize the interlaced to progressive conversion required in many applications. The most cost efficient are intra-field techniques which interpolate pixels of the same field. Some of these methods use the upper and lower line pixels. Among them, the ELA algorithm is widely employed since it reconstructs the edges of the de-interlaced image with more accuracy eliminating nondesired problems such as blurring and staircase effects. However, the ELA algorithm does not perform well when there are non clear edges or in presence of noise. In order to reduce these drawbacks, a new algorithm is presented in this paper. It is based on a simple fuzzy system which models heuristic rules to improve the ELA algorithm. Two enhancements of this new algorithm are also presented in this paper. Simulation results of video sequences prove the advantageous of the new algorithms.
Piecewise Linear Function Interpolation Using Lukasiewicz's Operators
N.M. Hussein-Hassan, A. Barriga and S. Sánchez-Solano
Conference · Int. Symposium on Innovations in Intelligent System and Applications INISTA 2005
abstract
Abstract not available
Interlaced to progressive scan conversion using a fuzzy edge-based line average algorithm
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE International Workshop on Intelligent Signal Processing WISP 2005
abstract
De-interlacing methods realize the interfaced to progressive conversion required in many applications. Among them, intra-field methods are widely used for their good trade off between performance and computational cost. In particular, the ELA algorithm is well-known for its advantages in reconstructing the edges of the images, although it degrades the image quality where the edges are not clear. The algorithm proposed in this paper uses a simple fuzzy system which models heuristic rules to improve the ELA rules. It can be implemented easily in software and hardware since the increase in computational cost is very low. Simulation results are included to illustrate the advantages of the proposed fuzzy ELA algorithm in de-interlacing, non noisy and noisy images.
Embedded fuzzy controllers on standard DSPs
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano, V. Blanco and J. Ferruz
Conference · IEEE International Symposium on Industrial Electronics ISIE 2005
abstract
Fuzzy controllers are used in many applications because of their rapid design by translating heuristic knowledge, robustness against perturbations, and smoothness in the control action. However, they require parallel processing and special operators (such as fuzzification or defuzzification) which are not available at standard DSPs, thus making inefficient its direct implementation. This paper describes a design methodology which allows starting with any kind of fuzzy controller and subsequently transforming it until obtaining a system suitable for DSP implementation. Such methodology is aided by Xfuzzy 3, a design environment developed by some of the authors. The parking problem of an autonomous robot is described to illustrate the steps of this methodology. Experimental results show the efficiency of the designed fuzzy controller embedded into a stand-alone card based on a fixed-point DSP from Texas Instruments.
Fuzzy logic activities at the Microelectronics Institute of Seville
A. Barriga, S. Sánchez-Solano, I. Baturone, F. Moreno-Velo, P. Brox, F. Montesino, N.M. Hussein, M. Brox and A. Gersnoviez
Conference · XVI Italian Workshop on Neural Nets WIRN 2005
abstract
In this communication we present the activities related to the development of fuzzy logic based systems at the Microelectronics Institute of Seville (Spain). These activities regard with the design of circuits and systems that operate in fuzzy logic, the development of CAD tools for fuzzy logic and the accomplishment of applications that use fuzzy logic in the resolution of certain problems.
FPGA implementation of a fuzzy based video de-interlacing algorithm
P. Brox, S. Sánchez-Solano, I. Baturone and A. Barriga
Conference · Conference on VLSI Circuits and Systems II, 2005
abstract
De-interlacing algorithms are used to convert interlaced video into progressive scan format. Among the different techniques reported in the literature, motion adaptive de-interlacing techniques that combine spatial and temporal interpolation according to the presence of motion achieve good results with a low computational cost. This paper presents the FPGA implementation of a motion adaptive algorithm which employs fuzzy logic in detecting motion and edges. Motion, which is evaluated at each pixel of the deinterlaced frame, determines the interpolation between an enhanced edge-dependent line average method and field insertion. Extensive simulations with video sequences show the advantages performance of the proposed method over other well-known de-interlacing techniques. The hardware implementation of the algorithm has been carried out on a FPGA obtaining a low-cost solution for real-time processing.
Codiseño Hardware/Software de controladores difusos mediante módulos de propiedad intelectual
A. Barriga, I. Barturone, P. Brox, A. Cabrera, F.J. Moreno and S. Sánchez-Solano
Conference · VI Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2004
abstract
El uso de técnicas de diseño basadas en módulos de propiedad intelectual (IP) constituye una alternativa válida para salvar la creciente distancia entre los recursos proporcionados por las actuales tecnologías de fabricación de circuitos integrados y la productividad alcanzada por los diseñadores de sistemas. Esta comunicación describe el desarrollo de un sistema de control basado en lógica difusa mediante una técnica de codiseño hardware/software que combina un procesador de propósito general disponible como módulo-IP y hardware específico para la síntesis del módulo de inferencia. La implementación física se ha llevado a cabo mediante una plataforma de desarrollo basada en FPGAs, lo que permite la realización de todo el sistema como un SoPC (System on Programmable Chip).
Development of fuzzy control systems on programmable chips: Application to motion planning of mobile robots
A. Cabrera, S. Sánchez-Solano, I. Baturone, F. Moreno-Velo, P. Brox and A. Barriga
Conference · International Symposium on Robotics and Applications ISORA 2004
abstract
This paper describes the realization of embedded fuzzy control systems for planning the motion of autonomous mobile robots. The development of the controllers is carried out by means of a reconfigurable platform based on FPGAs. This platform combines a general-purpose processor with specific hardware to implement fuzzy inference modules, thus allowing the comparison between a fully software solution and others based on hybrid hardware/software techniques. Both the processing system and the inference modules are configurable using available CAD tools, which make the development of the controllers easier.
The parametric definition of membership functions in XFL3
F.J. Moreno-Velo, I. Baturone, S. Sánchez-Solano and A. Barriga
Conference · Annual IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2004
abstract
This paper presents a study of the different kinds of membership function (MF) definitions, regarding free MFs and families of MFs, and describes the capabilities of XFL3 (the formal specification language defined by Xfuzzy 3) to manage them. This includes not only the possibility of using them in a system design, but also the capability for extending the available functions with new user-defined membership functions and families. An application example has been included in order to discuss on the suitable parametric definition of the functions.
Implementación sobre FPGAs de sistemas difusos programables
S. Sánchez-Solano, A. Cabrera, C.J. Jiménez, P. Brox, I. Baturone and A. Barriga
Conference · Workshop IBERCHIP 2003
abstract
El número de aplicaciones electrónicas que utilizan soluciones basadas en lógica difusa se ha incrementado considerablemente en los últimos años y, de forma paralela, se han desarrollado nuevas herramientas de CAD que contemplan diferentes técnicas de implementación para este tipo de sistemas. De entre ellas, el uso de arquitecturas específicas de procesado implementadas sobre FPGAs presenta como principales ventajas una buena relación 'coste-rendimiento' y un ciclo de desarrollo aceptablemente corto. En esta comunicación se analizan las distintas facilidades de síntesis que proporciona el entorno de diseño Xfuzzy para la implementación de sistemas difusos programables que aprovechen los recursos disponibles en las actuales familias de FPGAs.
VHDL high level modelling and implementation of fuzzy systems
A. Barriga, S. Sánchez-Solano, P. Brox, A. Cabrera and I. Baturone
Conference · International Workshop on Fuzzy Logic and Applications WILF 2003
abstract
In this paper we illustrate a fuzzy logic system design strategy based on a high level description. Employing this high level description, the knowledge base is described in a language in appearance close to the natural language with the particularity that it uses a hardware description language (VHDL) directly synthesizable on an FPGA circuit. In addition, we analyze FPCA implementations of different fuzzy inference hardware architectures in order to characterize them in terms of area and speed.
Optimizing the design of a fuzzy path planner for car-like autonomous robots
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano and A. Ollero
Conference · International Conference on Advanced Robotics ICAR 2003
abstract
This paper presents methods and tools to design a fuzzy path planner for autonomous non-holonomic vehicles by means of supervised learning. The method combines heuristic knowledge and geometric considerations to obtain a continuous-curvature short path that can be executed efficiently by the path tracking controller of the mobile robot. Furthermore, the method minimizes the computer requirements to implement the fuzzy planner. The proposed design method can be easily carried out by means of the Xfuzzy 3.0 environment developed by some of the authors. The resulting planning strategies have been proven successfully in the Romeo 4R autonomous vehicle fully designed and built at the Escuela Superíor de Ingenieros, University of Seville.
Tuning complex fuzzy systems by supervised learning algorithms
F.J. Moreno-Velo, I. Baturone, R. Senhadji and S. Sánchez-Solano
Conference · IEEE International Conference on Fuzzy Systems FUZZ 2003
abstract
Tuning a fuzzy system to meet a given set of input/output patterns is usually a difficult task that involves many parameters. This paper presents an study of different approaches that can be applied to perform this tuning process automatically, and describes a CAD tool, named xfs1, which allows applying a wide set of these approaches: (a) a large number of supervised learning algorithms; (b) different processes to simplify the learned system; (c) tuning only specific parameters of the system; (d) the ability to tune hierarchical fuzzy systems, systems with continuous output (like fuzzy controller) as well as with categorical output (like fuzzy classifiers), and even systems that employ user-defined fuzzy functions; and, finally, (e) the ability to employ this tuning within the design flow of a fuzzy system, because xfs1 is integrated into the fuzzy system development environment Xfuzzy 3.0.
Rapid design of fuzzy systems with XFUZZY
F.J.M. Velo, I. Baturone, S. Sánchez-Solano and A. Barriga
Conference · IEEE International Conference on Fuzzy Systems FUZZ 2003
abstract
The crecient use of fuzzy systems in complex applications has motivated us to develop a new version of Xfuzzy, the design environment for fuzzy system created at the IMSE (Instituto de Microelectronica de Sevilla). This new version, Xfuzzy 3.0, offers the advantages of being enterely programmed in Java, and allows designing hierarchical rule bases that can interchange fuzzy or non fuzzy values as well as employ user-defined fuzzy connectives, linguistic hedges, membership functions, and defuzzification methods. Xfuzzy 3.0 integrates tools that facilitate the description, tuning, verification, and synthesis of complex fuzzy systems. This is illustrated in this paper with the design of a fuzzy controller to solve a parking problem.
Hardware/Software Codesign Methodology for Fuzzy Controller Implementation
A. Cabrera, S. Sánchez-Solano, R. Senhadji, A. Barriga, C.J. Jiménez-Fernández
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2002
abstract
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This paper describes a HW/SW codesign methodology for the implementation of fuzzy controllers on a platform composed by a general-purpose microcontroller and specific processing elements implemented on FPGAs or ASICs. The different phases of the methodology, as well as the CAD tools used in each design stage, are presented, with emphasis on the fuzzy system development environment Xfuzzy. Also included is a practical application of the described methodology for the development of a fuzzy controller for a dosage system.
Development of level controllers based on fuzzy logic
A. Cabrera, R. Senhadji, S. Sánchez-Solano, A. Barriga, C.J. Jiménez-Fernández and O. Llanes
Conference · International ICSC-NAISO Congress on Neuro-Fuzzy Technologies NF 2002
abstract
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This paper describes the development of different kinds of level controllers based on fuzzy logic. Designs and implementations were carried out using tools from xfuzzy, a development environment that eases the different stages in the design of fuzzy inference systems. Special emphasis has been put in the on-line verification of the controller over a physical plant by means of xflab tool. Different approaches of the knowledge base were tested using xflab. Then, the results were analyzed and selected those that gave the better performance. Controllers implementations with different number of bit for input/output resolution were also carried out and analyzed. The results provide a base for the incoming development of a hardware fuzzy logic controller by means of specific hardware or by an embedded codesign system.
Herramientas de CAD para la síntesis de sistemas de interferencia difusos mediante FPGAs
S. Sánchez-Solano, A. Cabrera, C.J. Jiménez Fernández and D.R. López
Conference · V Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2002
abstract
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En esta comunicación se describe un flujo de diseño que permite automatizar el proceso de síntesis sobre FPGAs de sistemas de inferencia basados en lógica difusa. El entorno de CAD utilizado combina herramientas específicas desarrolladas por los autores con versiones educativas de herramientas comerciales de diseño de sistemas digitales. Todas las herramientas pueden ser ejecutadas sobre entornos MS-Windows, lo que facilita su utilización en aulas informáticas.
NORFREA: An algorithm for non redundant fuzzy rule extraction
R. Senhadji, S. Sánchez-Solano, A. Barriga, I. Baturone and F.J. Moreno-Velo
Conference · IEEE Int. Conference on Systems, Man and Cybernetics 2002
abstract
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This contribution presents a new algorithm (NORFREA) to select fuzzy rules from a grid partition of the input domain. Besides using an efficiency measure for the rules, this algorithm employs an heuristic technique to reduce the influence of the initial grid structure. Different benchmarks of classification problems are included to illustrate the advantages of this algorithm.
Automatic design of fuzzy control systems for autonomous mobile robots
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano and R.M. de Agar
Conference · IEEE Industrial Electronics Conference IECON 2002
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This paper describes the design and implementation of a fuzzy controller for autonomous mobile robots. The tool Xfuzzy 3.0, developed at the IMSE (Instituto de Microelectronica de Sevilla) has been used to design a controller for the Romeo 4R autonomous vehicle designed and built at the "Escuela SupeRíor de Ingenieros", University of Seville. The paper presents the design of the controller and real experiments with Romeo 4R demonstrating the efficiency of the controller.
Prototyping of fuzzy logic-based controllers using standard FPGA development boards
S. Sánchez-Solano, R. Senhadji, A. Cabrera, I. Baturone, C.J. Jiménez and A. Barriga
Conference · IEEE International Workshop on Rapid System Prototyping RSP 2002
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This paper describes a design methodology for fuzzy logic-based control systems. The methodology employs hardware/software codesign techniques according to an 'a priori' partition of the tasks assigned to the selected components. This feature makes it possible to tackle the control system prototyping as one of the design stages. In our case, the platform considered for prototyping has been a development board containing a standard microcontroller and an FPGA. Experimental results from an actual control application validate the efficiency of this methodology.
Books
Fuzzy logic-based algorithms for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Book · STUDFUZZ, vol. 246, 184 p, 2010
abstract
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The Fuzzy Logic research group of the Microelectronics Institute of Seville is composed of researchers who have been doing research on fuzzy logic since the beginning of the 1990s. Mainly, this research has been focused on the microelectronic design of fuzzy logic-based systems using implementation techniques which range from ASICs to FPGAs and DSPs. Another active line was the development of a CAD environment, named Xfuzzy, to ease such design. Several versions of Xfuzzy have been and are being currently developed by the group. The addressed applications had basically belonged to the control field domain. In this sense, several problems without a linear control solution had been studied thoroughly. Some examples are the navigation control of an autonomous mobile robot and the level control of a dosage system.
This book is organized in five chapters. In Chapter 1, some basic concepts are explained to completely understand the contribution of the algorithms developed in this research work. The evaluation of how motion is present and how it influences on de-interlacing is studied in Chapter 2. The design options of the proposed fuzzy motion-adaptive de-interlacing algorithm is studied in Chapter 3. A spatial interpolator that adapts the interpolation to the presence of edges in a fuzzy way is developed in Chapter 4. A temporal interpolator that adapts the strategy of the interpolation to possible repetition of areas of fields is presented in Chapter 5. Using both interpolators in the fuzzy motion-adaptive algorithm described in Chapter 3 clearly improves the de-interlaced results.
Book Chapters
Performance Analysis of Multimedia Traffic
F. Montesino, D.R. López, A. Barriga and S. Sánchez-Solano
Book Chapter · Encyclopedia of Networked and Virtual Organizations, pp 1196-1203, 2008
abstract
doi
The Internet and, more specifically, Web-based applications now provide the first-ever global, easy-to-use, ubiquitous and economical communications channel. Most companies have already automated their operations to some extent, which enhances their ability to interact with other companies electronically. With the advent of Web services, the interaction between companies becomes easier and more transparent (Khalaf, Curbera, Nagy, Tai, Mukhi, & Duftler, 2005). Web-based technologies are extensively employed and support core components of virtual and networked organizations. Many of them, including for instance Web-based communities, heavily rely on Web traffic. Additionally, Web technologies play a central role in the technologies for supporting industrial virtual enterprises (VE) being developed by the National Industrial Information Infrastructure Protocols Consortium (NIIIP). Thus, modelling and analysis techniques for Web traffic become important tools for performance analysis of virtual organizations (Malhotra, 2000; Foster, Kesselman, & Tuecke, 2001). This article overviews current models of Web traffic as well as performance analysis of Web-based systems.
Performance Measurement of Computer Networks
F. Montesino, D.R. López, A. Barriga and S. Sánchez-Solano
Book Chapter · Encyclopedia of Networked and Virtual Organizations, pp 1216-1222, 2008
abstract
doi
The Internet and, more specifically, Web-based applications now provide the first-ever global, easy-to-use, ubiquitous and economical communications channel. Most companies have already automated their operations to some extent, which enhances their ability to interact with other companies electronically. With the advent of Web services, the interaction between companies becomes easier and more transparent (Khalaf, Curbera, Nagy, Tai, Mukhi, & Duftler, 2005). Web-based technologies are extensively employed and support core components of virtual and networked organizations. Many of them, including for instance Web-based communities, heavily rely on Web traffic. Additionally, Web technologies play a central role in the technologies for supporting industrial virtual enterprises (VE) being developed by the National Industrial Information Infrastructure Protocols Consortium (NIIIP). Thus, modelling and analysis techniques for Web traffic become important tools for performance analysis of virtual organizations (Malhotra, 2000; Foster, Kesselman, & Tuecke, 2001). This article overviews current models of Web traffic as well as performance analysis of Web-based systems.
Performance Analysis of Peer-to-Peer Traffic
F. Montesino, D.R. López, A. Barriga and S. Sánchez-Solano
Book Chapter · Encyclopedia of Networked and Virtual Organizations, pp 1210-1215, 2008
abstract
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Peer-to-peer (P2P) networks have recently emerged as an attractive solution to enable large-scale content distribution without requiring major infrastructure investments. Recent developments have led to a significant maturity increase of peer-to-peer technologies, which are currently available as tools for performing core tasks in virtual and networked organizations.
A fuzzy edge-dependent interpolation algorithm
P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Book Chapter · Soft Computing in Image Processing: Recent Advances, STUDFUZZ, vol. 210, pp 157-183, 2007
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Images have always been very important in human life. Their applications range from primitive communication between humans of all ages to advanced technologies in the industrial, medical and military field. The increased possibilities to capture and analyze images have contributed to the largeness that the scientific field of "image processing" has become today. Many techniques are being applied, including soft computing.
Performance analysis and models of web traffic
F. Montesino-Pouzols, D.R. López, A. Barriga-Barros and S. Sánchez-Solano
Book Chapter · Encyclopedia of Networked and Virtual Organizations, pp 1196-1203, 2007
abstract
doi
The Internet and, more specifically, Web-based applications now provide the first-ever global, easy-to-use, ubiquitous and economical communications channel. Most companies have already automated their operations to some extent, which enhances their ability to interact with other companies electronically. With the advent of Web services, the interaction between companies becomes easier and more transparent (Khalaf, Curbera, Nagy, Tai, Mukhi, & Duftler, 2005). Web-based technologies are extensively employed and support core components of virtual and networked organizations. Many of them, including for instance Web-based communities, heavily rely on Web traffic. Additionally, Web technologies play a central role in the technologies for supporting industrial virtual enterprises (VE) being developed by the National Industrial Information Infrastructure Protocols Consortium (NIIIP). Thus, modelling and analysis techniques for Web traffic become important tools for performance analysis of virtual organizations (Malhotra, 2000; Foster, Kesselman, & Tuecke, 2001). This article overviews current models of Web traffic as well as performance analysis of Web-based systems.
Directional motion adaptive fuzzy method for video de-interlacing
J. Gutiérrez-Ríos, F. Fernández-Hernández, P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Book Chapter · Intelligent Engineering Systems Through Artificial Neural Networks, pp 567-577, 2005
abstract
The procedure employed to make de-interlacing of video sequences has great influence in the quality of the obtained image. Reaching good results is not possible if dynamical characteristics of the processed image are not considered. On the other hand, the gradual adjust of the de-interlacing procedure as a function of the motion detected in each pixel of the image is a powerful method that is able to be realised by means of fuzzy inference. Detection of motion direction in each pixel of a frame becomes important in order to choose inclination in the spatial interpolation operations. In this paper we start from a fuzzy algorithm proposed by Van de Ville et al. to succeed in a family of more efficient algorithms under the point of view of execution speed and quality. These algorithms are based on convolution techniques (in substitution of the sum-prod norms) that are able to create a good emphasising distribution on the input variables.
Other publications
Red de estudios sobre Soft Computing y sus aplicaciones tecnológicas y empresariales (RESCATE): Grupo de Lógica Difusa del IMSE-CNM
S. Sánchez-Solano
Presentation · Reunión de la Red RESCATE, Granada 2007
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El objetivo de la Red de Estudios sobre Soft Computing y sus Aplicaciones Tecnológicas y Empresariales (RESCATE) es poner en contacto a grupos de investigación del mundo académico-científico, con otros procedentes de los sectores empresarial e industrial con experiencia en temas de Soft Computing (SC) para lograr nuevos proyectos, desarrollos tecnológicos y productos innovadores y de calidad en el entorno de la I+D+i en SC. En esta presentación, correspondiente a la reunión de la Red RESCATE celebrada en Granada en febrero de 2007, se describe el Grupo de Lógica Difusa del Instituto de Microelectrónica de Sevilla (IMSE-CNM) y sus líneas de investigación.
