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Author: Luis F. Rojas Muñoz
Year: Since 2002
Journal Papers
Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management
S. Sánchez-Solano, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 24, no. 17, article 5674, 2024
abstract
doi
The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4
configurable logic blocks (CLBs) to accommodate the RO bank.
On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 23, no. 8, article 4070, 2023
abstract
doi
The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive set of on-line tests to obtain the metrics that determine its quality in terms of uniqueness, reliability, and entropy characteristics. The results obtained prove that the proposed module is a suitable candidate for various security applications. As an example, an implementation that uses less than 5% of the resources of a low-cost programmable device is capable of obfuscating and recovering 512-bit cryptographic keys with virtually zero error rate.
True Random Number Generation Capability of a Ring Oscillator PUF for Reconfigurable Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Electronics, vol. 11, no. 23, article 4028, 2022
abstract
doi
This paper presents the validation of a novel approach for a true-random number generator (TRNG) based on a ring oscillator-physical unclonable function (RO-PUF) for FPGA devices. The proposal takes advantage of the different noise sources that affect the electronic implementation of the RO-PUF to extract the entropy required to guarantee its function as a TRNG, without anything more than minimal changes to the original design. The new RO-PUF/TRNG architecture has been incorporated within a hybrid HW/SW embedded system designed for devices from the Xilinx Zynq-7000 family. The degree of randomness of the generated bit streams was assessed using the NIST 800-22 statistical test suite, while the validation of the RO-PUF proposal as an entropy source was carried out by fulfilling the NIST 800-90b recommendation. The features of the hybrid system were exploited to carry out the evaluation and validation processes proposed by the NIST publications, online and on the same platform. To establish the optimal configuration to generate bit streams with the appropriate entropy level, a statistical study of the degree of randomness was performed for multiple TRNG approaches derived from the different implementation modes and configuration options available on the original RO-PUF design. The results show that the RO-PUF/TRNG design is suitable for secure cryptographic applications, doubling its functionality without compromising the resource-efficiency trade-off already achieved in the design.
Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems
M.C. Martínez-Rodríguez, L.F. Rojas-Muñoz, E. Camacho-Ruiz, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 6, no.4, article 51, 2022
abstract
doi
The generation of unique identifiers extracted from the physical characteristics of the underlying hardware ensures the protection of electronic devices against counterfeiting and provides security to the data they store and process. This work describes the design of an efficient Physical Unclonable Function (PUF) based on the differences in the frequency of Ring Oscillators (ROs) with identical layout due to variations in the technological processes involved in the manufacture of the integrated circuit. The logic resources available in the Xilinx Series-7 programmable devices are exploited in the design to make it more compact and achieve an optimal bit-per-area rate. On the other hand, the design parameters can also be adjusted to provide a high bit-per-time rate for a particular target device. The PUF has been encapsulated as a configurable Intellectual Property (IP) module, providing it with an AXI4-Lite interface to ease its incorporation into embedded systems in combination with soft- or hard-core implementations of general-purpose processors. The capability of the proposed RO-PUF to generate implementation-dependent identifiers has been extensively tested, using a series of metrics to evaluate its reliability and robustness for different configuration options. Finally, in order to demonstrate its utility to improve system security, the identifiers provided by RO-PUFs implemented on different devices have been used in a Helper Data Algorithm (HDA) to obfuscate and retrieve a secret key.
Hardware/Software Co-Design of a Circle Detection System based on Evolutionary Computing
L.F. Rojas-Munoz, H. Rostro-Gonzalez, C.H. Garcia-Capulin and S. Sanchez-Solano
Journal Paper · Electronics, vol. 11, no. 17, article 2686, 2022
abstract
doi
In recent years, the strategy of co-designing Hardware/Software (HW/SW) systems has been widely adopted to exploit the synergy between both approaches thanks to technological advances that have led to more powerful devices providing an increasingly better cost-benefit trade-off. This paper presents an HW/SW system for the detection of multiple circles in digital images based on a genetic algorithm. It is implemented on an Ultra96-v2 development board, which contains a Xilinx Zynq UltraScale+ MPSoC device and supports a Linux operating system that facilitates application development. The design is powered by developing an interactive computing environment by means of the Jupyter Notebook platform, in which different programming languages coexist. The specific advantages of each of these languages have been used to describe the hardware component that accelerates the evolutionary computation for circle detection (VHDL), to execute SW-HW interaction functions, as well as the pre- and post-processing of the images (ANSI-C) and to code, evaluate, and document the system execution process (Python). As a result, a computationally efficient application was obtained, with high accuracy in the detection of circles in synthetic and real images, and with a high degree of reconfigurability that provides the user with the necessary tools to incorporate it in a specific area of interest.
Embedded system implementation of an evolutionary algorithm for circle detection on programmable devices
L.F.Rojas-Muñoz, S. Sánchez-Solano, C.H.García-Capulín and H. Rostro-González
Journal Paper · Computers & Electrical Engineering, vol. 99, article 107714, 2022
abstract
doi
Programmable devices combine powerful processing systems with a rich infrastructure of general-purpose and specific logic blocks, making it possible the efficient implementation of embedded systems to perform complex tasks by facilitating hardware acceleration of critical stages to improve their performance. Based on these characteristics, a hardware implementation of a genetic algorithm for circle detection in digital images is described in this paper. The detection system has been designed for Xilinx Zynq-7000 and Zynq UltraScale+ family devices and implemented on two low-cost development boards that reach acceleration factors of 33.12 and 37.3, respectively, when compared to the fully software implementation. Detection results from both development boards have been compared using synthetic and real images from different scenarios. The accuracy and performance achieved demonstrate the suitability of this proposal to design embedded systems with restricted size, resources and energy consumption for applications in Internet of Things, Industry 4.0 and other related paradigms.
Conferences
Digital Design Flow Based on Open Tools for Programmable Logic Devices
P. Navarro-Torrero, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez, A. Barriga-Barros, C.J. Jiménez-Fernández, M. Brox and P. Brox
Conference · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
abstract
doi
In this demonstrator, a design flow based on a set of open-source tools is showcased, enabling the simulation, synthesis, implementation, and programming of digital systems on programmable logic devices. Three academic examples, increasing in complexity, are shown running on open hardware development boards to demonstrate the validity of the digital design flow based on the APIO environment.
Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
abstract
doi
This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.
Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
P. Navarro-Torrero, L.F. Rojas-Muñoz, P. Brox and S. Sánchez-Solano
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
abstract
Abstract not available
Root of Trust Components to Increase Security of RISC-V Based Systems on Chips
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · RISC-V Summit Europe 5-9 June, 2023
abstract
Abstract not available
Análisis y evaluación de un RO-PUF como TRNG
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2023
abstract
Abstract not available
True Random Number Generator based on RO-PUF
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · Conference on Design of Circuits and Integrated Circuits DCIS 2022
abstract
The implementation of true random number generators is of vital importance to preserve the reliability of cryptographic systems. The lack of entropy can compromise their integrity, affecting the security of the entire chain of applications. Ensuring the effectiveness of a random number generator can be understood as reducing the risk of information loss due to possible attacks by third parties. This paper presents a novel approach for a true random number generator based on a Ring Oscillator- Physical Unclonable Function. Since the principle of operation of physical unclonable functions is based on the physical properties of each device, they can be used for security applications such as device identification, counterfeit prevention and increase the robustness of cryptographic functions. In addition, increasing the versatility of the design to use them as a source of entropy, they can also fulfill tasks such as generation of initialization vectors or nonces and keys for symmetric cryptography. The system incorporates multiple operating configurations, which allows a complete analysis of its performance to adapt it to different application scenarios. The randomness and correct operation of the proposed design have been evaluated online, by incorporating it into a hybrid HW/SW embedded system able to run the official test suite published by the National Institute of Standards and Technology without any need for post-processing. The architecture has been designed for Xilinx Zynq-700 family devices and implemented on the Pynq-Z2 development board.
SoPC Implementation of a Genetic Algorithm for Circle Detection
L.F. Rojas-Muñoz, S. Sánchez-Solano, C.H. García-Capulín and H. Rostro-González
Conference · IEEE International Autumn Meeting on Power, Electronics and Computing ROPEC 2021
abstract
This article presents a system-on-programable-chip implementation of a genetic algorithm for circle detection. The use of this implementation technique allows the development of an efficient, decentralized and embedded system with high scalability and robustness, in addition to providing it with an effective and easy-to-use interface. The hardware components of the system implement the evolutionary process and the software elements perform image pre-processing tasks and provide the user interface. The SoPC was implemented on a Zybo-Z7 development board equipped with a Xilinx Zynq-7000 family device and it has been numerically validated on synthetic and real images. Detection rates obtained for both types of images demonstrate the suitability of this proposal to design embedded systems with size, resources and power consumption limitations for applications in Industry 4.0 and other related paradigms.
Implementación en SoC de un Sistema Embebido para la Detección de Círculos en Imágenes Digitales
Luis F. Rojas-Muñoz, S. Sánchez-Solano, C.H. García-Capulín and H. Rostro-González
Conference · Congreso Internacional de Investigación Academia Journals Celaya CELAYA 2021
abstract
Los dispositivos basados en lógica programable que incorporan potentes sistemas de procesamiento permiten la implementación eficiente de sistemas embebidos que realizan tareas complejas, facilitando la aceleración en hardware de sus etapas críticas para mejorar su eficiencia. En este artículo se presenta el diseño de un sistema de detección de círculos en imágenes digitales basado en un algoritmo genético e implementado en la placa de desarrollo Pynq-Z2. Esta placa contiene un dispositivo Zynq-7000 SoC de Xilinx que incluye un procesador ARM Cortex-A9 de doble núcleo. Los beneficios que brindan la lógica programable y el
sistema de procesado son aprovechados para acelerar el algoritmo genético mediante su implementación en hardware y llevar a cabo las etapas de pre- y post-procesamiento de la imagen en software. La aplicación Jupyter Notebook, incorporada en el entorno de desarrollo PYNQ (Phython productivity for Zynq), permite utilizar funciones y librerías en Python para controlar de manera interactiva el flujo de datos entre los componentes software/hardware del sistema y los periféricos de entrada/salida. Los resultados obtenidos en precisión y rendimiento demuestran la idoneidad de esta propuesta para diseñar sistemas embebidos con tamaño, recursos y consumo de energía restringidos.
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