Noticias
Se buscan candidatos/as para un Contrato de Investigación de 2 años en el Instituto de Microelectrónica de Sevilla (IMSE-CNM) en la línea Microelectrónica para seguridad, con posibilidad de prórroga para realizar Tesis Doctoral en la Universidad de Sevilla (en el contexto de proyectos de I+D+i). [
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♦ Defensa de Trabajos Fin de Máster
- Diseño e implementación de un sistema para autenticación de voz.
Robinson Castillo Méndez
- Evaluación de Dispositivos Steep Slope para Computación Lógica.
Manuel Jiménez Través
- Metodología y herramientas para el desarrollo de aplicaciones de visión artificial basadas en OpenCV / OpenVX sobre FPGA.
José Ángel Martínez Trejo
12 Diciembre 2019
♦ PhD Talks. Facultad de Física (US)
Ciclo de conferencias de estudiantes de doctorado de la Facultad de Física y centros afines: Integrated system for neural stimulation with wireless power supply.
David Palomeque Mangut
4 Diciembre 2019
♦ Visitas al IMSE
IES Inca Garcilaso.
27 Noviembre 2019
Últimas publicaciones
A Dedicated Hardware Implementation for Biometric Recognition based on Finger Veins »
Nowadays, there is an increasing demand of security devices which include biometric authentication. Biometric recognition based on finger veins is very suitable for lightweight devices because it provides distinctiveness and the acquisition can employ small-size camera and low-cost sensors. Among the extraction techniques of features for finger veins, Wide Line Detector offers a good trade-off between recognition accuracy and computational complexity. A generic VHDL description has been developed for this feature extraction technique and the matching of the binary feature images. Implementation results on a Zynq 7020 FPGA are provided.
Conference -
IEEE International Conference on Electronics Circuits and Systems ICECS 2019
R. Arjona, J. Costas and I. Baturone
Low-power hardware implementation of SNN with decision block for recognition tasks »
We propose a fully configurable spiking convolutional node with rate saturation mechanism that can be used to implement arbitrary Convolutional Neural Networks (ConvNets) on FPGA. Using this node, a 4-layer ConvNet with 22 convolutional nodes and a decision block trained for poker card symbol recognition has been implemented in a Spartan6 FPGA, being tested with a stimulus where 40 poker cards where observed by a Dynamic Vision Sensor (DVS). In this paper, we study different strategies for the decision block to maximize the recognition rate with minimum power consumption.
Conference -
IEEE International Conference on Electronics Circuits and Systems ICECS 2019
L. A. Camuñas-Mesa, B. Linares-Barranco and T. Serrano-Gotarredona
Digital-Signal-Processor Realization of Izhikevich Neural Network for Real-Time Interaction with Electrophysiology Experiments »
The paper presents a realization on a digital signal processor of an Izhikevich Neural Network operating with biologically plausible real-time constants. The paper demonstrates the real-time realization of different neuron behavioral modes, i.e., regular spiking, chattering, bursting, and fast spiking under proper parametrization. Real-time spike-timing-dependentplasticity has also been embedded in the neural network realization. The paper studies the maximum array size that can be implemented on a TMS320C6455 microprocessor to be able to reproduce correctly the real-time dynamics of the different behaviors. The TMS320C6454, from the same DSP family as TMS320C6455, is embedded in a commercial microelectrode array system for real time interaction with biological neural cell cultures. As demonstrator, a simple classification of two binary patterns has been implemented. Upon learning activation, the system robustly unsupervisely learns to differentiate the two patterns.
Conference -
IEEE International Conference on Electronics Circuits and Systems ICECS 2019
J. Ahmadi-Farsani, B. Linares-Barranco and T. Serrano-Gotarredona
Demo: CNN Performance Prediction on a CPU-based Edge Platform »
The implementation of algorithms based on Dee p Learning at edge visual systems is currently a challenge. In addition to accuracy, the network architecture also has an impact on inference performance in terms of throughput and power consumption. This demo showcases per layer inference performance of various convolut ional neural networks running at a low cost edge platform . Furthermore, a n empirical model is applied to predict processing time and power consumption prior to actually running the networks A comparison between the prediction from our model and the actual inference performance is displayed in real time.
Conference -
International Conference on Sustainable Development in Civil Engineering ICSDC 2019
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez Vázquez
PhD Forum: A survey on FPGA-based high-resolution TDCs »
Time-to-digital converters based on Nutt method are especially suitable for FPGA implementation. They are able to provide high resolution, range and linearity with low resources usage. The core of this architecture consist in a coarse counter for long range, a fine time interpolator for high resolution and real-time calibration for high linearity. This paper reviews different time interpolation and real-time calibration techniques. Moreover, a comparison of state-of-the-art FPGA-based TDCs is presented as well.
Conference -
International Conference on Sustainable Development in Civil Engineering ICSDC 2019
M. Parsakordasiabi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
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