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Se buscan candidatos/as para un contrato predoctoral para la formación de doctores en el área de Tecnología Electrónica y de Comunicaciones asociada al Proyecto de Investigación TOGETHER (Dispositivos, circuitos y arquitecturas fiables y de bajo consumo para IoT).  [+ info] »
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Se buscan candidatos/as para un contrato de Titulado Superior en el área de Tecnología Electrónica y de Comunicaciones, asociado al Proyecto de Investigación MARAGDA (Aproximación multi-nivel al diseño orientado a la fiabilidad de circuitos integrados analógicos y digitales).  [+ info] »
IES Miguel Servet.
20 Marzo 2017
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16 Febrero 2017

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Últimas publicaciones
A CMOS Digital SiPM With Focal-Plane Light-Spot Statistics for DOI Computation  »
Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to improve the quality of the positron emission tomography images affected by the parallax error. This paper contemplates the computation of DOI based on the standard deviation of the light distribution. The simulations have been carried out by GAMOS. The design of the proposed digital silicon photomultiplier (d-SiPM) with focal plane detection of the center of mass position and dispersion of the scintillation light is presented. The d-SiPM shares the same off-chip time-to-digital converter such that each pixel can be individually connected to it. A miniature d-SiPM 8×8 single-photon avalanche-diode (SPAD) array has been fabricated as a proof of concept. The SPADs along each row and column are connected through an OR combination technique. It has 256×256μm2 without peripherals circuits and pads. The fill factor is about 11%. The average dark count rate of the mini d-SiPM is of 240 kHz. The average photon detection efficiency is 5% at 480 nm wavelength, room temperature, and 0.9 V excess voltage. The dynamic range is of 96 dB. The sensor array features a time resolution of 212 ps. The photon-timing SNR is 81 dB. The focal plane statistics of the light-spot has been proved as well by measurements.

Journal Paper - IEEE Sensors Journal, vol. 17, no. 3, pp 632-643, 2017 IEEE
DOI: 10.1109/JSEN.2016.2632200    ISSN: 1530-437X     » doi
I. Vornicu, F.N. Bandi and R. Carmona-Galán
Black-Box Calibration for ADCs with Hard Nonlinear Errors using a Novel INL-Based Additive Code: A Pipeline ADC Case Study  »
This paper presents a digital nonlinearity calibration technique for ADCs with strong input-output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affecting the ADC's performance. As a solution to this problem, this paper proposes a novel INL-based calibration which incorporates information from the ADC's internal signals to provide a robust estimation of static nonlinear errors for multivalued ADCs. The method is fully generalizable and can be applied to any existing design as long as there is access to internal digital signals. In pipeline or subranging ADCs, this implies access to partial subcodes before digital correction; for algorithmic or SAR ADCs, conversion bit/bits per cycle are used. As a proof-of-concept demonstrator, the experimental results for a 1.2 V 23 mW 130 nm-CMOS pipeline ADC with a SINAD of 58.4 dBc (in nominal conditions without calibration) is considered. In a stressed situation with 0.95 V of supply, the ADC has SINAD values of 47.8 dBc and 56.1 dBc, respectively, before and after calibration (total power consumption, including the calibration logic, being 15.4 mW).

Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, first online, 2017 IEEE
DOI: 10.1109/TCSI.2017.2662085    ISSN: 1549-8328    » doi
A.J. Ginés, E.J. Peralías and A. Rueda
System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor  »
This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, first online, 2017 IEEE
DOI: 10.1109/TBCAS.2016.2618319    ISSN: 1932-4545    » doi
M. Delgado-Restituto, A. Rodriguez-Perez, A. Darie, C. Soto, E. Fernandez and A. Rodriguez-Vazquez
Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction  »
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale invariance, which permits having the same response regardless of the distance of the scene to the camera. The chip comprises 176 x 120 photosensors arranged into 88 x 60 processing elements (PEs). The Gaussian pyramid is generated with a double-Euler switched capacitor (SC) network. Every PE comprises four photodiodes, one 8 b single-slope analog-to-digital converter, one correlated double sampling circuit, and four state capacitors with their corresponding switches to implement the double-Euler SC network. Every PE occupies 44 x 44 μm^2. Measurements from the chip are presented to assess the accuracy of the generated Gaussian pyramid for visual tracking applications. Error levels are below 2% full-scale output, thus making the chip feasible for these applications. Also, energy cost is 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions of imager plus microprocessor unit.

Journal Paper - IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp 483-495, 2017 IEEE
DOI: 10.1109/JSSC.2016.2610580    ISSN: 0018-9200    » doi
M. Suárez, V.M. Brea, J. Fernández-Berni, R. Carmona-Galán, D. Cabello and A. Rodríguez-Vázquez
SMASH ΔΣ modulator with adderless feed-forward loop filter  »
A novel cascade ΔΣ modulator, which combines the benefits of SMASH topology and feed-forward loop filter, is presented in this letter. The proposed ΔΣ architecture is based on moving the power-hungry adder block from the quantizer input to the first integrator output. The proposed architecture shows a better OTA linearity and relaxed OTA DC-gain compared to conventional MASH and SMASH topologies. This feature makes the modulator topology more suitable than conventional MASH and SMASH topologies for low-voltage applications.

Journal Paper - IET Electronics Letters, first online, 2017 IET
DOI: 10.1049/el.2016.4733    ISSN: 0013-5194    » doi
M. Honarparvar, J.M. de la Rosa, F. Nabki and M. Sawan

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