The collective behavior of many coupled oscillator systems is currently being explored for the implementation of different non-conventional computing paradigms. In particular, VO2 based nano-oscillators have been proposed to implement oscillatory neural networks that can serve as associative memories, useful in pattern recognition applications. Although the dynamics of a pair of coupled oscillators have already been extensively analyzed, in this paper, the topic is addressed more practically. Firstly, for the application mentioned above, each oscillator needs to be initialized in a given phase to represent the input pattern. We demonstrate the impact of this initialization mechanism on the final phase relationship of the oscillators. Secondly, such oscillatory networks are based on frequency synchronization, in which the impact of variability is critical. We carried out a comprehensive mathematical analysis of a pair of coupled oscillators taking into account both issues, which is a first step towards the design of the oscillatory neural networks for associative memory applications.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, first online, 2021 IEEE
DOI: 10.1109/TCSII.2021.3085133    ISSN: 1549-7747    » doi

In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and to understand the effects of these variability sources, an extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models and simulation tools needed to achieve reliable integrated circuits. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at nominal and accelerated aging conditions. To this end, a versatile transistor array chip and a flexible measurement setup have been used to reduce the required testing time to attainable values.

Journal Paper - Solid-State Electronics, vol. 185, article 108037, 2021 ELSEVIER
DOI: 10.1016/j.sse.2021.108037    ISSN: 0038-1101    » doi

This paper gives an overview of Cognitive-Radio (CR) circuits and systems, that will enable the implementation of new technology paradigms such as software-defined electronics and Artificial Intelligence (AI) managed Internet-of-Things (IoT). A survey of the state of the art, trends and design challenges is presented from a top-down perspective - from system-level to circuit and chip implementation. As an application, special emphasis is put on analog/digital interfaces as one of the key building blocks in CR-based devices. Cutting-edge architectures - mostly based on ΣΔ Modulators (ΣΔMs) - are discussed, as well as the best candidate circuit strategies to implement CR-based digitizers in deep nanometer CMOS.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020

The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired neuromorphic systems. Large-scale neuromorphic hardware platforms are being developed with increasing number of neurons and synapses, having a critical bottleneck in the online learning capabilities. Spike-timing-dependent plasticity (STDP) is a widely used learning mechanism inspired by biology which updates the synaptic weight as a function of the temporal correlation between pre- and post-synaptic spikes. In this work, we demonstrate experimentally that binary stochastic STDP learning can be obtained from a memristor when the appropriate pulses are applied at both sides of the device.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020

The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.

Conference - IEEE Latin America Electron Devices Conference LAEDC 2021