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El Ministerio de Economía y Competitividad publicó el pasado día 27 de septiembre la Propuesta de Resolución Provisional de los Proyectos I+D+i Excelencia y los Proyectos I+D+i Retos 2016. El Instituto de Microelectrónica de Sevilla ha obtenido la aprobación de los cinco proyectos presentados a ambas convocatorias, lo que supondrá una captación de fondos cercana a un millón de euros. Los proyectos, desarrollados por equipos de investigación mixtos pertenecientes a la Universidad de Sevilla y el CSIC, se centrarán en el diseño de circuitos microelectrónicos y su uso en aplicaciones espaciales, microelectrónica para seguridad y sistemas biomédicos.
El capítulo español de "IEEE Circuits and Systems Society", presidido por el Prof. José M. de la Rosa, del Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), ha recibido el premio al mejor capítulo de la Sección Española de IEEE en 2016. La ceremonia de entrega de premios tuvo lugar el pasado 7 de octubre en Barcelona, con motivo de la celebración del evento "IEEE DAY".
Caracterización de bioimpedancias para la calibración de sensores de presión capacitivos MEMs en aplicaciones cardiovasculares.
David Rivas Marchena
23 Septiembre 2016&

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Últimas publicaciones
Special issue on architectures of smart cameras for real-time applications  »
This special issue focuses on those topics having an incidence on the smart camera architecture, either emerging from the design of smart sensing and processing devices or imposed by the specifications for a particular distributed camera network and its applications. The collection of papers presented here starts by emphasizing the influence of the architecture in the performance of smart camera systems.

Journal Paper - Journal of Real-Time Image Processing, first online, 2016 SPRINGER
DOI: 10.1007/s11554-016-0567-1    ISSN: 1861-8200    » doi
R. Carmona-Galán, F. Berry, R. Kleihorst and D. Ginhac
Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis  »
This paper focuses on the implementation of different techniques for the integration of yield estimation in the synthesis loop of analog integrated circuits (ICs). MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is considered to be a very powerful multi-objective optimization algorithm. For the consideration of yield, several techniques are discussed and three different yield-aware Pareto front (PF) generation techniques have been implemented on the MOEA/D optimizer. The implemented yield-aware PF techniques are compared by designing a fully-differential folded-cascode amplifier with different number of objectives. In order to embed the variation effects into the optimization loop, the statistical analysis of the circuit has been carried out by using a Quasi Monte Carlo (QMC) technique. The results suggest that especially two of these techniques look promising for high dimensional robust optimization of analog circuits.

Journal Paper - Integration, the VLSI Journal, Article in Press, first online, 2016 ELSEVIER
DOI: 10.1016/j.vlsi.2016.04.004    ISSN: 0167-9260    » doi
M. Paka, F.V. Fernandez and G. Dundar
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links  »
Asynchronous handshaken interchip links are very popular among neuromorphic full-custom chips due to their delay-insensitive and high-speed properties. Of special interest are those links that minimize bit-line transitions for power saving, such as the two-phase handshaken non-return-to-zero (NRZ) 2-of-7 protocol used in the SpiNNaker chips. Interfacing such custom chip links to field-programmable gate arrays (FPGAs) is always of great interest, so that additional functionalities can be experimented and exploited for producing more versatile systems. Present-day commercial FPGAs operate typically in synchronous mode, thus making it necessary to incorporate synchronizers when interfacing with asynchronous chips. This introduces extra latencies and precludes pipelining, deteriorating transmission speed, particularly when sending multisymbols per unit communication packet. In this brief, we present a technique that learns to estimate the delay of a symbol transaction, thus allowing a fast pipelining from symbol to symbol. The technique has been tested on links between FPGAs and SpiNNaker chips, achieving the same throughput as fully asynchronous synchronizerless links between SpiNNaker chips. The links have been tested for periods of over one week without any transaction failure. Verilog codes of FPGA circuits are available as additional material for download.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 8, pp 763-767, 2016 IEEE
DOI: 10.1109/TCSII.2016.2531092    ISSN: 1549-7747    » doi
A. Yousefzadeh, L.A. Plana, S. Temple, T. Serrano-Gotarredona, S.B. Furber and B. Linares-Barranco
CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements  »
This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35 μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.

Journal Paper - IEEE Transactions on Nuclear Science, vol. 63, no. 4, pp. 2379-2389, 2016 IEEE
DOI: 10.1109/TNS.2016.2586140    ISSN: 0018-9499    » doi
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutierrez and M.A. Lagos-Florido
SpotEgg: An image-processing tool for automatised analysis of colouration and spottiness  »
Colouration and patterning are widespread amongst organisms. Regarding avian eggs, colouration (reflectances) has been previously measured using spectrometers whereas spottiness has been determined using human-based scoring methods or by applying global thresholding over the luminance channel on photographs. However, the availability of powerful computers and digital image-processing algorithms and software offers new possibilities to develop systematised, automatable, and accurate methods to characterise visual information in eggs. Here, we provide a computing infrastructure (library of functions and a Graphical User Interface) for eggshell colouration and spottiness analysis called SpotEgg, which runs over MATLAB. Compared to previous methods, our method offers four novelties for eggshell visual analysis. First, we have developed a standardised non-human biased method to determine spottiness. Spottiness determination is based on four parameters that allow direct comparisons between studies and may improve results when relating colouration and patterning to pigment extraction. Second, researcher time devoted to routine tasks is remarkably reduced thanks to the incorporation of image-processing techniques that automatically detect the colour reference chart and egg-like shapes in the scene. Third, SpotEgg reduces the errors in colour estimation through the eggshell that are created by the different angles of view subtended from different parts of the eggshell and the optical centre of the camera. Fourth, SpotEgg runs automatic Fractal Dimension analysis (a measure of how the details in a pattern change with the scale at which this pattern is measured) of the spots pattern in case researchers want to relate other measurements with this special spatial pattern. Finally, although initially conceived for eggshell analysis, SpotEgg can also be applied in images containing objects different from eggs as feathers, frogs, insects, etc., since it allows the user to manually draw any region to be analysed making this tool useful not only for oologist but also for other evolutionary biologists.

Journal Paper - Journal of Avian Biology, first online, 2016 BLACKWELL PUBLISHING
DOI: 10.1111/jav.01117    ISSN: 1600-048X    » doi
J. Gómez and G. Liñán-Cembrano

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