Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Bridging ICT and Medical Technologies for Smart Disease Diagnosis.
Myung Hoon Sunwoo, Ultra-small-sized Diagnostic and Smart Devices (uDSD) Research Center.
28 Junio 2019
La empresa Digilent Inc, en colaboración con el Instituto de Microelectrónica de Sevilla y la Escuela Politécnica Superior de la Universidad de Sevilla va a impartir en el mes de junio los siguientes workshops.
- Accelerate real-time high definition video processing designs with Digilent Zybo Z7, a Zynq-7000 AP SoC Platform and Xilinx Vivado HLS.
- Hands-on experimentation using Digilent Analog Discovery 2. Complete analog & digital circuits in or out of the lab.
17 y 18 de Junio de 2019
♦ Premio Mac Van Valkenburg 2019
El Dr. Ángel Rodríguez Vázquez, profesor de la Universidad de Sevilla e investigador del IMSE-CNM, ha sido galardonado con el Premio Mac Van Valkenburg de la sociedad IEEE-CAS, por sus destacadas contribuciones a la arquitectura de circuitos de señal mixta para dispositivos de vision inteligentes y procesamiento de datos 2-D. El galardón será entregado durante la celebración del congreso ISCAS 2019 el día 28 de Mayo de 2019.
Actividades presentadas por el Instituto de Microelectrónica de Sevilla en la 17ª Feria de la Ciencia.   [imágenes]
16-18 Mayo 2018

Ofertas de empleo en el IMSE

El Mundo de los Chips

Oferta de servicios basados en el sistema automático de test ATE Agilent 93000

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Últimas publicaciones
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop  »
In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 6, pp 989-1002, 2019 IEEE
DOI: 10.1109/TCAD.2018.2834394    ISSN: 0278-0070    » doi
R. Martins, N. Lourenço, F. Passos, R. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. Sieiro, F.V. Fernández and N. Horta
A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors  »
Random Telegraph Noise (RTN) has attracted increasing interest in the last years. This phenomenon introduces variability in the electrical properties of transistors, in particular in deeply-scaled CMOS technologies, which can cause performance degradation in circuits. In this work, the dependence of RTN parameters, namely current jump amplitude and emission and capture time constants, on the bias conditions, both VG and VD, has been studied on a set of devices, with a high granularity in a broad voltage range. The results obtained for the VG dependences corroborate previous works, but suggest a unique trend for all the devices in a VG range that goes from the near-threshold region up to voltages over the nominal operation bias. However, different trends have been observed in the parameters dependence for the case of VD. From the experimental data, the probabilities of occupation of the associated defects have been evaluated, pointing out large device-to-device dispersion in the VD dependences.

Journal Paper - Microelectronic Engineering, vol. 215, article 111004, 2019 ELSEVIER
DOI: 10.1016/j.mee.2019.111004    ISSN: 0167-9317    » doi
P. Saraza-Canflanca, J. Martin-Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Guest Editorial Special Issue on the 2019 IEEE International Symposium on Circuits and Systems  »
This special issue of the IEEE Transactions on Circuits and Systems-Part II: Express Briefs ( TCAS-II ) follows the successful co-publication initiative started last year by the IEEE Circuits and Systems Society (CASS) to publish a selection of the best papers accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS), held this year in Sapporo, Japan, on May 26-29. As TCAS-II only publishes five-page briefs, and hence both conference and journal versions of selected works would be largely overlapped, the papers included in this issue represent the only record published in IEEE Xplore and they will not appear in the Proceedings of IEEE ISCAS , which will however contain DOI links to the corresponding TCAS-II papers. Similar to other IEEE societies, IEEE-CASS intends to shift the role of IEEE conferences toward networking events as well as a scientific discussion opportunity, rather than putting the emphasis on the conference paper publication itself.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no.5, pp 717-717, 2019 IEEE
DOI: 10.1109/TCSII.2019.2909179    ISSN: 1549-7747    » doi
J.M. de la Rosa and Y. Nishio
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator  »
Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and timeefficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability.

Conference - Design Automation and Test in Europe DATE 2019
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors  »
Bias Temperature Instability has become a critical issue for circuit reliability. This phenomenon has been found to have a stochastic and discrete nature in nanometerscale CMOS technologies. To account for this random nature, massive experimental characterization is necessary so that the extracted model parameters are accurate enough. However, there is a lack of automated analysis tools for the extraction of the BTI parameters from the extensive amount of generated data in those massive characterization tests. In this paper, a novel algorithm that allows the precise and fully automated parameter extraction from experimental BTI recovery current traces is presented. This algorithm is based on the Maximum Likelihood Estimation principles, and is able to extract, in a robust and exact manner, the threshold voltage shifts and emission times associated to oxide trap emissions during BTI recovery, required to properly model the phenomenon.

Conference - Design Automation and Test in Europe DATE 2019
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F. V.Fernandez

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lunes, 17 de junio de 2019
Última actualización: 14.06.2019

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