Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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En el año 2020 se ha celebrado la sexta edición de los premios HiPEAC Tech Transfer Awards. Entre los ganadores se encuentra el desarrollo de una red neuronal profunda utilizada en una misión espacial y una estructura de bloqueo lógico escalable para la protección de la integridad del hardware. El alcance del trabajo ganador sirve como una demostración de cómo la investigación desarrollada en la red HiPEAC continúa resonando más allá del laboratorio.
22 Diciembre 2020
Publicado el libro 'Silicon Systems for Wireless LAN'. Entre los autores figuran el investigador del IMSE Gildas Léger (también editor) y el profesor de la Universidad de Sevilla Antonio J. Ginés Arteaga.
Diciembre 2020
♦ Premio a la mejor contribución al congreso DCIS 2020
Los investigadores del IMSE-CNM P. Sarazá-Canflanca, H. Carrasco-López, P. Brox, R. Castro-López, E. Roca and F.V. Fernández han sido galardonados con el premio a la mejor contribución al congreso DCIS 2020, con el trabajo titulado 'Improving the reliability of SRAM-based PUFs under varying conditions'.
19 Noviembre 2020
La investigadora del IMSE Teresa Serrano Gotarredona ha sido nombrada por el Consejo de Gobierno de la Junta de Andalucía nueva Directora General de Investigación y Transferencia del Conocimiento de la Consejería de Transformación Económica, Industria, Conocimiento y Universidades.
17 Noviembre 2020

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Últimas publicaciones
Editorial: A Year Ahead Full of New Initiatives  »
First of all, I hope that you, your families and all yours remain healthy and safe. The thoughts of the Editorial Board (EB) of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS (TCAS-II) and all the staff from IEEE are with those who are facing health problems and have suffered the consequences of the COVID-19 pandemic. The first year of my term as Editor-in-Chief (EiC) of IEEE TCAS-II has run under this terrible situation which has changed the lifestyle of all of us. We have seen how almost all social and professional events, including of course most IEEE conferences, have been either cancelled or running virtual, what has precluded us from enjoying together with our friends and colleagues as we had always done. The New Year 2021 comes full of hope for humankind with the development of several vaccines and more effective drugs to fight against the coronavirus SARS-Cov-2, and I am firmly convinced that sooner than later we will be able to recover our way of living.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 1, pp 4-4, 2021 IEEE
DOI: 10.1109/TCSII.2020.3041170    ISSN: 1549-7747    » doi
J.M. de la Rosa
An efficient transformer modeling approach for mm-wave circuit design  »
In this paper, a Gaussian-process surrogate modeling methodology is used to accurately and efficiently model transformers, which are still a bottleneck in radio-frequency and millimeter-wave circuit design. The proposed model is useful for a wide range of frequencies from DC up to the millimeter-wave range (over 100 GHz). The technique is statistically validated against full-wave electromagnetic simulations. The efficient model evaluation enables its exploitation in iterative user-driven design approaches, as well as automated design exploration involving thousands of simulations. As experimental results, the model is used in several scenarios, such as the design of an inter-stage amplifier operating at 60 GHz, where the model assisted in the simulation of the transformers and baluns used, and the design of individual transformers and a matching network.

Journal Paper - AEU - International Journal of Electronics and Communications, vol. 128, article 153496, 2021 ELSEVIER
DOI: 10.1016/j.aeue.2020.153496    ISSN: 1434-8411    » doi
F. Passos, E. Roca, J. Sieiro, R. Castro-Lopez and F.V. Fernandez
A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-based CT MASH ΣΔ Modulator  »
We present in this brief a novel multi-stage noise-shaping (MASH) 3-1 continuous-time (CT) delta-sigma modulator ( Σ δM ) with gated ring oscillator based quantizers (GROQs) in both stages of the cascade. The use of GROQs increases the linearity performance with respect to the conventional voltage controlled oscillator based quantizers (VCOQs) and allows a more robust extraction of the front-end stage quantization error in the time domain, thus making the proposed architecture more suitable to implement high-order expandable scaling-friendly MASH Σ δ Ms, in which the back-end stages are implemented by mostly-digital GRO-based time-to-digital converters (TDCs). The circuit has been fabricated in a 65-nm CMOS technology with 1-V supply voltage, and it operates at 640-MHz sampling frequency to digitize 10-MHz signals. To the best of the authors‚ knowledge, this is the first reported experimental validation of a GRO-based CT MASH Σ δM , featuring a 79.8-dB signal to noise ratio (SNR) at -2.2-dBFS, a 77.3-dB signal to (noise + distortion) ratio (SNDR) at -4-dBFS and a dynamic range (DR) of 81.7 dB, with a power consumption of 12-mW. These metrics demonstrate state-of-the-art performance with a DR-based Schreier FOM of 170.9 dB.

Conference - International Symposium on Integrated Circuits and Systems ISICAS 2020
M. Honarparvar, J.M. de la Rosa and M. Sawan
Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions based on the Matrix Exponential  »
This paper presents a new simulation method for fast evaluation of non-linear circuits. The proposed approach solves the non-linear ordinary differential equation (ODE) set of the system using a semi-analytical solution based on the matrix exponential. The method is fully general and suitable for different circuits, including switched-capacitor (SC) architectures, analog to digital converters (Pipeline, SAR, Sigma-Delta ADCs) or digital to analog converters. For illustration purpose in this paper, an analog signal processing front-end for discrete-time data acquisition system is considered as case study. The circuit comprises a Flip-Around Sample&Hold followed by a Programmable Gain Amplifier (PGA), based on a Correlated Double-Sampling amplifier, and a back-end ADC. The model includes non-linearity associated to switches, capacitive parasitics, finite nonlinear DC-gain and non-linear settling behavior including slew-rate. Comparison with traditional ODE numerical solvers shows a reduction of the computation time in almost two orders of magnitude with negligible difference in terms of accuracy.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
J.A. Serrano, A.J. Gines and E. Peralías
Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar  »
Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages-coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2020
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco

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