Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Ciclo de conferencias '¿Qué sabemos de...?'
Del electrón al chip.
Gloria Huertas Sánchez
25 Septiembre 2017
♦ Defensa de Tesis Doctoral
Hardware dedicado para sistemas empotrados de visión.
Elisa Calvo Gallego
18 de Septiembre de 2017
♦ Defensa de Tesis Doctoral.
Diseño Sistemático de Circuitos y Sistemas Analógicos y de Señal Mixta Reconfigurables.
Manuel Velasco Jiménez
15 Septiembre 2017
Nota de prensa. Un estudio Internacional experimental en el que ha participado Gustavo Liñán Cembrano, investigador del IMSE-CNM, confirma la disminución de los efectos de las perturbaciones como beneficio de la modularidad en la construcción de redes.   [+info]
14 Julio 2017

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Últimas publicaciones
Gaussian Pyramid: Comparative Analysis of Hardware Architectures  »
This paper addresses a comparison of architectures for the hardware implementation of Gaussian image pyramids. Main differences between architectural choices are in the sensor front-end. One side is for architectures consisting of a conventional sensor that delivers digital images and which is followed by digital processors. The other side is for architectures employing a non-conventional sensor with per-pixel embedded preprocessing structures for Gaussian spatial filtering. This later choice belongs to the general category of " artificial retina" sensors which have been for long claimed as potentially advantageous for enhancing throughput and reducing energy consumption of vision systems. These advantages are very important in the internet of things context, where imaging systems are constantly exchanging information. This paper attempts to quantify these potential advantages within a design space in which the degrees of freedom are the number and type of ADCs, single-slope, SAR, cyclic, Sigma Delta, and pipeline, and the number of digital processors. Results show that speed and energy advantages of preprocessing sensors are not granted by default and are only realized through proper architectural design. The methodology presented for the comparison between focal-plane and digital approaches is a useful tool for imager design, allowing for the assessment of focal-plane processing advantages.

Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 9, pp 2308-2321, 2017 IEEE
DOI: 10.1109/TCSI.2017.2709280    ISSN: 1549-8328    » doi
F.D.V.R. Oliveira, J.G.R.C. Gomes, J. Fernandez-Berni, R. Carmona-Galan, R. del Rio and A. Rodriguez-Vazquez
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs  »
This brief presents a digital calibration technique for compensating timing-skew errors between the sub-ADC and the MDAC in the first stage of sample-and-hold amplifier (SHA)-less pipeline ADCs. In the presence of clock-skew errors, sub-ADC comparators produce time-variant offsets depending on the input-signal slope at the sampling instants. These increase residue excursions at the MDAC output, potentially causing overranging and an increment in nonlinear errors. This paper derives close analytical expressions for these effects. The proposed method uses the overranging information to perform a low-cost estimation and correction of the skew error with the following features: 1) very fast convergence (in the order of 1-k input samples); 2) indirect evaluation of the skew error signal, without any previous knowledge of the input signal's frequency distribution; and 3) relatively simple digital logic--basically, two digital comparators and one small accumulator. The method was verified in behavioral and transistor-level simulations. As a demonstrator, its implementation in a 1.8-V 80-dB SNDR 100-Msps SHA-less pipeline ADC in a 0.18-μm CMOS process is shown.

Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, first online, 2017 IEEE
DOI: 10.1109/TVLSI.2017.2718625    ISSN: 1063-8210    » doi
A.J. Gines, E. Peralias and A. Rueda
Impact of the RT-level architecture on the power performance of tunnel transistor circuits  »
Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer-level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.

Journal Paper - International Journal of Circuit Theory and Applications, first online, 2017 JOHN WILEY & SONS
DOI: 10.1002/cta.2398    ISSN: 0098-9886    » doi
M.J. Avedillo and J. Núñez
Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications  »
RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this paper, we analyze the limitations of typical TFET rectifier topologies associated with the forward biasing of their intrinsic diode and show that this can occur at relatively weak input signals depending on the specific characteristic of the used tunnel device. We propose a simple modification in the implementation of the rectifiers to overcome this problem. The impact of our proposal is evaluated on the widely used gate cross-coupled topology. The proposed designs exhibit similar peak PCE and sensitivity but significantly improve PCE for larger input signal amplitude and larger input power.

Journal Paper - IEEE Journal of the Electron Devices Society, first online, 2017 IEEE
DOI: 10.1109/JEDS.2017.2737598    ISSN: 2168-6734    » doi
J. Nuñez and M.J. Avedillo
Multiradix Trivium Implementations for Low-Power IoT Hardware  »
The integration of lightweight symmetric encryption is becoming increasingly widespread in very low-power Internet of Things applications, with the rapid emergence of very low energy block and stream ciphers in portable and wireless systems. Trivium is one of the lightweight stream ciphers shortlisted for the hardware profile of the eSTREAM project. This paper describes low-power multiradix Trivium implementations based on the use of parallelization techniques to reduce dynamic power consumption. The low-power Trivium designs were implemented and characterized in TSMC 90 nm to compare area resources and power reduction. The implementation results show that our proposed designs offer dynamic power savings of 31%-45% with radix-1 and radix-2 when compared with the standard Trivium, and 15% with radix-8. There is no improvement, however, with radix-16.

Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, first online, 2017 IEEE
DOI: 10.1109/TVLSI.2017.2736063    ISSN: 1063-8210    » doi
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero

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