A dynamic vision sensor (DVS) is a new type of vision sensor in which each pixel acts as a motion sensor and generates highly time-accurate events when it detects movement in the scene. The high temporal precision of these types of vision sensors allows the extraction of different low-level temporal features, which is not possible when using a frame-based camera. Hierarchical vision-processing systems use low-level features to recognize a higher level of abstraction. One of the lowlevel features that can be extracted with DVS is the temporal frequency. This feature can be used along with other visual features for more accurate object recognition when the object has rotating parts, such as a quadcopter. This work is an extension of our previous work, wherein we proposed an algorithm to extract this temporal low-level feature by using a DVS. In this work, we proposed a digital circuit with a small footprint to extract the frequency of rotating objects in real time with very low latency. We have synthesized the digital circuit in Spartan-6 field-programmable gate array (FPGA) and also in UMC 180-nm technology to measure the performance, power consumption, and occupied area. MATLAB and Verilog codes for this work are available for academic purposes upon request.

Conference - IEEE International Conference on Intelligent Computer Communication and Processing ICCP 2018

In artificial intelligence (AI), proposing an efficient algorithm with an appropriate hardware implementation has always been a challenge because of the well-accepted fact that AI hardware implementations should ideally be comparable to biological systems in terms of hardware area. Active learning method (ALM) is a fuzzy learning algorithm inspired by human brain computations. Unlike traditional algorithms, which employ complicated computations, ALM tries to model human brain computations using qualitative and behavioral descriptions of the problem. The main computational engine in ALM is the ink drop spread (IDS) operator, but this operator imposes high memory requirements and computational costs, making the ALM algorithm and its hardware implementation unsuitable for some of the applications. This paper proposes an adaptive alternative method for implementing the IDS operator; a method which results in a marked reduction in the algorithm´s computational complexity and in the amount of memory required and hardware. To check its validity and performance, the method was used to carry out modeling and pattern classification tasks. This paper used challenging and real-world datasets and compared with well-known algorithms (adaptive neuro-fuzzy inference system and multi-layer perceptron) in software simulation and hardware implementation. Compared to traditional implementations of the ALM algorithm and other learning algorithms, the proposed FPGA implementation offers higher speed, less hardware, and improved performance, thus facilitating real-time application. Our ultimate goal in this paper was to present a hardware implementation with an on-chip training that allows it to adapt to its environment without dependency on the host system (on-chip learning).

Journal Paper - International Journal of Machine Learning and Cybernetics, first online, 2018 SPRINGER
DOI: 10.1007/s13042-018-0890-x    ISSN: 1868-8071    » doi

Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm².

Journal Paper - IEEE Journal of Solid-State Circuits, first online, 2018 IEEE
DOI: 10.1109/JSSC.2018.2881923    ISSN: 0018-9200    » doi

In this article, we present a review of the driving principles and parameters of a previously reported focal-plane tone-mapping operator. We then extend it in order to include color information processing. The signal processing operations required for handling color images are white balance and demosaicing. Neither white balance nor demosaicing are carried out in the focal plane, in order to avoid increasing circuit size and complexity. Since, in this case, white balance is carried out after tone mapping, multiplication of red and blue channels by constant gains may lead to wrong color results. An alternative approach is proposed, in which different gains are assigned for every red and blue pixel of the matrix. Because of the introduction of color, a modification in the original circuit is proposed, which affects the integration time of red and blue pixels. This modification leads to a reduction in the number of photodiodes required in the pixel array, and hence to a reduction of the sensing circuit area. The results produced by the operator are compared to those obtained from two other digital tone-mapping operators.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018

This demo shows a first prototype two-axis miniaturized spiking sun sensor. The device is composed of spiking pixels, and uses a novel Time-to-First-n-Spikes with time-out readout mode to reduce bandwidth consumption and post-processing computation. Due to on-chip processing, and compressing the angle information, the sensor produces much less data and is much faster than digital sensors. Its response latency is 88 µW, and average power consumption is 6.3 µW. An integrated circuit with core electronics was fabricated in the AMS 0.35 µm CMOS image sensor process, and was integrated inside a very small QFN64 package with micro-optics on top.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018