IMSE-CNM

Implementando conceptos innovadores en silicio

Áreas de Investigación

Analog Signal Processing
Analog Signal Processing

Digital Signal Processing & VLSI Systems
Digital Signal Processing & VLSI Systems

Brain-Inspired Neural Networks and Artificial Intelligence
Brain-Inspired Neural Networks and Artificial Intelligence

Sensory & Photonic Vision Systems
Sensory & Photonic Vision Systems

Nanoelectronics and Emerging Technologies
Nanoelectronics and Emerging Technologies

Biomedical and Bioinspired Circuits and Systems
Biomedical and Bioinspired Circuits and Systems

Integrated Circuits for Space Applications
Integrated Circuits for Space Applications

Hardware Security
Hardware Security

Noticias

Feria Ciencia 2026
El IMSE lleva la tecnología y la innovación a la Feria de la Ciencia

Un año más, el Instituto de Microelectrónica de Sevilla ha estado presente en la Feria de la Ciencia, que ya alcanza su 24ª edición.
14 Mayo 2026

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IMSE Feria Ciencia Europea
Esquivando láseres para entender la seguridad digital

A través de un laberinto láser y retos criptográficos, investigadores del centro acercaron conceptos clave de protección digital a cientos de estudiantes procedentes de toda Europa.
26 Marzo 2026

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IMSE Dia de las Matematicas 2026
Acercar las matemáticas a las aulas para despertar vocaciones científicas

Investigadores del IMSE llevan la divulgación científica a centros educativos con motivo del Día Internacional de las Matemáticas.
16 Marzo 2026

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IMSE Dia de la Mujer y la Niña en la Ciencia 2026
Inspirando a la próxima generación de científicas y científicos

Desde el IMSE llevamos a cabo varias actividades para poner en valor en papel de las investigadoras de nuestro centro.
2 Marzo 2026

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IMSE participará Science is Wonderful 2026
El IMSE representará al CSIC en la Feria Europea de la Ciencia "Science is Wonderful!" 2026

"Science is Wonderful!", la Feria Internacional de la Ciencia organizada por la Comisión Europea, se celebrará en Bruselas los próximos 18, 19 y 20 de marzo de 2026, y volverá a contar por tercer año consecutivo con la participación de un equipo de investigadores del Instituto de Microelectrónica de Sevilla (IMSE-CNM).
3 Noviembre 2025

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Premio TFM Pablo Navarro IMSE
El IMSE firma la excelencia en seguridad digital

El talento investigador del IMSE vuelve a destacar con el Premio "Leonardo Torres Quevedo" concedido a Pablo Navarro por su Trabajo de Fin de Máster que profundiza en la seguridad y eficiencia de algoritmos criptográficos.
31 Octubre 2025

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EVENTOS Y NOTICIAS ANTERIORES

Nueva Directora del IMSE-CNM

La investigadora del IMSE Teresa Serrano Gotarredona ha sido nombrada nueva Directora del Instituto de Microelectrónica de Sevilla.

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Formación en el IMSE

- Doctorado
- Máster
- Grados
- Trabajos Fin de Grado
- Prácticas en Empresa

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Publicaciones recientes

Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation
P. Ortega-Castro, E. Camacho-Ruiz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Journal Paper · IEEE Open Journal of the Solid-State Circuits Society (Early Access)
IEEE    ISSN: 2644-1349
resumen      doi      

In increasingly interconnected systems, security has become a critical concern. In this context, delay-based Physical Unclonable Functions (PUFs), such as Ring Oscillator (RO) PUFs, have emerged as key hardware security primitives by providing unique, unpredictable, and reliable responses, addressing security challenges related to key storage and device authentication. To ensure robustness, RO-PUF designs traditionally resort to analog-driven implementation flows, which suffer from high design overhead and limit scalability across technology nodes. We present a configurable RO-PUF design integrated following a standard-cell-based, fully digital semi-custom-design methodology, significantly reducing design effort while enabling portability across planar CMOS technologies. The proposed architecture integrates fully on-chip Helper Data Algorithm (HDA) combined with a lightweight Error Correction Code (ECC) to support key generation, obfuscation, and recovery. Furthermore, it was fabricated in TSMC 65 nm technology and extensively characterized across diverse operating conditions, including process, voltage, and temperature (PVT) variations, achieving state-of-the-art metrics.

Assessment of an FPGA Implementation of a Hybrid PUF Based on a Configurable Transient Effect Ring Oscillator and Ring Oscillator (TERORO-PUF)
A. Casado-Galán, J. Núñez, E. Tena-Sánchez, F.E. Potestad-Ordóñez and A.J. Acosta-Jiménez
Journal Paper · Electronics, vol. 15, no. 3, article 661, 2026
MDPI    ISSN: 2079-9292
resumen      doi      

In the current situation of the Internet of Things (IoT) with its billions of interconnected devices, security in this low-resource environment is paramount. A Physical Unclonable Function (PUF) is a very useful cryptographic primitive which allows us to extract unique information from a particular device in a non-reproducible way. This allows us to use a PUF in cryptography for authentication or secret-key generation. Ring Oscillators (ROs) and Transient Effect Ring Oscillators (TEROs) are oscillating structures used in both FPGAs and ASICs to build PUFs. In this paper we present an FPGA implementation of a PUF based on what we call the ’’TERORO’’ cell (TERO + RO), which is a hybrid structure that allows us to use the different functionalities of both RO and TERO in a single building block. We assess all the possible methods of extracting bits of information from the PUF based on TERORO cells. Finally, we tested the circuit and presented experimental results in terms of its uniqueness, uniformity, and reliability. In RO-counter mode, we obtain 49.74% uniqueness, 54.66% uniformity, and 97.81% reliability across devices, while TERO-based XOR mixing achieves 52.83% uniformity, 45.79% uniqueness, and 93.15% reliability. The FPGA footprint is 142 LUTs, 36 registers, and 82 slices.

Enhancing the performance of HfO2-based memristors with a thin Al2O3 layer: a comparative study
M. Shooshtari, T. Serrano Gotarredona and B. Linares-Barranco
Journal Paper · Journal of Physics D: Applied Physics, vol. 58, no. 45, 2025
IOP Science    
resumen      doi      

The resistive switching behavior of memristors is pivotal for advancing next-generation non-volatile memory and neuromorphic computing devices. In this study, we investigate the impact of incorporating a thin Al2O3 interfacial layer into HfO2-based memristors by fabricating and comparing two device architectures: W/HfO2/Ti/TiN and W/Al2O3/HfO2/Ti/TiN. The Al2O3 layer significantly influences device behavior by altering the electric field distribution and suppressing oxygen vacancy diffusion, leading to more confined and stable filament formation. While the dual-layer structure exhibits higher forming voltages due to increased dlectric thickness and the insulating properties of Al2O3, it also demonstrates improved switching uniformity, reduced resistance variability, and enhanced cycle-to-cycle endurance. Variability, quantified as resistance state variation over repeated cycles, was notably improved in the Al2O3-based device, with resistance fluctuations reduced by nearly 50% compared to the single-layer HfO2 device. These results highlight the role of interfacial engineering in improving memristor stability and reliability, offering valuable design strategies for future memory and neuromorphic computing systems.

A Side-Channel Protected and High-Performance Hardware Implementation for EdDSA25519
P. Navarro-Torrero, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · IEEE Access Vol 13
IEEE    ISSN: 2169-3536
resumen      doi      

This paper presents a high-performance and secure hardware implementation of the Edwards-Curve Digital Signature Algorithm (EdDSA25519). Using the fixed-base signed multi-comb and the k-ary algorithms for scalar multiplication, the proposed design achieves 307%, 253%, and 48% faster performance in key generation, signature generation, and signature verification, respectively, compared to the fastest previous hardware implementation in the state-of-the-art. When compared to the software-based OpenSSL implementation, our design demonstrates timing performance improvements ranging from 1000% to 2200%. Additionally, we integrate robust Side-Channel Attack (SCA) countermeasures and validate their effectiveness through Test Vector Leakage Assessment (TVLA). The results demonstrate increased resistance to Simple Power Analysis (SPA) and Differential Power Analysis (DPA), offering a hardware-based secure solution for modern cryptographic applications.

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Qué hacemos en el IMSE

El área de especialización del Instituto es el diseño de circuitos integrados analógicos y de señal mixta en tecnología CMOS, así como su uso en diferentes contextos de aplicación tales como dispositivos biomédicos, comunicaciones inalámbricas, conversión de datos, sensores de visión inteligentes, ciberseguridad, computación neuromórfica y tecnología espacial.

La plantilla del IMSE-CNM está formada por unas cien personas, entre personal científico y de apoyo, que participan en el avance del conocimiento, la generación de diseños de alto nivel científico-técnico y la transferencia de tecnología.

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Webs relacionadas con el IMSE

Máster en Microelectrónica. Diseño y Aplicaciones de Sistemas Micro/Nanométricos

Doctorado en Ciencias y Tecnologías Físicas

Doctorado de Ingeniería Informática

SIMSIDES: A Time-Domain Behavioral Simulator for Sigma-Delta Modulators in MATLAB/SIMULINK

SHORES: Software & Hardware Open Repository for Embedded Systems

Fuzzy Logic Design Tools

El IMSE en los medios
El IMSE en los medios

El Mundo de los Chips
El Mundo de los Chips

Catálogo de Servicios Científico-Técnicos
Catálogo de Servicios Científico-Técnicos

Empleo en el IMSE
Empleo en el IMSE
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