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Se buscan candidatos/as para un contrato de Titulado Superior en el área de Tecnología Electrónica y de Comunicaciones, asociado al Proyecto de Investigación n-PATETIC (Nuevos paradigmas para el test de circuitos integrados de señal mixta).  [+ info] »
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Se buscan candidatos/as para un contrato predoctoral para la formación de doctores en el área de Tecnología Electrónica y de Comunicaciones asociada al Proyecto de Investigación TOGETHER (Dispositivos, circuitos y arquitecturas fiables y de bajo consumo para IoT).  [+ info] »
♦ Oferta de empleo. Titulado Superior
Se buscan candidatos/as para un contrato de Titulado Superior en el área de Tecnología Electrónica y de Comunicaciones, asociado al Proyecto de Investigación MARAGDA (Aproximación multi-nivel al diseño orientado a la fiabilidad de circuitos integrados analógicos y digitales).  [+ info] »
♦ Visitas al IMSE
IES San Blas.
10 Febrero 2017
♦ Defensa de Tesis Doctoral
Diseño CMOS de Sistemas de Front-End para Instrumentación Ambiental en Marte.
Samuel Sordo Ibáñez
15 Diciembre 2016

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Últimas publicaciones
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs  »
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four MOSFET and FinFET transistors. The impact of logic depth, switching activity and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.

Journal Paper - IEEE Transactions on Nanotechnology, vol. 16, no, 1, pp 83-89, 2017 IEEE
DOI: 10.1109/TNANO.2016.2629264    ISSN: 1536-125X    » doi
J. Núñez and M.J. Avedillo
An automated design methodology of RF circuits by using Pareto-optimal fronts of EM-simulated inductors  »
A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a single-objective and a multi-objective optimization of a Low Noise Amplifier.

Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp 15-26, 2017 IEEE
DOI: 10.1109/TCAD.2016.2564362    ISSN: 0278-0070    » doi
R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, J. Sieiro, J.M. López-Villegas and N. Vidal
An inductor modeling and optimization toolbox for RF circuit design  »
This paper describes the SIDe-O toolbox and the support it can provide to the radio-frequency designer. SIDe-O is a computer-aided design toolbox developed for the design of integrated inductors based on surrogate modeling techniques and the usage of evolutionary optimization algorithms. The models used feature less than 1% error when compared to electromagnetic simulations while reducing the simulation time by several orders of magnitude. Furthermore, the tool allows the creation of S-parameter files that accurately describe the behavior of inductors for a given range of frequencies, which can later be used in SPICE-like simulations for circuit design in commercial environments. This toolbox provides a solution to the problem of accurately and efficiently optimizing inductors, which alleviates the bottleneck that these devices represent in the radio-frequency circuit design process.

Journal Paper - ntegration, the VLSI Journal, first online, 2016 ELSEVIER
DOI: 10.1016/j.vlsi.2017.01.009    ISSN: 0167-9260    » doi
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Brownian distance correlation-directed search: A fast feature selection technique for alternate test  »
Machine-learning indirect test relies on powerful statistical algorithms to build prediction models that relate cheap measurements to costly performance metrics. Though many works in the past have been focused on proposing different models or on ways to improve the reliability of the results, it appears that the main bottleneck of the approach is the definition of an information-rich input space. Finding the appropriate measurements that are both cheap and meaningful is a task that has not yet been automated. In this framework, feature selection is a necessary tool to explore possible candidates. In this paper a hybrid method is proposed that lay between filtering and wrapper-based methods, trying to strike the right balance between accuracy and speed for the particular case of Alternate Test.

Journal Paper - Integration, the VLSI Journal, vol. 55, pp 401-414, 2016 ELSEVIER
DOI: 10.1016/j.vlsi.2016.05.003    ISSN: 0167-9260    » doi
G. Leger and M.J. Barragan
Side-channel analysis of the modular inversion step in the RSA key generation algorithm  »
This paper studies the security of the RSA key generation algorithm with regard to side-channel analysis and presents a novel approach that targets the simple power analysis (SPA) vulnerabilities that may exist in an implementation of the binary extended Euclidean algorithm (BEEA). The SPA vulnerabilities described, together with the properties of the values processed by the BEEA in the context of RSA key generation, represent a serious threat for an implementation of this algorithm. It is shown that an adversary can disclose the private key employing only one power trace with a success rate of 100 % - an improvement on the 25% success rate achieved by the best side-channel analysis carried out on this algorithm. Two very different BEEA implementations are analyzed, showing how the algorithm's SPA leakages could be exploited. Also, two countermeasures are discussed that could be used to reduce those SPA leakages and prevent the recovery of the RSA private key.

Journal Paper - International Journal of Circuit Theory and Applications, first online, 2016 JOHN WILEY & SONS
DOI: 10.1002/cta.2283    ISSN: 0098-9886    » doi
A. Cabrera Aldaya, R. Cuiman Márquez, A.J. Cabrera Sarmiento and S. Sánchez-Solano

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