Encontrados resultados para:
Autor: Diego Vázquez García de la Vega
Año: Desde 2002
Artículos de revistas
Análisis de robustez ante variaciones de proceso en amplificadores CMOS integrados de bajo ruido
J.L. González Ríos, J.C. Cruz Hurtado, R.L. Moreno and D. Vázquez
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 37, no. 1, pp 1-8, 2016
resumen
En este artículo se presenta el análisis estadístico del comportamiento de diferentes amplificadores de bajo ruido (LNA) ante las variaciones de proceso presentes en una tecnología de fabricación de circuitos integrados CMOS, así como el impacto de las variaciones que ocurren en el LNA sobre el desempeño del receptor. Los LNA fueron diseñados utilizando una tecnología CMOS de 130 nm y 1.2 V de alimentación, siguiendo las especificaciones requeridas para receptores ZigBee® (estándar IEEE 802.15.4), en la banda de 2.4 GHz. Fueron estudiados circuitos con transistores de distintos valores de largo del canal y de corriente de polarización. De las simulaciones de Monte Carlo realizadas se obtuvo que la utilización de transistores de canal más largo y con mayor consumo de potencia disminuyen la dispersión de los parámetros de RF de los LNA, lo que aumenta el número de circuitos que cumplen con las especificaciones trazadas. Se observó que las variaciones de los parámetros de los amplificadores afectan en mayor medida el ruido del receptor que la linealidad, asociado a la caída de la ganancia del LNA por debajo del límite establecido. Los resultados presentados confirman la necesidad agregar el análisis de variabilidad a las metodologías de diseño convencionales de este tipo de circuito, con el objetivo de balancear el consumo de potencia y el costo de producción (asociado a la relación entre el número de circuitos útiles y el total fabricado).
A Proposal for Yield Improvement with Power Tradeoffs in CMOS LNAs
J.L. González, J.C. Cruz, R.L. Moreno and D. Vázquez
Journal Paper · IEEE Latin America Transactions, vol. 14, no. 1, pp. 13-19, 2016
resumen
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This paper investigates the capability of an architecture with digitally controllable gain and power consumption, for mitigating the effects of process variations on CMOS Low-Noise Amplifiers (LNAs). A 130-nm 1.2-V LNA with the proposed architecture is designed, based on the analysis of variability in LNAs with a traditional architecture under different biasing currents conditions, and the corresponding effects in the performance of a complete receiver context. Two different adjusting strategies are evaluated, which could be implemented with already reported Built-in Self-Test (BIST) circuits. Results show that the proposed architecture allows yield enhancement with low-power operation compared to traditional LNAs.
Energy-Aware Low-Power CMOS LNA with Process-Variations Management
J.L. González, R.L. Moreno, J.C. Cruz and D. Vázquez
Journal Paper · Active and Passive Electronic Components, vol. 2016, Article ID 8351406, 2016
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A reconfigurable low-noise amplifier (LNA) with digitally controllable gain and power consumption is presented. This architecture allows increasing power consumption only when required, that is, to improve LNA's radiofrequency performance at extreme communication-channel conditions and/or to counteract the effect of process, voltage, and temperature variations. The proposed design leads to significant power saving when a relaxed operation is acceptable. The LNA is implemented in a 130 nm 1.2 V CMOS technology for a 2.4 GHz IEEE-802.15.4 application. Simulated LNA performance (taking into account the worst cases under process variations) is comparable to recently published works.
Límites impuestos por los elementos pasivos en el diseño de amplificadores de bajo ruido en tecnología CMOS
J.L. González Ríos, R. Luiz Moreno and D. Vázquez
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 36, no. 3, pp 1-12, 2015
resumen
En este trabajo se analizan las restricciones impuestas por los límites tecnológicos de los elementos pasivos en el diseño de un amplificador de bajo ruido (LNA) integrado en tecnología CMOS, de configuración fuente común con degeneración inductiva. A partir del análisis del circuito se establecieron dependencias cualitativas entre los valores de los elementos pasivos y los objetivos de síntesis del LNA (ganancia, corriente de polarización y ancho de los transistores), que permiten prever cómo los parámetros constructivos limitan el desempeño funcional. Estas dependencias fueron comprobadas y enriquecidas a través de simulaciones, realizadas para una tecnología CMOS de 130 nm con 1.2 V de alimentación y una frecuencia de trabajo de 2.45 GHz. Para la topología estudiada, se muestra que la ganancia máxima, la corriente de polarización mínima (y, por tanto, el consumo de potencia mínimo) y las dimensiones de los transistores que pueden ser utilizados en el diseño están determinadas por los valores extremos de inductancia y capacidad disponibles en el proceso tecnológico. Los resultados obtenidos corroboran la necesidad de incluir toda la información tecnológica posible de los elementos pasivos dentro del flujo de diseño de circuitos integrados para aplicaciones de radiofrecuencia.
On-chip sinusoidal signal generation with harmonic cancelation for analog and mixed-signal BIST applications
M. Barragan, G. Leger, D. Vazquez and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 82, no. 1, pp 67-79, 2015
resumen
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This work presents a technique for the on-chip generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. The proposed generation technique consists of a modified low-order analog filter, that provides a sinusoidal output as response to a DC input, combined with a harmonic cancellation strategy to improve the linearity of the generated signal. The proposed generator has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. An integrated prototype designed in a 180 nm CMOS technology is presented in order to show the feasibility of the technique. Results obtained from the prototype show a THD around -80 dB.
Analog sinewave signal generators for mixed-signal built-in test applications
M.J. Barragán, D. Vázquez and A. Rueda
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 27, no. 3, pp 305-320 2011
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This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators-a continuous-time generator and a discrete-time one-have been integrated in a standard 0.35 mu m CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.
A BIST solution for frequency domain characterization of analog circuits
M.J. Barragán, D. Vázquez and A. Rueda
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 26, no. 4, pp 429-441, 2010
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This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1st-order I I" pound modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35 mu m-3.3 V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of 70 dB@62.5 kHz (1 MHz clock) has been demonstrated.
On-chip characterization of RF systems based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Journal Paper · Electronics Letters, vol. 46, no. 1, pp 36-37, 2010
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A simple on-chip procedure for testing embedded RF blocks is presented. It is based on the detection and spectral analysis of the two-tone response envelope of the device under test (DUT). A main difference with similar methods is its inherent simplicity, avoiding a preprocessing stage and resorting to simpler circuitry to process the envelope. As a consequence, the main nonlinearity specifications of the DUT can be easily estimated from the envelope signal without the need of expensive RF test equipment.
A low-cost digital frequency testing approach for mixed-signal devices using sigma delta modulation
G. Prenat, S. Mir, D. Vázquez and L. Rolindez
Journal Paper · Microelectronics Journal, vol. 36, no. 12, pp 1080-1090, 2005
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This paper presents a digital approach to frequency testing of Analogue and mixed-signal (AMS) circuits. This approach is aimed at facilitating low-cost test techniques for system-on-chip (SoC) devices, rendering the test of mixed-signal cores compatible with the use of a low-cost digital tester. Analogue test signal generation is performed on-chip by low pass filtering a sigma-delta (Sigma Delta) encoded bit-stream. Analogue harmonic test response analysis is also performed on-chip using square wave modulation and Sigma Delta modulation. Since both analogue signal generation and test response analysis are digitally programmable on-chip, compatibility with a low-cost digital tester is ensured. Optimisation of test signatures is discussed in detail as a trade-off between fault and yield coverage. A 0.18 mu m CMOS implementation of this BIST technique is presented, including some experimental results. (c) 2005 Elsevier Ltd. All rights reserved.
Sine-wave signal characterization using square-wave and Sigma Delta-modulation: Application to mixed-signal BIST
D. Vázquez, G. Huertas, A. Luque, M.J. Barragán, G. Léger, A. Rueda and J.L. Huertas
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 21, no. 3, pp 221-232, 2005
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This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. It is based on a double-modulation, square-wave and sigma-delta, together with a simple Digital Processing Algorithm. It leads to an efficient and robust approach very suitable for BIST applications. In this line, some considerations for on-chip implementation are addressed together with simulation results that validate the feasibility of the proposed approach.
A switched opamp-based bandpass filter: Design and implementation in a 0.35 μm CMOS technology
L. Quintanilla, J. Arias, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 34, no. 3, pp 201-209, 2003
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A fully differential SC bandpass filter (central frequency, 58 kHz; Q = 15; and voltage gain, 8) based on the switched-opamp approach is designed and implemented in this work. The filter operates from a single 1 V supply voltage and is realized in a 0.35 mum CMOS technology. It has been characterized with a sampling frequency of 1 MHz and its power consumption is about 230 muW. As a main internal filter component, an appropiate switched opamp was also designed. Its common-mode feedback circuit was implemented by using an error amplifier and sampling of the output common-mode voltage is carried out by applying a DC offset to level shift the common-mode sample. It provides an accurate common-mode output for a wide temperature and supply voltage ranges.
Oscillation-based test in oversampled ΣΔ modulators modulators
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · Microelectronics Journal, vol. 33, no. 10, pp 799-806, 2002
resumen
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This paper discusses a way of applying the oscillation-based test (OBT)/oscillation-based built-in-self test concept to oversampled ΣΔ modulators, exploiting previous experience coined through the implementation of OBT in SC integrated filters. Analytical and simulation results demonstrate that it is always feasible to find out an OBT configuration for a typical discrete-time second-order modulator structure without adding a substantial extra circuitry, but only resorting to local feedback loops. A feedback strategy can be chosen providing enough freedom to force oscillations, which can be worthwhile for testing purposes. The selected oscillation parameters allow us to establish criteria for a high fault coverage.
On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits
D. Vázquez, G. Huertas, G. Leger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 201-211, 2002
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This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.
Practical oscillation-based test of integrated filters
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · IEEE Design & Test of Computers, vol. 19, no. 6, pp 64-72, 2002
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Oscillation-based test techniques show promise in detecting faults in mixed-signal circuits and require little modification to the circuit under test. Comparing both the oscillation's amplitude and frequency yields acceptable test quality.
Testing mixed-signal cores: A practical oscillation-based test in an analog macrocell
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · IEEE Design & Test of Computers, vol. 19, no. 6, pp 73-82, 2002
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A formal set of design decisions can aid in using oscillation-based test for analog subsystems in SoCs. The goal is to offer designers testing options that don't have significant area overhead, performance degradation, or test time.
A simple and secure start-up circuitry for oscillation-based-test application
D. Vázquez, G. Huertas, A. Rueda and J.L. Huertas
Journal Paper · Analog Integrated Circuits and Signal Processing, vol 32, no. 2, pp 187-190, 2002
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A simple start-up strategy specially suitable for the oscillation-based-test application of opamp-based circuits is presented. The proposed approach not only ensures that the oscillator will start to run (safe start-up) but also the steady-state (SS) can be reached very fast (short transient-time).
Congresos
INTA′s Mars miniature sensors: synergies for Ice Giants exploration
V. Apéstigue, I. Arruego, D. Toledo, J. Martínez-Oter, M. González-Guerrero, J. Rivas, J.R. de Mingo, J. Manzano, F. Serrano, E. García-Menéndez, A. Martín-Ortega, N.S. Montalbo, J. Núñez, L. Gómez, M. Yela, S. Espejo, J. Ceballos and D. Vázquez
Conference · Ice Giants Systems 2020 (Royal Society)
resumen
INTA′s Space Sensors Engineering Area (AISE) has been involved in Martian exploration during the last decade, developing four different radiometers, one magnetometer, one nephelometer (in cooperation with INAF, Italy) and one dust sensor (together with University Carlos III, Spain) for different missions (MetNet penetrator, Schiparelli Lander, Mars 2020 Rover and ExoMars 2020 Surface Platform).
That is the result of a long-term strategy established ten years ago, named InMARS, devoted to the development of high performance, low power, miniature sensors capable of operating in the extreme Martian atmospheric conditions. Within this program we have developed an intensive selection, qualification and screening activity (CERES-Compact Electronic Resources for the Exploration of Space) that allowed us to acquire key enabling technologies, components (including ASICs), materials and procedures.
Taking advantage of the experience and heritage accumulated during this decade, we propose an early concept of a lightweight radiometer for future probes to Ice Giants or other moons with rich atmospheres for the study of the suspended aerosols scattering properties, the particles number density, constraining the aerosol shape, size and opacity. The limited resources that our technology demands from the platform allow it to be used as a complement to other atmospheric instrumentation included in future missions.
InMARS: a comprehensive program for the development of compact atmospheric probes for Mars
I. Arruego, V. Apéstigue, J. Martínez, J.J. Jiménez, A. Martín-Ortega, J.R. de Mingo, M. González-Guerrero, J. Azcue, N. Andrés, F.J. Álvarez, J. Rivas, J. Manzano, F. Serrano, I. Martín, A. Gonzalo, H. Guerrero, S. Espejo, J. Ceballos, A. Ragel, D. Vázquez, F. López, A.J. de Castro and F. Cortés
Conference · International Planetary Probes Workshop IPPW 2018
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The Space Sensors Engineering Area of INTA (the National Institute of Aerospace Technology, Spain) maintains a continuous activity aimed at the development of different resources and enabling capabilities, to allow the construction of compact instruments for atmospheric science on Mars and, in the long term, complete miniature atmospheric probes that could be used to deploy networks of meteorological stations on the red planet. InMARS (Instrumentation for Martian Atmospheric Research on Surface) program is part of this strategy. Under this program, we are presently developing one instrument for the JPL/NASA Mars 2020 Rover, two different sensors for the METEO package on board the ESA/Roscosmos ExoMars 2020 surface Platform (one of them led by a partner team from the Carlos III University, Madrid), and another instrument for the Dust Complex on board the same lander. We also developed a radiometer for the DREAMS payload on board the ill-fated Schiaparelli Descent Module of ExoMars 2016. This program is complemented by another initiative we named CERES (Compact Electronic Resources for the Exploration of Space), devoted to develop horizontal capabilities for the aforementioned purpose, and also supported by our own inorbit test-beds (INTA ′s Small Satellites Program). Amongst them, we include the development of Radiation-Hardened By design (RHBD) mixed-signal ASICs developed by another partner, the Institute for Microelectronics in Seville (IMSE).
InMARS: a comprehensive program for the development of key-technologies for miniature Martian probes
I. Arruego, V. Apéstigue, J. Martínez, J.J. Jiménez, A. Martín-Ortega, J.R. de Mingo, M. González-Guerrero, J. Azcue, N. Andrés, F.J. Álvarez, J. Rivas, J. Manzano, F. Serrano, I. Martín, A. Gonzalo, H. Guerrero, S. Espejo, J. Ceballos, A. Ragel, D. Vázquez, F. López, A.J. de Castro and F. Cortés
Conference · International Planetary Probes Workshop IPPW 2018
resumen
1.- The need for miniaturization: Synergy between Planetary Exploration & Small Satellites
2.- Starting from the basic building blocks
3.- Gaining In-Orbit Experience
4.- Going to Mars - Scientific instruments
5.- Future? - Synergies between our 3 present lines of work
SIS20: A CMOS ASIC for Solar Irradiance Sensors in Mars Surface
D. Vázquez, J. Ceballos and S. Espejo
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2018
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This paper reports the design and characterization of the ASIC SIS20, planned for an instrument aimed to
measure Solar Irradiance on the surface of Mars. It has been designed using the AMS0.35u CMOS technology
and with the rad-hard digital library developed at IMSE (Spain). The ASIC is intended for flying with the
ExoMars2020 mission.
Analysis of process variations' impact on a 2.4 GHz 90 nm CMOS LNA
J. Gonzalez, J. Cruz, D. Vazquez and A. Rueda
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2013
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This work presents the analysis of a 90nm CMOS LNA under process variations. The main parameters charactering the performance of this kind of devices are analyzed. It shows how the performance degradation is mainly derived from the resonant frequency shifting due to the output matching passive network. A way to partially compensate the degradation is presented. Preliminary results are shown.
Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique
M.J. Barragan, G. Leger, D. Vazquez and A. Rueda
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2013
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This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. The proposed generation technique is based on a modified analog filter, that provides a sinusoidal output as the response to a DC input, combined with a harmonic cancellation technique. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. Simulation results are provided in order to validate the proposed generation technique.
A 3.6mW @ 1.2V high linear 8th-order CMOS complex filter for IEEE 802.15.4 standard
A. Villegas, D. Vázquez, E. Peralías and A. Rueda
Conference · European Solid-State Circuits Conference ESSCIRC 2011
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This paper presents a fully differential 1.2V 8th-order inverter-based gm-C complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm CMOS technology. Tuning is carried out through voltage controlled capacitors instead of transconductors, resulting in a significant improvement in terms of linearity. The filter presents attractive attributes in terms of power, IRR, SFDR, noise and selectivity, demonstrated by experimental measurements from a fabricated prototype. © 2011 IEEE.
2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS
R. Fiorelli, A. Villegas, E. Peralías, D. Vázquez and A. Rueda
Conference · European Conference on Circuit Theory and Design ECCTD 2011
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A 2.4-GHz CMOS single ended-input differential-output front-end built with a common source low noise amplifier (CS-LNA) and a switched transconductor mixer (SW-MIX) is presented. The circuit is designed and optimized to work in a ZigBee receiver. Since this is a low power consumption standard, a single-ended LNA is preferred over a fully-differential topology because it leads to lower cost in area and power consumption. Also, moderate and weak inversions regions were selected for the operation of the principal transistors. The front-end prototype has been implemented in a 90 nm RF process and occupies a chip area of 0.74 mm2 including on-chip inductors. Very competitive results are observed: a maximum conversion gain (CG) of 30 dB, a DSB noise figure of 7.5 dB, a maximum IIP3 of -12.8 dBm and IIP2 of 14.4 dBm while it consumes 4.7 mW from a 1.2 V supply. © 2011 IEEE.
A 1.2V CMOS-90nm gm-c complex filter with frequency tuning for wireless network applicatons
A. Villegas, D. Vázquez and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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Abstract not available
1.2V, 1.96mw At 2.4 GHz CMOS-90nm Switched-Transconductor Mixer
A. Villegas, D. Vázquez and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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Abstract not available
Low-cost signature test of RF blocks based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE European Test Symposium ETS 2010
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This paper presents a novel and low-cost methodology that can be used for testing RP blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach. © 2010 IEEE.
Guidelines for the efficient design of sinewave generators for analog/mixed-signal BIST
M.J. Barragán, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE International Mixed-Signals, Sensors and Systems Test Workshop IMS3TW 2010
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This paper presents a design methodology for the implementation of efficient and accurate sinewave generators suitable for analog and mixed-signal BIST applications. The design guidelines are based on an analytical discussion that contemplates the main non-idealities of the generator. A full design example is presented to illustrate the proposed methodology. ©2010 IEEE.
A low power low voltage mixer for 2.4 GHz applications in CMOS-90nm technology
A. Villegas, D. Vázquez and A. Rueda
Conference · IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
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This paper presents the design of a fully differential double balanced switched transconductor mixer for ZigBee applications in the 2.4GHz band. It provides programmable conversion gain by using an active load stage. The design includes RF and LO input matching networks. It has been implemented in a 90nm 1P9M CMOS process. Post-layout simulations show conversion gains of 12dB/20dB, NF of 18.9dB/18.1dB and power consumption of 4.1mW/4.4mW at high and low gain mode respectively from a 1.2V power supply. It also offers very good linearity performance. © 2010 IEEE.
Practical test cores for the on-chip generation and evaluation of analog test signals: Application to a network/spectrum analyzer for analog BIST
M.J. Barragán, D. Vázquez and A. Rueda
Conference · IEEE PhD. Research in Microelectronics and Electronics PRIME 2009
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This paper presents practical implementations of test cores for analog and mixed-signal BIST. A sinewave generator for test stimulus generation, and a peRíodical signal characterization system for response evaluation are discussed. Integrated prototypes and experimental results are provided, and a prototype of a network/spectrum analyzer featuring both test cores has been developed and tested in the lab.
Efficient functional built-In test for RF systems using two-tone response envelope analysis
M.J. Barragán, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE AFRICON 2009
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This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.
A BIST solution for the functional characterization of RF systems based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE Asian Test Symposium ATS 2009
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This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally practical simulation examples show the feasibility of the approach.
A 2.5MHz bandpass active complex filter with 2.4MHz bandwidth for wireless communications
A. Villegas, R. Bianca, A. Ginés, R. Doldán, M.A. Jalón, A.J. Acosta, E. Peralías, D. Vázquez and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2008
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This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The filter compliants with the requirements of the IEEE802.15.4 standard. Simulation results including mismatching and process variations over the extracted view of the circuit are shown. The filter has a nominal gain of 12dB, good selectivity (20dB@2MHz offset), high image rejection (51dB nominal) and low power consumption (3.6mA @2.5V).
A 2.4 GHz LNA in a 90-nm CMOS technology designed with ACM model
R. Fiorelli, F. Silveira, E. Peralías, D. Vazquez, A. Rueda and J.L Huertas
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2008
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As part of a Low-IF ZigBee receiver, a 2.4GHz differential common source low noise amplifier, implemented in a 90nm mixed/RF 7M CMOS process and designed in moderate inversion, is presented in this work. Design methodology and simulation results from Spectre-RF simulator are presented. With 2.5V supply voltage, the LNA achieves a noise figure of 2.5dB, an IIP3 of 1dB and gain higher than 10dB, with a current consumption of 12mA. The LNA area without pads is 720m x 710m. Copyright 2008 ACM.
A 1.2V 5.14 mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4 GHz ZigBee applications
A.J. Ginés, R. Doldán, A. Villegas, A.J. Acosta, M.A Jalón, D. Vázquez, A. Rueda and E. Peralías
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
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A low-cost 1.2V 5.14mW phase-lock loop (PLL) quadrature frequency synthesizer compliant with the 2.4GHz ZigBee standard (IEEE 802.15.4) has been implemented in 90nm CNIOS technology. In-phase and quadrature (I/Q) components exhibit a phase noise of-105.9dBc/Hz at 1MHz offset from the carrier. The PLL die area including decoupling capacitors and testing buffers is 209x422 mu m(2).
Practical implementation of a network analyzer for analog BIST applications
M.J. Barragán, D. Vázquez and A. Rueda
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2008
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This paper presents a practical implementation of a network analyzer for analog BIST applications. The network analyzer consists of a sinewave generator and a sinewave evaluator based on switch-capacitor techniques. Both the generator and the evaluator have been integrated in a 0.35 mu m CMOS technology. The functionality of the system has been proved in the lab. For this purpose, a demonstrator board has been developed including the proposed network analyzer and a filter as DUT Measurements in the lab demonstrate a dynamic range of 70dB in the frequency range up to 20kHz.
On-chip analog sinewave generator with reduced circuitry resources
M.J. Barragán, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2006
resumen
This paper proposes an analog sinewave signal generator with minimal circuitry resources. It is based on a linear time variant filter that gives a high quality sine signal in response to a DC input. The proposed architecture has the attributes of digital programming and control capability, robustness and reduced area overhead, what make it suitable for BIST applications. Experimental results from a practical design demonstrate the feasibility of the approach.
A sinewave analyzer for mixed-signal BIST applications in a 0.35 mu m technology
M.J. Barragán, D. Vázquez and A. Rueda
Conference · IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems DDECS 2006
resumen
This paper presents an integrated prototype of a mixed-signal sinewave analyzer. It extracts, in the digital domain, the DC level and the amplitude of the harmonics of a distorted analog sinewave signal. It Is based on a double modulation, squarewave and sigma-delta, together with a simple digital processing algorithm. The presented prototype has been integrated In a 0.35 pm technology. It is intended for the characterization of sinewave signals In the range of audio. Experimental measurements in the lab verify the feasibility of the approach and the functionality of the prototype.
Test of switched-capacitor ladder filters using OBT
E. Romero, G. Peretti, G. Huertas and D. Vázquez
Conference · International Mixed-Signals Testing Workshop IMSTW 2004
resumen
In this paper, a way to test switched-capacitors ladder filters by means of Oscillation-Based Test (OBT) methodology is proposed. Third-order low-pass Butterworth and Elliptic filters are considered in order to prove the feasibility of the proposed approach. A topology with a non-linear element in an additional feedback loop is employed for converting the Circuit Under Test (CUT) into an oscillator. The idea is inspired in some author's previous works (G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Oscillation-based Test Experiments in Filters: a DTMF example, in: Proceedings of the International Mixed-Signal Testing Workshop (IMSTW'99), British Columbia, Canada, 1999, pp. 249-254; G. Huertas, D. Vázquez, E. Peralías, A. Rueda, J.L. Huertas, Oscillation-based test in oversampling A/D converters, Microelectronic Journal 33(10) (2002) 799-806; G. Huertas, D. Vázquez, E. Peralías, A. Rueda. J.L. Huertas, Oscillation-based test in bandpass oversampled A/D converters, in: Proceedings of the International Mixed-Signal Test Workshop, June 2002, Montreaux (Switzerland), pp. 39-48; G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Practical oscillation-based test of integrated filters, IEEE Design and Test of Computers 19(6) (2002) 64-72; G. Huertas, D. Vázquez, E. Peralías, A. Rueda, J.L. Huertas, Testing mixed-signal cores: practical oscillation-based test in an analog macrocell, IEEE Design and Test of Computers 19(6) (2002) 73-82). Two methods are used, the describing function approach for the treatment of the non linearity and the root-locus method for analysing the circuit and predicting the oscillation frequency and the oscillation amplitude. In order to establish the accuracy of these predictions, the oscillators have been implemented in SWITCAP (K. Suyama, S.C. Fang, Users' Manual for SWITCAP2 Version 1.1, Columbia University, New York, 1992). Results of a catastrophic fault injection in switches and capacitors of the filter structure are reported. A specification-driven fault list for capacitors is also defined based on the sensitivity analysis. The ability of OBT for detecting this kind of faults is presented. (c) 2005 Elsevier Ltd. All rights reserved.
Method for parameter extraction of analog sine-wave signals for mixed-signal built-in-self-test applications
D. Vázquez, G. Léger, G. Huertas, A. Rueda and J.L. Huertas
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen
This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. The required circuitry for on-chip implementation is very simple and robust, which makes the present approach very suitable for BIST applications. Solutions in this sense are addressed together with simulation results that validate the feasibility of the proposed approach.
A LP-LV high performance monolitic DTMF receiver with on-chip test facilities
D. Vázquez, G. Huertas, M.J. Avedillo, J.M. Quintana, A. Rueda and J.L. Huertas
Conference · Conference on VLSI Circuits and Systems 2003
resumen
This paper presents a mixed-signal DTMF receiver implemented in a double-poly double-metal 0.6um technology able to operate in the range of 2.7V-5V of voltage supply with a low current consumption (<1mA). An smart digital detector and decoder algorithm provides a very good speech immunity. On-chip test facilities for the analog part have.. been incorporated into the chip. A modified opamp (called sw-opamp) has been used to provide external accessing to inputs and outputs of the main analog blocks for off-line testing purposes. The so-called Oscillation-Based-Test (OBT) has also been integrated to perform a structural testing of the analog part. The additional cost of such on-chip test facilities is very small: just one extra pin and an area overhead of around 7%. Experimental results demonstrate the good performance of the design and the feasibility of the testing approaches.
Oscillation-based test in bandpass oversampled A/D converters
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE International Mixed-Signal Testing Workshop IMSTW 2003
resumen
This paper extends a study performed by the authors in Previous papers dealing with the OBT approach applied to low-pass modulators 'Microelectron. J. 33/10 (2002) 799', showing herein the specific features associated to the bandpass case. A practical feedback strategy will be proposed in order to built an effective oscillator, which can be valuable for testing purposes. Critical points of the proposed OBT solution will be considered in order to establish useful guidelines to apply this test approach to generic bandpass SigmaDelta modulators. (C) 2003 Elsevier Ltd. All rights reserved.
Practical solutions for the application of the oscillation-based-test in analog integrated circuits
D. Vázquez, G. Huertas, G. Léger, A. Rueda and J.L. Huertas
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
This paper presents practical solutions for solving the problems arising when applying Oscillation-Based-Test. It is devoted to discuss a practical on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.
Practical oscillation-based test in analog integrated filters: Experimental results
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE International Workshop on Electronic Design, Test and Applications DELTA 2002
resumen
This paper presents experimental results corresponding to the use of Oscillation-based Test (OBT) when applied to a switched-capacitor integrated filter. A universal biquad is used as an example to demonstrate the feasibility of the OBT technique.
Practical solutions for the application of the oscillation-based-test: Start-up and on-chip evaluation
D. Vázquez, G. Huertas, G. Léger, A. Rueda and J.L. Huertas
Conference · IEEE VLSI Test Symposium VTS 2002
resumen
This paper presents practical solutions for two of the main topics arising when applying Oscillation-Based-Test: the start-up of the configured oscillator and the on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.
Libros
Oscillation-Based-Test in Mixed-Signal Circuits
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Book · FRET, vol. 36, 452 p, 2006
resumen
link
Oscillation-Based Test in Mixed-Signal Circuits presents the development and experimental validation of the structural test strategy called Oscillation-Based Test - OBT in short. The results here presented allow to assert, not only from a theoretical point of view, but also based on a wide experimental support, that OBT is an efficient defect-oriented test solution, complementing the existing functional test techniques for mixed-signal circuits.
Capítulos de libros
Design of an energy efficient ZigBee transceiver
A. Ginés, R. Fiorelli, A. Villegas, R. Doldán, M. Barragán, D. Vázquez, A. Rueda and E. Peralías
Book Chapter · Mixed-Signal Circuits, pp 171-203, 2018
resumen
doi
This chapter tries to summarize our experience in the development of the analog front-end part of 2.4 GHz ZigBee transceivers with the main objective of optimizing power consumption during normal operation in both reception and transmission modes. Other interesting design aspects, such as optimizing the transceiver protocol, the design of the digital subsystems, or managing the sleep modes, have not been included due to space limitation. To gather together the presented design ideas, the chapter concludes in Section 7.5 with an example of a complementary metal-oxide semiconductor (CMOS) integrated transceiver analog front-end. The competitive experimental performances for this integration endorse the employed design flow, procedures, and analysis.
Oscillation-based test strategies
G. Huertas-Sánchez, G. Leger, D. Vázquez, A. Rueda and J.L. Huertas
Book Chapter · Test and Design-For-Testability in Mixed-Signal Integrated Circuits, pp 259-298, 2004
resumen
doi
This chapter aims to present a structural test methodology using the so-called OBT technique. The conceptual bases of the OBT approach are presented as well as many practical details on its application to practical integrated circuits.
DFT and BIST techniques for embedded analog integrated filters
D. Vázquez
Book Chapter · Test and Design-for-Testability in Mixed-Signal Integrated Circuits, pp 215-258, 2004
resumen
doi
This chapter focuses on both Design-for-Test and BIST approaches for analog circuits testing, but with special emphasis in the case of embedded Analog Integrated filters.
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