Encontrados resultados para:
Autor: Juan Núñez Martínez
Año: Desde 2002
Artículos de revistas
A Review of Ising Machines Implemented in Conventional and Emerging Technologies
T. Zhang, Q. Tao, B. Liu, A. Grimaldi, E. Raimondo, M. Jiménez, M.J. Avedillo, J. Núñez, B. Linares-Barranco, T. Serrano-Gotarredona, G. Finocchio and Jie Han
Journal Paper · IEEE Transactions on Nanotechnology (Early Access), 2024
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Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and pase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOSspintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
A CMOS-compatible oscillation-based VO2 Ising machine solver
O. Maher, M. Jiménez, C. Delacour, N. Harnack, J. Núñez, M.J. Avedillo, B. Linares-Barranco, A. Todri-Sanial, G. Indiveri and S. Karg
Journal Paper · Nature Communications vol. 15, article 3334, 2024
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Phase-encoded oscillating neural networks offer compelling advantages over metal-oxide-semiconductor-based technology for tackling complex optimization problems, with promising potential for ultralow power consumption and exceptionally rapid computational performance. In this work, we investigate the ability of these networks to solve optimization problems belonging to the nondeterministic polynomial time complexity class using nanoscale vanadium-dioxide-based oscillators integrated onto a Silicon platform. Specifically, we demonstrate how the dynamic behavior of coupled vanadium dioxide devices can effectively solve combinatorial optimization problems, including Graph Coloring, Max-cut, and Max-3SAT problems. The electrical mappings of these problems are derived from the equivalent Ising Hamiltonian formulation to design circuits with up to nine crossbar vanadium dioxide oscillators. Using sub-harmonic injection locking techniques, we binarize the solution space provided by the oscillators and demonstrate that graphs with high connection density (μ > 0.4) converge more easily towards the optimal solution due to the small spectral radius of the problema’s equivalent adjacency matrix. Our findings indicate that these systems achieve stability within 25 oscillation cycles and exhibit power efficiency and potential for scaling that surpasses available commercial options and other technologies under study. These results pave the way for accelerated parallel computing enabled by large-scale networks of interconnected oscillators.
Experimental Demonstration of Coupled Differential Oscillator Networks for Versatile Applications
M. Jiménez, J. Núñez, J. Shamsi, B. Linares-Barranco and M.J. Avedillo
Journal Paper · Frontiers in Neuroscience, Neuromorphic Engineering, vol. 17, 2023
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Oscillatory Neural Networks (ONNs) exhibit a high potential for energy-efficient computing. In ONNs, neurons are implemented with oscillators and synapses with resistive and/or capacitive coupling between pairs of oscillators. Computing is carried out on the basis of the rich, complex, nonlinear synchronization dynamics of a system of coupled oscillators. The exploited synchronization phenomena in ONNs are an example of fully parallel collective computing.A fast system´s convergence to stable states, which correspond to the desired processed information, enables an energy-efficient solution if small area and low-power oscillators are used, specifically, when they are built on the basis of the hysteresis exhibited by phase-transition materials such as VO2. In recent years, there have been numerous studies on ONNs using VO2. Most of them report simulation results. Although in some cases experimental results are also shown, they don´t implement the design techniques that other works on electrical simulations report that allow to improve the behavior of the ONNs.Experimental validation of these approaches is necessary. Therefore, in this work, we describe an ONN realized in a commercial CMOS technology in which the oscillators are built using a circuit that we have developed to emulate the VO2 device. The purpose is to be able to study in depth the synchronization dynamics of relaxation oscillators similar to those that can be performed with VO2 devices. The fabricated circuit is very flexible. It allows programming the synapses to implement different ONNs, calibrating the frequency of the oscillators or controlling their initialization. It uses differential oscillators and resistive synapses equivalent to the use of memristors. In this article, the designed and fabricated circuit is described in detail and experimental results are shown. Specifically, its satisfactory operation as an associative memory is demonstrated. The experiments carried out allow us to conclude that the ONN must be operated according to the type of computational task to be solved, and guidelines are extracted in this regard.
Learning Algorithms for Oscillatory Neural Networks as Associative Memory for Pattern Recognition
M. Jiménez, M.J. Avedillo, B. Linares-Barranco and J. Núñez
Journal Paper · Frontiers in Neuroscience, Neuromorphic Engineering, vol. 17, 2023
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Alternative paradigms to the von Neumann computing scheme are currently arousing huge interest. Oscillatory neural networks (ONNs) using emerging phase-change materials like VO2 constitute an energy-efficient, massively parallel, brain-inspired, in-memory computing approach. The encoding of information in the phase pattern of frequency-locked, weakly coupled oscillators makes it possible to exploit their rich nonlinear dynamics and their synchronization phenomena for computing. A single fully connected ONN layer can implement an auto-associative memory comparable to that of a Hopfield network, hence Hebbian learning rule is the most widely adopted method for configuring ONNs for such applications, despite its well-known limitations. An extensive amount of literature is available about learning in Hopfield networks, with information regarding many different learning algorithms that perform better than the Hebbian rule. However, not all of these algorithms are useful for ONN training due to the constraints imposed by their physical implementation. This paper evaluates different learning methods with respect to their suitability for ONNs. It proposes a new approach, which is compared against previous works. The proposed method has been shown to produce competitive results in terms of pattern recognition accuracy with reduced precision in synaptic weights, and to be suitable for online learning.
Operating Coupled VO2-based Oscillators for Solving Ising Models
M.J. Avedillo, M. Jiménez, C. Delacour, A. Todri-Sanial, B. Linares-Barranco and J. Núñez
Journal Paper · IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023
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Coupled nano-oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. The potential of phase transition devices for such dynamical systems has recently been recognized. This paper investigates the implementation of coupled VO2-based oscillator networks to solve combinatorial optimization problems. The target problem is mapped to an Ising model, which is solved by the synchronization dynamics of the system. Different factors that impact the probability of the system reaching the ground state of the Ising Hamiltonian and, therefore, the optimum solution to the corresponding optimization problem, are analyzed. The simulation-based analysis has led to the proposal of a novel Second-Harmonic Injection Locking (SHIL) schedule. Its main feature is that SHIL signal amplitude is repeatedly smoothly increased and decreased. Reducing SHIL strength is the mechanism that enables escaping from local minimum energy states. Our experiments show better results in terms of success probability than previously reported approaches. An experimental Oscillatory Ising Machine (OIM) has been built to validate our proposal.
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles using TFETs
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A.J. Acosta
Journal Paper · IEEE Embedded Systems Letters, vol. 14, no. 2, pp 99-102, 2021
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The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. The paper deals with the optimized design of DPA-resilient hiding-based techniques, using Tunnel Field-Effect Transistors (TFETs). Specifically, proposed TFET implementations of Dual-Precharge-Logic primitives optimizing their computation tree in three different ways, are applied to the design of PRIDE Sbox-4, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals have shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction (x25), compared to their CMOS-based counterparts in 65nm, which is a significant advance in the development of secure circuits with TFETs.
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase
A. Todri-Sanial, S. Carapezzi, C. Delacour, M. Abernot, T. Gil, Elisabetta Corti, S.F. Karg, J. Nüñez, M. Jiménez, M.J. Avedillo and B. Linares-Barranco
Journal Paper · IEEE Transactions on Neural Networks and Learning Systems, vol. 33, no. 5, pp 1996-2009, 2021
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Brain-inspired computing employs devices and architectures that emulate biological functions for more adaptive and energy-efficient systems. Oscillatory neural networks (ONNs) are an alternative approach in emulating biological functions of the human brain and are suitable for solving large and complex associative problems. In this work, we investigate the dynamics of coupled oscillators to implement such ONNs. By harnessing the complex dynamics of coupled oscillatory systems, we forge a novel computation model--information is encoded in the phase of oscillations. Coupled interconnected oscillators can exhibit various behaviors due to the strength of the coupling. In this article, we present a novel method based on subharmonic injection locking (SHIL) for controlling the oscillatory states of coupled oscillators that allow them to lock in frequency with distinct phase differences. Circuit-level simulation results indicate SHIL effectiveness and its applicability to large-scale oscillatory networks for pattern recognition.
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications
M. Abernot, T. Gil, M. Jiménez, J. Núñez, M.J. Avellido, B. Linares-Barranco, T. Gonos, T. Hardelin and A. Todri-Sanial
Journal Paper · Frontiers in Neuroscience, vol. 15, article 713054, 2021
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Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called ‘data deluge gap ’). This has resulted in investigating novel computing paradigms and design approaches at all levels from materials to system-level implementations and applications. An alternative computing approach based on artificial neural networks uses oscillators to compute or Oscillatory Neural Networks (ONNs). ONNs can perform computations efficiently and can be used to build a more extensive neuromorphic system. Here, we address a fundamental problem: can we efficiently perform artificial intelligence applications with ONNs? We present a digital ONN implementation to show a proof-of-concept of the ONN approach of ‘computing-in-phase’ for pattern recognition applications. To the best of our knowledge, this is the first attempt to implement an FPGA-based fully-digital ONN. We report ONN accuracy, training, inference, memory capacity, operating frequency, hardware resources based on simulations and implementations of 5 × 3 and 10 × 6 ONNs. We present the digital ONN implementation on FPGA for pattern recognition applications such as performing digits recognition from a camera stream. We discuss practical challenges and future directions in implementing digital ONN.
Insights into the Dynamics of Coupled VO2 Oscillators for ONNs
J. Núñez, J.M. Quintana, M.J. Avedillo, M. Jiménez, A. Todri-Sanial, E. Corti, S. Karg and B. Linares-Barranco
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 10, pp 3356-3360, 2021
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The collective behavior of many coupled oscillator systems is currently being explored for the implementation of different non-conventional computing paradigms. In particular, VO2 based nano-oscillators have been proposed to implement oscillatory neural networks that can serve as associative memories, useful in pattern recognition applications. Although the dynamics of a pair of coupled oscillators have already been extensively analyzed, in this paper, the topic is addressed more practically. Firstly, for the application mentioned above, each oscillator needs to be initialized in a given phase to represent the input pattern. We demonstrate the impact of this initialization mechanism on the final phase relationship of the oscillators. Secondly, such oscillatory networks are based on frequency synchronization, in which the impact of variability is critical. We carried out a comprehensive mathematical analysis of a pair of coupled oscillators taking into account both issues, which is a first step towards the design of the oscillatory neural networks for associative memory applications.
Oscillatory Neural Networks using VO2 based Phase Encoded Logic
J. Núñez, M.J. Avedillo, M. Jiménez, J.M. Quintana, A. Todri-Sanial, E. Corti, S. Karg and B. Linares-Barranco
Journal Paper · Frontiers in Neuroscience, vol. 15, article 655823, 2021
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Nano-oscillators based on phase-transition materials are being explored for the implementation of different non-conventional computing paradigms. In particular, vanadium dioxide (VO 2) devices are used to design autonomous non-linear oscillators from which oscillatory neural networks (ONNs) can be developed. In this work, we propose a new architecture for ONNs in which sub-harmonic injection locking (SHIL) is exploited to ensure that the phase information encoded in each neuron can only take two values. In this sense, the implementation of ONNs from neurons that inherently encode information with two-phase values has advantages in terms of robustness and tolerance to variability present in VO2 devices. Unlike conventional interconnection schemes, in which the sign of the weights is coded in the value of the resistances, in our proposal the negative (positive) weights are coded using static inverting (non-inverting) logic at the output of the oscillator. The operation of the proposed architecture is shown for pattern recognition applications.
Approaching the Design of Energy Recovery Logic Circuits using Tunnel Transistors
J. Núñez and J.M. Avedillo
Journal Paper · IEEE Transactions on Nanotechnology, vol. 19, pp 500-507, 2020
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Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope, and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account that problems associated with the inverse current of their intrinsic p-i-n diode. In this paper, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.
Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A. Acosta
Journal Paper · ACM Journal on Emerging Technologies in Computing Systems, vol. 16, no. 3, article 30, 2020
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The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4-bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude.
Hybrid Phase Transition FET Devices for Logic Computation
M. Jiménez, J. Núñez and M.J. Avedillo
Journal Paper · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, pp 1-8, 2020
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Hybrid Phase Transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON to OFF current ratio. In this paper, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ONOFF current tradeoffs are evaluated at circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, on the basis of this analysis, the paper proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained which were lower than those achieved with low standby power (LSTP) FinFETs and high performance (HP) FinFETs. The paper also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.
Design and analysis of secure emerging crypto-hardware using HyperFET devices
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A.J. Acosta
Journal Paper · IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp 787-796, 2020
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The emergence of new devices to be used in low-power applications are expected to reach impressive performance compared to those obtained by equivalent CMOS counterparts. However, when used in lightweight security applications, these emerging paradigms are required to be reliable and safe enough during the task of protecting important and valuable data. In this work, the usage of HyperFET devices for security applications has been analyzed and new paradigms for enhancing security against Power Analysis attacks have been developed for the first time. To perform this analysis, classical dual-precharge logic primitives implemented with 14nm FinFET have been upgraded to incorporate HyperFET devices. The proposed primitives incorporating HyperFETs, as well as a 4-bit Substitution box of PRIDE algorithm as demonstrative example, have been designed and simulated using predictive models. Simulation-based Differential Power Analysis attacks demonstrate high improvements in security levels in a x25 factor at least, with negligible degradation in performance. This first approach could be easily extensible to other ciphers or crypto-circuits, where the incorporation of HyperFET devices will enhance security for most future applications.
Phase Transition Device for Phase Storing
M.J. Avedillo, J.M. Quintana and J. Núñez
Journal Paper · IEEE Transactions on Nanotechnology, vol. 19, pp 107-112, 2020
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Nano-oscillators based on phase transitions materials (PTM) are being explored for the implementation of different non-conventional computing paradigms. This paper describes the capability of such autonomous non-linear oscillators to store phase-encoded information. A latch based in sub-harmonic injection locking using an oscillator composed of a PTM device and a transistor is described. Resistive coupling is used to inject both a required synchronization signal and the input to be stored. Operation of the proposed latch implementation, the embedding of functionality into the latch and its application to frequency division are illustrated and validated by simulation.
Power and Speed Evaluation of Hyper-FET Circuits
J. Núñez and M.J. Avedillo
Journal Paper · IEEE Access, vol. 7, pp 6724-6732, 2019
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Many emerging devices are currently being explored as potential alternatives to complementary metal-oxide-semiconductor (CMOS) technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at circuit level. In this paper, we investigate the speed and power performance of Hyper-Field Effect Transistor (Hyper-FET) circuits, comparing them with both high-performance (HP) and low stand-by power (LSTP) Fin-Shaped Field Effect Transistor (FinFET) designs on the same technology node. The evaluation, which was carried out at gate and circuit level, includes characterization of 8 bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from transistor and gate level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated which support the obtained results.
Phase Transition FETs for Improved Dynamic Logic Gates
M.J. Avedillo, M. Jiménez and J. Núñez
Journal Paper · IEEE Electron Device Letters, vol. 39, no. 11, pp 1776-1779, 2018
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Transistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. In addition to the replacement of the transistors in conventional static CMOS logic circuits, the distinguishing features of Phase Change FETs can be exploited in other application domains or can be useful for solving specific design challenges. In this paper, we take advantage of them to implement a smart dynamic gate in which undesirable contention currents are reduced, leading to speed advantage without power penalties.
Impact of the RT-level architecture on the power performance of tunnel transistor circuits
M.J. Avedillo and J. Núñez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 46, no. 3, pp 647-655, 2018
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Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer-level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.
Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
J. Nuñez and M.J. Avedillo
Journal Paper · IEEE Journal of the Electron Devices Society, vol. 5, no. 6, pp 530-534, 2017
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RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this paper, we analyze the limitations of typical TFET rectifier topologies associated with the forward biasing of their intrinsic diode and show that this can occur at relatively weak input signals depending on the specific characteristic of the used tunnel device. We propose a simple modification in the implementation of the rectifiers to overcome this problem. The impact of our proposal is evaluated on the widely used gate cross-coupled topology. The proposed designs exhibit similar peak PCE and sensitivity but significantly improve PCE for larger input signal amplitude and larger input power.
Insights into the Operation of Hyper-FET-Based Circuits
M.J. Avedillo and J. Nuñez
Journal Paper · IEEE Transactions on Electron Devices, vol. 64, no. 9, pp 3912-3918, 2017
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Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the I-ON/I-OFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called hyper-FET to simulate different circuits, and to analyze the impact of the degraded dc output voltage levels of hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements. We show that these estimations can reduce, cancel, or even lead to power penalties in low switching and/or low-frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design.
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
J. Núñez and M.J. Avedillo
Journal Paper · IEEE Transactions on Nanotechnology, vol. 16, no, 1, pp 83-89, 2017
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Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four MOSFET and FinFET transistors. The impact of logic depth, switching activity and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
J. Núñez and M.J. Avedillo
Journal Paper · IEEE Transactions on Electron Devices, vol. 63, no. 12, pp 5012-5020, 2016
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In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas.
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
J. Núñez, A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 89, no. 33, pp 593-609, 2016
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This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100 fsrms) for high-performance ADCs. The key ideas of the design methodology are: (a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, (b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100 fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8 V 0.18 μm and 1.2 V 90 nm). Post-layout simulation results for a case of study with typical jitter of 68 fs for a 1.8 V 80 dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.
Improving speed of tunnel FETs logic circuits
M.J. Avedillo and J. Núñez
Journal Paper · Electronics Letters, vol. 51, no. 21, pp 1702-1704, 2015
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Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital tunnel FET circuits leading to delay degradation. A minor modification of the complementary gate topology to avoid the bootstrapping problem is proposed and its impact on speed at the circuit level is shown. Speed improvements up to 33% have been obtained for 8-bit ripple carry adders when implemented with the solution.
Experimental validation of a two-phase clock scheme for fine-grained pipelined circuits based on monostable to bistable logic elements
J. Nuñez, M.L. Avedillo and J.M. Quintana
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp 2238-2242, 2014
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Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating two series connected negative differential resistance devices with a clock bias. This brief describes and experimentally validates a two-phase clock scheme for such MOBILE-based ultragrained pipelines. Its advantages over other reported interconnection schemes for MOBILE gates, and also over pure CMOS two-phase counterparts, are stated and analyzed. Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE circuit to have been reported with this interconnection architecture.
Novel pipeline architectures based on Negative Differential Resistance devices
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper · Microelectronics Journal, vol. 44, no. 9, pp 807-813, 2013
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Devices exhibiting Negative Differential Resistance (NDR) in their I-V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.
Two-phase RTD-CMOS pipelined circuits
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper · IEEE Transactions on Nanotechnology, vol. 11, no. 6, pp 1063-1066, 2012
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MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have been reported using different clock schemes including a four-phase strategy and a single-phase clock scheme. In particular, significant power advantages of single-phase RTD-CMOS MOBILE circuits over pure CMOS have been shown. This letter compares the RTD-CMOS realizations using a single clock and a novel two-phase clock solution. Significant superior robustness and performance in terms of power and area are obtained for the two-phase implementations.
Domino inspired MOBILE networks
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper · Electronics Letters, vol. 48, no. 5, pp 292-293, 2012
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MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported that alternates rising and falling edge-triggered MOBILE gates. A novel two-phase interconnection scheme resembling conventional domino pipelines is proposed and validated. It exhibits advantages in terms of speed with respect to both four-phase and single-phase interconnection schemes. In addition, the new architecture improves logic flexibility regarding the domino pipeline counterpart, since inverting and non-inverting stages can be interspersed.
RTD-CMOS pipelined networks for reduced power consumption
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper · IEEE Transactions on Nanotechnology, vol. 10, no. 6, pp 1217-1220, 2011
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The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work in this direction is required. In this letter, we compare RTD-CMOS and pure CMOS realizations of a logic gate network which can be operated in a gate-level pipeline. Significantly lower average power is obtained for RTD-CMOS implementations.
Simplified single-phase clock scheme for MOBILE networks
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper · Electronics Letters, vol. 47, no. 11, pp 648-649, 2011
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MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required for this. A single-phase scheme is possible adding latches to the MOBILE gates. Proposed and experimentally validated is a new single-phase interconnection scheme that simplifies the inter-stage element, which translates in power, area and clock load advantages with respect to using latches.
Efficient realisation of MOS-NDR threshold logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper · Electronics Letters, vol. 45, no. 23, pp 1158-1159, 2009
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A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.
Operation limits for RTD-based MOBILE circuits
J.M. Quintana, M.J. Avedillo, J. Nuñez and H.P. Roldan
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 2, pp 350-363, 2009
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Resonant-tunneling-diode (RTD)-based MOnostable-BIstable Logic Element (MOBILE) circuits operate properly in a certain frequency range. They exhibit both a minimum operating frequency and a maximum one. From a design point of view, it should be desirable to have gates with a correct operation from do up to the maximum operating frequency (i.e., without the minimum bound). This paper undertakes this problem by analyzing how transistors and RTDs interact in RTD-based circuits. Two malfunctions have been identified: the incorrect evaluation of inputs and the lack of self-latching operation. The difficulty to study these problems in an analytical way has been overcome by resorting to series expansions for both the RTD and the heterojunction field-effect transistor I-V characteristics in the points of interest. We have obtained analytical expression linking representative device parameters and technological setup, for a MOBILE-based circuit to operate correctly.
Congresos
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices
J. Núñez, M.J. Avedillo and M. Jiménez
Conference · International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2023
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Abstract not available
Energy-efficient Brain-inspired Oscillatory Neural Networks using Phase-Transition Material
M. Jiménez, B. Linares-Barranco, M.J. Avedillo and J. Núñez
Conference · Workshop on Deep Learning meets Neuromorphic Hardware. European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases ECML PKDD 2023
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Oscillatory Neural Network (ONN) is a promising neuromorphic computing approach which uses networks of frequency-locked coupled oscillators, and their inherent parallel synchronization to compute. Also, ONN can be im-plemented using phase-transition materials using nano-scale area, low voltage amplitude and reduced power consumption, being an efficient way to im-plement oscillator-based computing. In state-of-theart, ONN is built with a fully-connected architecture, with coupling configured depending on the tar-get application. Its most widespread use has been as associative memory, but recently it is gathering interest as a solver for non-deterministic polynomial time problem (NP-hard). This is performed on the basis of encoding the NP-problem in the Ising model, so ONN operates as an Ising machine. ONN state naturally evolves to minimum points in the Hamiltonian energy function re-sorting to its rich non-lineal dynamics, supposing a promising paradigm of fast, low-power, parallel computation.
Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks
M. Jiménez, J. Núñez, J. Shamsi, B. Linares-Barranco and M.J. Avedillo
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
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The utilization of phase-transition materials-based nano-oscillators is being investigated to apply various non-traditional computing paradigms. Specifically, vanadium dioxide (VO2) devices are used to design self-sustained non-linear oscillators that can be employed for oscillatory neural networks (ONNs). In addition, in these ONN architectures sub-harmonic injection locking (SHIL) can be exploited to ensure that each neuron's phase information can only adopt one of two possible values. An integrated circuit demonstrator of an analog 9-neuron ONN using a deep-submicron commercial technology have been designed and fabricated. The oscillators forming the neurons closely resemble those designed using VO2 devices. The capability of the fabricated ONN to work as an associative memory has been tested. An example of two store patterns has been used to show that the ONN successfully stores the two patterns and exhibits the associative memory functionality.
Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
M. Jiménez, M.J. Avedillo, B. Linares-Barranco and J. Núñez
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
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Alternative paradigms to the von Neumann computing scheme are currently arousing huge interest. Oscillatory neural networks (ONNs) using emerging phase-change materials constitute an energy-efficient, massively parallel, brain-inspired, in-memory computing approach. The encoding of information in the phase pattern of frequency-locked, weakly coupled oscillators makes it possible to exploit their rich nonlinear dynamics and their synchronization phenomena for computing. A single fully connected ONN layer can implement an auto-associative memory comparable to that of a Hopfield network. Hebbian learning rule is the most widely adopted method for configuring ONNs for such applications, despite its well-known limitations. Other approaches that perform better than the Hebbian rule are not useful for ONN training due to the constraints imposed by its physical implementation. This paper proposes a new approach and compares it with previous work. The proposed method has been shown to produce competitive results in terms of pattern recognition accuracy with reduced precision in synaptic weights, and to be suitable for online learning.
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory
M. Jiménez, M.J. Avedillo, J. Núñez and B. Linares-Barranco
Conference · XXXVII Conference on Design of Circuits and Integrated Systems DCIS 2022
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Abstract not available
Solving Combinatorial Optimization Problems with Coupled Phase Transition based Oscillators
J. Núñez, M.J. Avedillo and M. Jiménez
Conference · XXXVII Conference on Design of Circuits and Integrated Systems DCIS 2022
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Abstract not available
Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications
J. Núñez, S. Thomann, H. Amrouch and M.J. Avedillo
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2022
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Coupled oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. Coupled nano-oscillator implementations using emerging devices have arisen, but the immaturity of these technologies has allowed only simple experimental demonstrations. The potential of Negative Capacitance FET (NCFET) for such applications has recently been recognized, which is a step towards the physical realization given their ease of co-integration with commercial CMOS technologies. However, the design of circuits using these devices can be seriously compromised by the variability inherent in them. In this paper, we will highlight this problem through the design of an oscillatory neural network for pattern recognition applications. We propose the application of subharmonic injection mechanisms to mitigate the impact of NCFET transistor variability and present results showing that the performance of these circuits improves significantly.
FeFETs for Phase Encoded Oscillatory based Computing
J. Núñez, M. Jiménez, B. Linares-Barranco and M.J. Avedillo
Conference · Design, Automation and Test in Europe DATE 2022
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Coupled nano-oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. The potential of Ferroelectric Field-Effect Transistor (FeFET) for such applications has recently been recognized, which is a step towards the physical realization given their ease of cointegration with commercial CMOS technologies. This paper investigates the design of oscillators using FeFETs and their potential for oscillator-based computing in which information is encoded in phase. As applications, we present the operation of FeFET coupled oscillators systems for graph coloring and Max-Cut problems, including subharmonic injection mechanism to discretize the phase in the second one.
FeFETs for Phase Encoded Oscillatory based Computing
J. Nunez, M. Jimenez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2021
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Coupled oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. Coupled nano-oscillator implementations using emerging devices have arisen, but the immaturity of these technologies has allowed only simple experimental demonstrations. The potential of Ferroelectric Field-Effect Transistor (FeFET) for such applications has recently been recognized, which is a step towards the physical realization given their ease of cointegration with commercial CMOS technologies. This paper investigates the design of oscillators using FeFETs and their potential for oscillatory-based computing (OBC) in which information is encoded in phase. After analyzing the FeFET-based oscillator, the operation of an Oscillatory Hopfield Neural Network (OHNN) for image classification applications in a 2x2 size example is illustrated. Finally, it is shown that this type of oscillator can also be combined with a subharmonic injection mechanism to discretize the phase as it is required in coupled oscillator’s networks for solving combinatorial optimization problems.
An Approach to the Device-Circuit Co-Design of HyperFET Circuits
M. Jiménez, J. Núñez and M.J. Avedillo
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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In this paper, we describe device-circuit co-design experiments for Hybrid Phase Transition FETs (HyperFETs). HyperFET transistors, built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON current without triggering the OFF current. This enables reducing supply voltage and so power consumption. HyperFETs with different ON-OFF currents tradeoffs are analyzed. Inverter chains and ring oscillators built with them are evaluated in terms of power and compared to reference designs using FETs alone. Power reductions up to 32% are shown for a HyperFET with similar OFF current and higher ON current than its FET counterpart when nodes frequently switch. However, power penalties by a factor of 400 have been obtained for other simulation stimuli. Our results identify switching activity as critical for obtaining power savings and suggest guidance both at device and circuit level to take full advantage of these devices.
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits
J. Núñez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
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Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope (SS), and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account the problems associated with their inverse current due to their intrinsic p-i-n diode. In this paper, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially at medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits, both at gate and architecture levels, with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks
P. Martin-Lloret, J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
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This paper presents an integrated circuit (IC) array whose purpose is to observe, quantify and characterize the impact of time-dependent variability effects, like aging, in several widely used digital and analog circuit blocks. With the increasing interest that this kind of mechanism has attracted in the last years, for its potential impact in the reliability of ultra-scaled integrated circuits, it is only relevant that appropriate measures are taken to find out how it can be included (and thus mitigated) in the design process of such integrated circuits. And, while substantial literature exists that covers the device level, time-dependent variability at circuit level has not been as equally studied. This work complements our previous efforts in providing a holistic approach to Reliability-Aware Design: from statistical characterization and modeling at device-level, to simulation, and into optimization-based design with reliability considerations, the array presented here provides one more step towards a thorough and accurate understanding of how time-dependent variability works at the circuit level.
Device circuit co-design of HyperFET transistors
J. Núñez, M. Jiménez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
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In this paper, we describe device-circuit co-design experiments for Hybrid Phase Transition FETs (HyperFETs). HyperFET transistors, built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON current without triggering the OFF current. This enables reducing supply voltage and so power consumption. HyperFETs with different ON-OFF currents tradeoffs are analyzed. Inverter chains and ring oscillators built with them are evaluated in terms of power and compared to reference designs using FETs alone. Power reductions up to 50% are shown for a HyperFET with similar OFF current and higher ON current than its FET counterpart when nodes frequently switch. However, power penalties by a factor of 80 have been obtained for other simulation stimuli. Our results identify switching activity as critical for obtaining power advantages from the supply voltage reduction permitted by HyperFETs, and suggest guidance both at device and circuit level to take full advantage of these devices.
Experimental Characterization of Time-Dependent Variability in Ring Oscillators
J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
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Reliability in CMOS-based integrated circuits has always been a critical concern. In today′s ultra-scaled technologies, a time-varying kind of variability has raised that, on top of the well-known time-zero variability, threatens to shorten the lifetime of integrated circuits, both analog and digital. Effects like Bias Temperature Instability and Hot Carriers Injection need to be studied, characterized and modeled to include, and, thus, mitigate, their impact in the design of CMOS integrated circuits. This paper presents an array-based integrated circuit whose purpose is precisely that: to observe, quantify and characterize the impact of timedependent variability effects in a specific kind of circuits: Ring Oscillators.
Device Circuit Co-Design of HyperFET Transistors
J. Núñez and M.J. Avedillo
Conference · International Forum on Information Systems and Technologies INFOS 2019
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In this paper, we describe a device-circuit codesign experiment for Hybrid Phase Transition FETs (HyperFETs) transistors. Inverter chains and ring oscillators are evaluated using three HyperFETs devices. Our results suggest guidance for device design to avoid known power penalty mechanisms at the circuit level.
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
E. Tena-Sánchez, I.M. Delgado-Lozano, J. Nuñez and A.J. Acosta
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2018
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The design of cryptographic circuits is requiring greater performance restrictions due to the constrained environments for IoT applications in which they are included. Focusing on the countermeasures based on dual-precharge logic styles, power, area and delay penalties are some of their major drawbacks when compared to their static CMOS single-ended counterparts. In this paper, we propose a initial study where scaled CMOS technnology and FinFET emerging technology are considered to foresee the relationship between ultra low power consumption, reduced delay, and security. As demonstration vehicle, we measure the performance and the security level achieved by different Substitution Boxes, implemented in different technologies. As main results, nanometer CMOS technologies maintains considerable security levels at reasonable power and delay figures, while FinFETs outperform CMOS in power and delay reduction, but with a non negligible degradation in security.
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jimenez, M.J. Avedillo and J. Núñez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
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Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.
Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
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Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.
Impact of TFET reverse currents into circuit operation: A case study
J. Nuñez
Conference · Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2018
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Tunnel FET transistors (TFETs) are one of the most promising candidates to replace CMOS transistors for future integrated circuits. However TFET-based circuit design can exhibit significant limitations due to their reverse conduction currents caused by the direct bias of the intrinsic diode of these transistors. In this paper we analyze in depth this issue through the design of charge pump (DC-DC step up converters) circuits for energy harvesting applications. The proposed solution mitigates the impact of reverse conduction currents and, thus, improves power conversion efficiencies (PCE) compared to previous designs.
Exploring Logic Architectures Suitable for TFETs Devices
J. Núñez and M.J. Avedillo
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
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Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are critical for IoT development. Although they show higher ON currents than CMOS at low supply voltages, currently TFETs do not reach those exhibited by CMOS at its nominal supply voltage and so they have being identified to be competitive for moderate operating frequencies. However, in many cases, architectural choices are not taken into account when benchmarking them against CMOS. In this paper we claim that the logic architecture should be selected in order to take full advantage of the specific characteristics of these devices. Widely used circuits are designed and evaluated showing how properly tuning the logic architecture results in raising the frequency up to which TFETs are competitive or in increasing power savings at lower frequencies.
Complementary Tunnel Gate Topology to Reduce Crosstalk Effects
J. Núñez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
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Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated.
Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits
M.J. Avedillo and J. Núñez
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2016
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Tunnel transistors are one of the most attractive steep sub threshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, we analyze the impact of the logic depth into the power consumption and energy efficiency of logic circuits and show critical differences between tunnel transistors and CMOS technologies, due to the distinct delay versus supply voltages exhibited by each type of device. Obtained results show that reducing logic depth as a power reduction technique is more efficient for tunnel transistors circuits than for their CMOS counterparts. A simple model to estimate the power reductions achieved when using pipeline to cut down logic depth, and taking into account the power overheads associated to the pipelined registers is developed. It shows that in CMOS power benefits cancels with the incorporation of a number of flip-flops equal to the 5% of the number of gates in the original circuit while this number rises to 90% for tunnel circuits. Simulation experiments of a simple adder tree are carried out to validate our analysis. No power savings are obtained by the CMOS pipelined circuit while the TFET pipelined circuit saves 77% of power. The results of this work suggest that architectural issues should be considered in the evaluation of this type of transistors.
Secure Cryptographic Hardware Implementation Issues for High-Performance Applications
E. Tena-Sánchez, A.J. Acosta and J. Nuñez
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2016
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In this paper the effect of high-performance techniques for high speed applications in secure cryptographic implementations is studied. The use of dual precharge logic styles with fine-grained pipelining with an overlapping three-phase clock scheme is studied, also including a correct distribution of the clock signal in the cryptographic implementation. To make this study, four different implementations of the Sbox-9 of the Kasumi algorithm have been implemented using an 90nm TSMC technology. Simulation-based DPA attacks have been carried out, showing how the proper synchronization of data signals gives better results in terms of power consumption and operating frequency, but affects negatively the security against side channel attacks, decreasing the number of input patterns needed to disclosure the secret key.
Assessing application areas for tunnel transistor technologies
M.J. Avedillo and J. Núñez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
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Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.
Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
J. Núñez, A.J. Gines, E. Peralías and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
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High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (< 200fs) are introduced and compared in a 0.18μm commercial CMOS process.
Improving robustness of dynamic logic based pipelines
H.J. Quintero, M.J. Avedillo and J. Núñez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
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Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the non-inverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its non-inverting feature.
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs
J. Núñez, A.J. Ginés, E.J. Peralías and A. Rueda
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2015
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This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for highperformance ADCs. The key idea is twofold: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) performing a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm).
DOE Based High-Performance Gate-Level Pipelines
J. Núñez, M.J. Avedillo and H.J. Quintero
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2014
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Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the noninverting behavior of domino gates, there are also performance disadvantages when compared to inverting dynamic gates, which can be related to this feature. These penalties rise from the fact that in order to produce a logic one, a non-inverting gate requires one or more of its inputs to be also at logic one. We analyze the operation of gate-level pipelines implemented with domino and with Delayed Output Evaluation (DOE), an inverting dynamic gate we have recently proposed, and compare their performance. Using domino and DOE gates similar in terms of delay, improvements in operating frequencies around 50% have been obtained by the DOE pipelines.
Novel dynamic gate topology for superpipelines in DSM technologies
J. Nuñez, M.J. Avedillo and J.M. Quintana
Conference · Euromicro Conference on Digital System Design DSD 2013
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Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high throughput. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and the Carry-Merge chain of a Kogge-Stone adder is designed as an application example.
Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications
J. Núñez, M.J. Avedillo, J.M. Quintana and H.J. Quintero
Conference · Conference on the Design of Circuits and Integrated Systems DCIS 2013
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Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high through-output. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and a gate per phase Carry Look Ahead adder is designed as an application example.
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J. Nuñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an 'all MOS' version of one previously reported which uses Resonant Tunneling Diodes (RTDs). The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications
J. Núñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2012
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Monostable to Bistable (MOBILE) gates are very suitable for the implementation of gate-level pipelines which can be achieved without resorting to memory elements. MOBILE operating principle is implemented using two series connected Negative Differential Resistance (NDR) devices with a clocked bias. This paper describes and experimentally validates a two-phase clock scheme for such MOBILE based ultra-grain pipelines. Up to our knowledge it is the first MOBILE working circuit reported with this interconnection architecture. The proposed interconnection architecture is applied to the design of a 4-bit Carry Look-ahead Adder.
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J. Núñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference · Iberchip XVIII Workshop IWS 2012
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The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an ¿all MOS¿ version of one previously reported which use Resonant Tunneling Diodes (RTDs) The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.
Compact and Power Efficient MOS-NDR Muller C-Elements
J. Núñez-Martínez, M. J. Avedillo and J.M. Quintana-Toledo
Conference · IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems DoCEIS 2012
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Recently there is a renewed interest in the development of transistor circuits which emulate the Negative Differential Resistance (NDR) exhibited by different emerging devices like Resonant Tunneling Diodes (RTDs). These MOS-NDR circuits easily allow the prototyping of design concepts and techniques developed for such NDR devices. The importation of those concepts into transistor technologies can result in circuit realizations which are advantageous for some functionalities and application fields. This paper describes a Muller C-element which illustrates this statement which is inspired in an RTD-based topology. The required RTD is implemented by means of the MOS-NDR device. A 4-input Muller C-element has been fabricated and experimentally validated. The proposed circuit compares favorably with respect to a well-known conventional gate realization.
Efficient realization of RTD-CMOS logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference · Great Lakes Symposium on VLSI GLSVLSI 2011
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The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined. Lower average power and energy per cycle are obtained for RTD/CMOS implementations. Copyright © 2011 by ASME.
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs
J. Nuñez, M.J. Avedillo and J.M. Quintana
Conference · SPIE Microtechnologies for the New Millennium 2011
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The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. We compare RTD-CMOS and pure CMOS realizations of a network of logic gates which can be operated in a gate-level pipeline. Significant lower average power is obtained for RTD-CMOS implementations.
Redes MOBILE MOS-NDR operando con reloj de una fase
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference · Iberchip XVI Workshop IWS 2010
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La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative Differential Resistance, NDR) resulta atractiva desde el punto de vista del diseño de circuitos, como ha sido demostrado por los circuitos que usan diodos basados en el efecto túnel resonante (Resonant Tunneling Diodes, RTDs). Ideas procedentes de diseños con RTDs pueden exportarse a un entorno 'todo CMOS' en el que la característica NDR se obtiene mediante transistores (MOS-NDR). En este artículo se proponen estructuras MOS-NDR para realizar puertas lógicas (Threshold Gates, TGs) que operan según el principio de operación MOBILE (MOnostable to BIstable Logic Element). Además, se demuestra que estas puertas pueden interconectarse para formar redes que operan en modo pipeline usando un esquema de reloj de una fase.
Evaluation of RTD-CMOS logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference · Euromicro Conference on Digital System Design DSD 2010
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The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined fashion, thus allows estimating logic networks operating frequency. Lower power-delay products are obtained for RTD/CMOS implementations. © 2010 IEEE.
Single phase MOS-NDR mobile networks
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
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Devices with an I-V characteristic exhibiting Negative Differential Resistance (NDR) are attractive from the circuit design point of view as it has been demonstrated by Resonant Tunneling Diodes (RTDs) circuits. Ideas coming from RTD-based designs can be exported to an "all CMOS" environment by using transistor circuits to generate the NDR characteristic (MOS-NDR). In this paper novel programmable MOS-NDRs are proposed and used to realize threshold logic gates on the basis of the MOnostable to BIstable Operating principle. It is shown that these gates can be connected to build up networks that are operated in a pipelined fashion using a single phase clock scheme.
Fast and area efficient multi-input Muller C-element based on MOS-NDR
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2009
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A new multi-input Muller C-element based on a MOS-NDR device is proposed in this contribution. This design overcomes some drawbacks of previously proposed structures. A comparison in terms of area, delay and power consumption over another efficient CMOS Muller C-element circuit has been performed, resulting that our structure improves this performance.
Design of RTD-based NMIN/NMAX gates
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE Conference on Nanotechnology, IEEE-NANO 2008
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A novel implementation of NMIN/NMAX gates based on RTDs and transistors is presented. In this paper we will derive the relations that circuit representative parameters must verify to obtain a correct behaviour by means of the principles of the Monostable-to-Multistable Logic (MML). HSPICE simulations will be used to check our theoretical results. © 2008 IEEE.
Limits to a correct evaluation in RTD-based quaternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · International Symposium on Multiple-Valued Logic ISMVL 2007
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML quaternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.
Operation limits for MOBILE followers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE Conference on Nanotechnology IEEE-NANO 2006
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This paper analyses how the presence of the HFET transistor modifies the DC operation of a Resonant Tunneling Logic Follower MOBILE, and can prevent its correct operation. The difficulty of an analytical study for the resulting circuit has been overcome by resorting to series expansions for both the RTD and the HFET I-V characteristics in the points of interest. We have obtained analytical expressions describing the regions where a MOBILE follower operates correctly. © 2006 IEEE.
Holding Dissapearance in RTD-based Quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · European Nano Systems Worshop ENS 2005
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. The operation of such quantizer has two steps : sampling and holding. Once the quantizer samples the signal, it must maintain the sampled value even if the input changes. However, holding property is not inherent to MML circuit topologies. This paper analyses the case of an MML ternary inverter used as a quantizer, and determines the relations that circuit representative parameters must verify to avoid this malfunction.
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Analytic Approach to the Operation of RTD Ternary Inverters Based on MML
J. Núñez, J.M. Quintana and M.J. Avedillo
Book Chapter · Cutting Edge Nanotechnology, pp 97-112, 2010
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaMultiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.
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