Encontrados resultados para:
Autor: Miguel A. Lagos Florido
Año: Desde 2002
Artículos de revistas
CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutierrez and M.A. Lagos-Florido
Journal Paper · IEEE Transactions on Nuclear Science, vol. 63, no. 4, pp. 2379-2389, 2016
resumen
doi
This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35 μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.
A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz,A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Journal Paper · IEEE Transactions on Magnetics, vo. 51, no. 1, article 4001804, 2015
resumen
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This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D magnetometer for space applications, with a significant reduction in mass and volume while maintaining a high sensitivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances and a rad-hard mixed-signal ASIC designed in a standard 0.35 μm CMOS technology. The ASIC performs sensor-signal conditioning and analogue-to-digital conversion, and handles calibration tasks, system configuration, and communication with the outside. The proposed system provides high sensitivity to low magnetic fields, down to 3 nT, while offering a small and reliable solution under extreme environmental conditions in terms of radiation and temperature.
Four-channel self-compensating single-slope ADC for space environments
S. Sordo-Ibáñez, S. Espejo-Meana, B. Piñero-García, A. Ragel-Morales, J. Ceballos-Cáceres, M. Muñoz-Díaz, L. Carranza-González, A. Arias-Drake, J.M. Mora-Gutiérrez, M.A. Lagos-Florido and J. Ramos-Martos
Journal Paper · Electronics Letters, vol. 50, no.8, pp 579-581, 2014
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A multichannel high-resolution single-slope analogue-to-digital converter (SS ADC) is presented that automatically compensates for process, voltage and temperature variations, as well as for radiation effects, in order to be used in extreme environmental conditions. The design combines an efficient implementation by using a feedback loop that ensures an inherently monotonic and very accurate ramp generation, with high levels of configurability in terms of resolution and conversion rate, as well as input voltage range. The SS ADC was designed in a standard 0.35 μm CMOS technology. Experimental measurements of the performance and stability against radiation and temperature are presented to verify the proposed approach.
Congresos
Characterization, Screening and Qualification of the MEDA Wind-Sensor ASIC
S. Espejo, J. Ceballos, A. Ragel, L. Carranza, J.M. Mora, M.A. Lagos, J. Ramos, S. Sordo, E. Cordero and D. López
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2018
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The paper describes the final characterization results of the MEDA-WS ASIC, which was described in a previous paper in AMICSA-2016. It describes as well the qualification and the screening processes that have been carried out, and the present status of its integration and calibration in the final engineering and flying modules of the wind-sensor instrument.
A Front-End ASIC for a 3-D Magnetometer for Space Applications Based on Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · European Conference on Magnetic Sensors and Actuators EMSA 2014
resumen
Abstract not avaliable
A Rad-Hard Multichannel Front-End Readout ASIC for Space Applications
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · IEEE International Workshop on Metrology for Aerospace METROAEROSPACE 2014
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This paper presents a single-chip solution for sensor-signals conditioning and digitalization in space applications. The rad-hard ASIC implements a set of 6 generic instrumentation channels that are highly configurable in terms of resolution, conversion rate, and input voltage range, providing a flexible solution for space applications requiring the digital acquisition of slow input signals with medium-to-high resolutions. The resolution can be configured between 12 bits at 19.6 kS/s and 16 bits at 2.6 kS/s. The differential input voltage range can be extended up to 4 Vpp. The instrumentation channels combine a programmable-gain, high input impedance instrumentation amplifier and dual-slope analog-to-digital converters with radiation hardening by design (RHBD) techniques in a standard 0.35 μm CMOS technology. Experimental results demonstrate the performance of the ASIC across an operating temperature range of -90 ºC to +125 ºC and its robustness against radiation effects up to 318 krad of TID, absence of latch-up up to at least 81.8 MeV·cm2/mg, and a SEUs LETth of 22.5 MeV·cm2/mg.
SEE Characterization of a Magnetometer Front-End ASIC using a RHBD Digital Library in AMS 0.35μm CMOS
J. Ramos-Martos, A. Arias-Drake, L. Carranza-González, S. Sordo-Ibáñez, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, S. Espejo-Meana and M.A. Lagos-Florido
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2014
resumen
A radiation-hardened-by-design (RHBD) digital library, developed for the Austria Microsystems (AMS) 0.35μm CMOS technology has been applied in a mixedsignal ASIC that operates as a multi-channel data acquisition system for magnetometers using anisotropic magnetoresistances (AMR). The circuit has been tested in the Heavy-Ion facilities of the Université Catholique de Louvain-la-Neuve (HIF-UCL). The experimental results demonstrate a LET threshold of 22.5 MeV·cm2/mg and absence of latchup up to 81.8 MeV·cm2/mg. This radiation-tolerant performance is obtained at the cost of a penalty in area and power with respect to the unhardened technology.
An Adaptive Approach to On-Chip CMOS Ramp Generation for High Resolution Single-Slope ADCs
S. Sordo-Ibanez, B. Piñero-García, S. Espejo-Meana, A. Ragel-Morales, J. Ceballos-Cáceres, M. Muñoz-Díaz, L. Carranza-González, A. Arias-Drake, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · European Conference on Circuit Theory and Design ECCTD 2013
resumen
Many image sensors employ column-parallel ADCs in their readout structures. Single-slope ADCs are ideally suited for these multi-channel applications due to their simplicity, low power and small overall area. The ramp generator, shared by all the converters in the readout architecture, is a key element that has a direct effect in the transfer characteristic of single-slope ADCs. Because a digital counter is inherently present in this conversion scheme, one common practice is to use a digital-to-analog converter driven by the counter to generate the ramp. Given the direct relationship between the DAC and the ADC transfer characteristics, one of the main issues is to ensure a sufficient linearity of the DAC, with special emphasis on its monotonicity. Very often, in particular when medium to high resolutions are aimed, this requires calibration of the DAC, which must be repeated every once in a while to account for temperature, process, power supply, and aging variations. This paper presents an inherently monotonic ramp generator with high levels of linearity and stability against any expected source of variations, combined with a very efficient realization and an inherent automatic adaptability to different resolutions. The ramp generator has been designed using radiation hardening by design (RHBD) techniques, allowing its use in space applications.
SEE Characterization of the AMS 0.35 μm CMOS Technology
J. Ramos-Martos, A. Arias-Drake, J.M. Mora-Gutiérrez, M. Muñoz-Díaz, A. Ragel-Morales, B. Piñero-García, J. Ceballos-Cáceres, L. Carranza-González, S. Sordo-Ibáñez, M.A. Lagos-Florido and S. Espejo-Meana
Conference · European Conference on Radiation and Its Effects on Components and Systems RADECS 2013
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This work presents experimental results for the single-event effects characterization of a commercial (Austria Microsystems) 0.35 ΣΔm CMOS technology. It improves and expands previous results. The knowledge gained is being applied in the development of a RHBD digital library.
Design Methodology and Development of Mixed-Signal ASICs for Space Applications in Standard CMOS Technology
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference · IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2013
resumen
The design of mixed-signal ASICs for on-board space applications can provide several advantages that would not otherwise be possible with discrete components. However, extreme environmental conditions in terms of radiation and temperature imply a detailed knowledge of the technology used while CMOS commercial foundries do not usually have or make available these data. The aim of this work is to overcome these obstacles and offer solutions for space applications based on mixed-signal ASICs in commercial CMOS technologies. This paper presents the methodology followed for the assessment of a commercial (Austria Microsystems, AMS) 0.35 µm CMOS technology and for the development of a radiation hardened by design (RHBD) digital library. In addition, the described methodology has been applied to the development of two mixed-signal ASICs. The first chip performs the function of an optical digital transceiver for diffused-light intra-satellite optical communications. The second one implements a front-end solution for sensor data acquisition and signal conditioning and consists in a set of configurable multi-mode dual slope ADCs with resolution up to 16 bits.
OWLS: A Mixed-Signal Asic for Optical Wire-Less Links in Space Instruments
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, M.A. Lagos-Florido, S. Sordo-Ibáñez, S. Espejo-Meana, I. Arruego, J. Martínez-Oter and M.T. Álvarez
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2012
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This paper describes the design of a mixed-signal ASIC for space application and the techniques employed for radiation
hardening and temperature effects compensation. The work is part of a planned long-term effort and collaboration
between "Instituto de Microelectrónica de Sevilla (IMSE)", "Universidad de Sevilla (US)", and "Instituto Nacional de
Técnica Aeroespacial (INTA)" aimed to consolidate a group of experienced mixed-signal space-ASIC designers.
Evaluation of the AMS 0.35μm CMOS Technology for use in Space Applications
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, M.A. Lagos-Florido, S. Sordo-Ibáñez and S. Espejo-Meana
Conference · Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2012
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The design of mixed-signal application specific integrated circuits (ASICs) requires a detailed knowledge of the
behavior of the technology which exceeds the needs of digital designs. For space applications, with its
extended-temperature and radiation environment, the job of the mixed-signal designer is made even more difficult as in
most cases commercial foundries do not have or make available data on the behavior of their devices under those nonstandard
conditions.
Radiation Characterization of the austriamicrosystems 0.35 μm CMOS Technology
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero.García, M. Muñoz-Díaz, M.A. Lagos-Florido and S. Espejo-Meana
Conference · Conference on Radiation Effects on Components and Systems RADECS 2011
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The design of mixed-signal ASICs for space requires a detailed knowledge of the behaviour of the technology to be used in an environment imposing radiation levels and temperatures beyond those found in standard applications. Commercial foundries providing standard CMOS technologies do not usually have or make available data on the behaviour of their devices under those conditions. Instituto de Microelectrónica de Sevilla and Universidad de Sevilla (IMSE-USE) have started a long term collaboration with the Spanish Instituto Nacional de Técnica Aeroespacial (INTA) to extend its experience on mixed-signal design to the field of ASICs for space applications. The assessment of a commercial (austriamicrosystems) 0.35 μm CMOS technology is a first step towards the development of a mixed-signal design methodology, including an RHBD digital library suitable for use in space
conditions.
A 10 μm Thick Poly-Sige gyroscope processed above 0.35 μm CMOS
A. Scheurle, T. Fuchs, K. Kehr, C. Leinenbach, S. Kronmüller, A. Arias, J. Ceballos, M.A. Lagos, J.M. Mora, J.M. Muñoz, A. Ragel, J. Ramos, S. Van Aerde, J. Spengler, A. Mehta, A. Verbist, B. Du Bois, A. Witvrouw
Conference · IEEE International Conference on Micro Electro Mechanical Systems MEMS 2007
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This paper describes a monolithically integrated omegaz-gyroscope fabricated in a surface-micromaching technology. As functional structure, a 10 μm thick Silicon-Germanium layer is processed above a standard high voltage 0.35 μm CMOS-ASIC. Drive and Sense of the in plane double wing gyroscope is fully capacitively. Measurement of movement is also done fully capacitively in continuous-time baseband sensing. For characterization, the gyroscope chip is mounted on a breadboard with auxiliary circuits. A noise floor of 0.01 degs/sqrt(Hz) for operation at 3 mBar is achieved.
Processing of MEMS Gyroscopes on Top of CMOS ICs
A. Witvrouw, A. Mehta, A. Verbist, B. Du Bois, S. Van Aerde, J. Ramos-Martos, J. Ceballos, A. Ragel, J.M. Mora, M.A. Lagos, A. Arias, J.M. Hinojosa, J. Spengler, C. Leinenbach, T. Fuchs and S. Kronmüller
Conference · IEEE International Solid-State Conference ISSCC 2005
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Integrated 10 μm thick poly-SiGe gyroscopes are processed on top of an 8" standard 0.35 μm CMOS wafer with 5 metal levels by using an advanced plasma-enhanced chemical vapor deposition multi-layer technology. The gyroscopes are free-moving with Q-factors for the drive mode up to 10000 at the pressure of 0.8 mTorr while the CMOS chip is fully functional.
SIGEM, low-temperature deposition of Poly-SiGe MEMs structures on standard CMOS circuits
J. Ramos-Martos, J. Ceballos-Cáceres, A. Ragel-Morales, J.M. Mora-Gutierrez, A. Arias-Drake, M.A. Lagos-Florido, J.M. Muñoz-Hinojosa, A. Mehta, A. Verbist, B. du Bois, K. Kehr, C. Leinenbach, S. Van Aerde, J. Spengler and A. Witvrouw
Conference · Conference on VLSI Circuits and Systems II SPIE 2005
resumen
Fabrication of surface-micromachined structures by a post-processing module above standard IC circuits is an efficient way to produce monolithic microsystems, allowing nearly independent optimization of the circuitry and the MEMS process. However, until now the high-temperature steps needed for deposition of poly-Si have limited its application. SiGeM explores the possibilities offered by the low-temperature (450 degrees C) deposition and structuring of poly-SiGe layers, which is compatible with the temperature budget of fully-processed standard IC wafers. In the SiGeM project several low-temperature deposition methods (CVD, PECVD, LPCVD) were developed, and were evaluated with respect to growth rate and material quality. The interconnection technology to the underlying CMOS circuitry was also developed. The capabilities of this new integration technology will be demonstrated in a monolithic high-performance rate-of-turn sensor, currently considered the most demanding MEMs application in terms of material properties of the structural layer (thickness > 10 mu m, stress gradient < 03MPa/mu m) and signal processing circuitry (capacitance resolution in the aF range, SNR > 110 dB). System partitioning will combine analog and DSP circuit techniques to maximize resolution and stability. Parasitic electrical coupling within different parts of the system has been analyzed, and countermeasures to reduce it have been incorporated in the design. The feasibility of the approach has already been proved by preliminary characterization of working prototypes containing released microstructures deposited on top of preamplifier circuits built on a 0.35 mu m, 5-metal, 2-poly, standard CMOS process from Philips Semiconductors. Resonance frequencies are in good agreement with predictions, and quality factors above 8000 have been obtained at pressures of 0.8 mTorr. Measured SNR confirms the capability to achieve a resolution of 0.015 degrees/s over a bandwidth of 50 Hz.
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