Encontrados resultados para:
Autor: María J. Avedillo de Juan
Año: Desde 2002
Artículos de revistas
A Review of Ising Machines Implemented in Conventional and Emerging Technologies
T. Zhang, Q. Tao, B. Liu, A. Grimaldi, E. Raimondo, M. Jiménez, M.J. Avedillo, J. Núñez, B. Linares-Barranco, T. Serrano-Gotarredona, G. Finocchio and Jie Han
Journal Paper · IEEE Transactions on Nanotechnology (Early Access), 2024
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Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and pase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOSspintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
A CMOS-compatible oscillation-based VO2 Ising machine solver
O. Maher, M. Jiménez, C. Delacour, N. Harnack, J. Núñez, M.J. Avedillo, B. Linares-Barranco, A. Todri-Sanial, G. Indiveri and S. Karg
Journal Paper · Nature Communications vol. 15, article 3334, 2024
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Phase-encoded oscillating neural networks offer compelling advantages over metal-oxide-semiconductor-based technology for tackling complex optimization problems, with promising potential for ultralow power consumption and exceptionally rapid computational performance. In this work, we investigate the ability of these networks to solve optimization problems belonging to the nondeterministic polynomial time complexity class using nanoscale vanadium-dioxide-based oscillators integrated onto a Silicon platform. Specifically, we demonstrate how the dynamic behavior of coupled vanadium dioxide devices can effectively solve combinatorial optimization problems, including Graph Coloring, Max-cut, and Max-3SAT problems. The electrical mappings of these problems are derived from the equivalent Ising Hamiltonian formulation to design circuits with up to nine crossbar vanadium dioxide oscillators. Using sub-harmonic injection locking techniques, we binarize the solution space provided by the oscillators and demonstrate that graphs with high connection density (μ > 0.4) converge more easily towards the optimal solution due to the small spectral radius of the problema’s equivalent adjacency matrix. Our findings indicate that these systems achieve stability within 25 oscillation cycles and exhibit power efficiency and potential for scaling that surpasses available commercial options and other technologies under study. These results pave the way for accelerated parallel computing enabled by large-scale networks of interconnected oscillators.
Experimental Demonstration of Coupled Differential Oscillator Networks for Versatile Applications
M. Jiménez, J. Núñez, J. Shamsi, B. Linares-Barranco and M.J. Avedillo
Journal Paper · Frontiers in Neuroscience, Neuromorphic Engineering, vol. 17, 2023
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Oscillatory Neural Networks (ONNs) exhibit a high potential for energy-efficient computing. In ONNs, neurons are implemented with oscillators and synapses with resistive and/or capacitive coupling between pairs of oscillators. Computing is carried out on the basis of the rich, complex, nonlinear synchronization dynamics of a system of coupled oscillators. The exploited synchronization phenomena in ONNs are an example of fully parallel collective computing.A fast system´s convergence to stable states, which correspond to the desired processed information, enables an energy-efficient solution if small area and low-power oscillators are used, specifically, when they are built on the basis of the hysteresis exhibited by phase-transition materials such as VO2. In recent years, there have been numerous studies on ONNs using VO2. Most of them report simulation results. Although in some cases experimental results are also shown, they don´t implement the design techniques that other works on electrical simulations report that allow to improve the behavior of the ONNs.Experimental validation of these approaches is necessary. Therefore, in this work, we describe an ONN realized in a commercial CMOS technology in which the oscillators are built using a circuit that we have developed to emulate the VO2 device. The purpose is to be able to study in depth the synchronization dynamics of relaxation oscillators similar to those that can be performed with VO2 devices. The fabricated circuit is very flexible. It allows programming the synapses to implement different ONNs, calibrating the frequency of the oscillators or controlling their initialization. It uses differential oscillators and resistive synapses equivalent to the use of memristors. In this article, the designed and fabricated circuit is described in detail and experimental results are shown. Specifically, its satisfactory operation as an associative memory is demonstrated. The experiments carried out allow us to conclude that the ONN must be operated according to the type of computational task to be solved, and guidelines are extracted in this regard.
Learning Algorithms for Oscillatory Neural Networks as Associative Memory for Pattern Recognition
M. Jiménez, M.J. Avedillo, B. Linares-Barranco and J. Núñez
Journal Paper · Frontiers in Neuroscience, Neuromorphic Engineering, vol. 17, 2023
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Alternative paradigms to the von Neumann computing scheme are currently arousing huge interest. Oscillatory neural networks (ONNs) using emerging phase-change materials like VO2 constitute an energy-efficient, massively parallel, brain-inspired, in-memory computing approach. The encoding of information in the phase pattern of frequency-locked, weakly coupled oscillators makes it possible to exploit their rich nonlinear dynamics and their synchronization phenomena for computing. A single fully connected ONN layer can implement an auto-associative memory comparable to that of a Hopfield network, hence Hebbian learning rule is the most widely adopted method for configuring ONNs for such applications, despite its well-known limitations. An extensive amount of literature is available about learning in Hopfield networks, with information regarding many different learning algorithms that perform better than the Hebbian rule. However, not all of these algorithms are useful for ONN training due to the constraints imposed by their physical implementation. This paper evaluates different learning methods with respect to their suitability for ONNs. It proposes a new approach, which is compared against previous works. The proposed method has been shown to produce competitive results in terms of pattern recognition accuracy with reduced precision in synaptic weights, and to be suitable for online learning.
Operating Coupled VO2-based Oscillators for Solving Ising Models
M.J. Avedillo, M. Jiménez, C. Delacour, A. Todri-Sanial, B. Linares-Barranco and J. Núñez
Journal Paper · IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023
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Coupled nano-oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. The potential of phase transition devices for such dynamical systems has recently been recognized. This paper investigates the implementation of coupled VO2-based oscillator networks to solve combinatorial optimization problems. The target problem is mapped to an Ising model, which is solved by the synchronization dynamics of the system. Different factors that impact the probability of the system reaching the ground state of the Ising Hamiltonian and, therefore, the optimum solution to the corresponding optimization problem, are analyzed. The simulation-based analysis has led to the proposal of a novel Second-Harmonic Injection Locking (SHIL) schedule. Its main feature is that SHIL signal amplitude is repeatedly smoothly increased and decreased. Reducing SHIL strength is the mechanism that enables escaping from local minimum energy states. Our experiments show better results in terms of success probability than previously reported approaches. An experimental Oscillatory Ising Machine (OIM) has been built to validate our proposal.
Effect of Device Mismatches in Differential Oscillatory Neural Networks
J. Shamsi, M.J. Avedillo, B. Linares-Barranco and T. Serrano-Gotarredona
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 2, pp 872-883, 2023
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Analog implementation of Oscillatory Neural Networks (ONNs) has the potential to implement fast and ultra-low-power computing capabilities. One of the drawbacks of analog implementation is component mismatches which cause desynchronization and instability in ONNs. Emerging devices like memristors and VO2are particularly prone to variations. In this paper, we study the effect of component mismatches on the performance of differential ONNs (DONNs). Mismatches were considered in two main blocks: differential oscillatory neurons and synaptic circuits. To measure DONN tolerance to mismatches in each block, performance was evaluated with mismatches being present separately in each block. Memristor-bridge circuits with four memristors were used as the synaptic circuits. The differential oscillatory neurons were based on VO2-devices. The simulation results showed that DONN performance was more vulnerable to mismatches in the components of the differential oscillatory neurons than to mismatches in the synaptic circuits. DONNs were found to tolerate up to 20% mismatches in the memristance of the synaptic circuits. However, mismatches in the differential oscillatory neurons resulted in non-uniformity of the natural frequencies, causing desynchronization and instability. Simulations showed that 0.5% relative standard deviation (RSD) in natural frequencies can reduce DONN performance dramatically. In addition, sensitivity analyses showed that the high threshold voltage of VO2-devices is the most sensitive parameter for frequency non-uniformity and desynchronization.
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase
A. Todri-Sanial, S. Carapezzi, C. Delacour, M. Abernot, T. Gil, Elisabetta Corti, S.F. Karg, J. Nüñez, M. Jiménez, M.J. Avedillo and B. Linares-Barranco
Journal Paper · IEEE Transactions on Neural Networks and Learning Systems, vol. 33, no. 5, pp 1996-2009, 2021
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Brain-inspired computing employs devices and architectures that emulate biological functions for more adaptive and energy-efficient systems. Oscillatory neural networks (ONNs) are an alternative approach in emulating biological functions of the human brain and are suitable for solving large and complex associative problems. In this work, we investigate the dynamics of coupled oscillators to implement such ONNs. By harnessing the complex dynamics of coupled oscillatory systems, we forge a novel computation model--information is encoded in the phase of oscillations. Coupled interconnected oscillators can exhibit various behaviors due to the strength of the coupling. In this article, we present a novel method based on subharmonic injection locking (SHIL) for controlling the oscillatory states of coupled oscillators that allow them to lock in frequency with distinct phase differences. Circuit-level simulation results indicate SHIL effectiveness and its applicability to large-scale oscillatory networks for pattern recognition.
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications
M. Abernot, T. Gil, M. Jiménez, J. Núñez, M.J. Avellido, B. Linares-Barranco, T. Gonos, T. Hardelin and A. Todri-Sanial
Journal Paper · Frontiers in Neuroscience, vol. 15, article 713054, 2021
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Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called ‘data deluge gap ’). This has resulted in investigating novel computing paradigms and design approaches at all levels from materials to system-level implementations and applications. An alternative computing approach based on artificial neural networks uses oscillators to compute or Oscillatory Neural Networks (ONNs). ONNs can perform computations efficiently and can be used to build a more extensive neuromorphic system. Here, we address a fundamental problem: can we efficiently perform artificial intelligence applications with ONNs? We present a digital ONN implementation to show a proof-of-concept of the ONN approach of ‘computing-in-phase’ for pattern recognition applications. To the best of our knowledge, this is the first attempt to implement an FPGA-based fully-digital ONN. We report ONN accuracy, training, inference, memory capacity, operating frequency, hardware resources based on simulations and implementations of 5 × 3 and 10 × 6 ONNs. We present the digital ONN implementation on FPGA for pattern recognition applications such as performing digits recognition from a camera stream. We discuss practical challenges and future directions in implementing digital ONN.
Hardware Implementation of Differential Oscillatory Neural Networks using VO2-based Oscillators and Memristor-Bridge Circuits
J. Shamsi, M.J. Avedillo, B. Linares-Barranco and T. Serrano-Gotarredona
Journal Paper · Frontiers in Neuroscience, vol. 15, article 674567, 2021
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Oscillatory Neural Networks (ONNs) are currently arousing interest in the research community for their potential to implement very fast, ultra-low-power computing tasks by exploiting specific emerging technologies. From the architectural point of view, ONNs are based on the synchronization of oscillatory neurons in cognitive processing, as occurs in the human brain. As emerging technologies, VO2 and memristive devices show promising potential for the efficient implementation of ONNs. Abundant literature is now becoming available pertaining to the study and building of ONNs based on VO2 devices and resistive coupling, such as memristors. One drawback of direct resistive coupling is that physical resistances cannot be negative, but from the architectural and computational perspective this would be a powerful advantage when interconnecting weights in ONNs. Here we solve the problem by proposing a hardware implementation technique based on differential oscillatory neurons for ONNs (DONNs) with VO2-based oscillators and memristor-bridge circuits. Each differential oscillatory neuron is made of a pair of VO2 oscillators operating in anti-phase. This way, the neurons provide a pair of differential output signals in opposite phase. The memristor-bridge circuit is used as an adjustable coupling function that is compatible with differential structures and capable of providing both positive and negative weights. By combining differential oscillatory neurons and memristor-bridge circuits, we propose the hardware implementation of a fully connected differential ONN (DONN) and use it as an associative memory. The standard Hebbian rule is used for training, and the weights are then mapped to the memristor-bridge circuit through a proposed mapping rule. The paper also introduces some functional and hardware specifications to evaluate the design. Evaluation is performed by circuit-level electrical simulations and shows that the retrieval accuracy of the proposed design is comparable to that of classic Hopfield Neural Networks.
Insights into the Dynamics of Coupled VO2 Oscillators for ONNs
J. Núñez, J.M. Quintana, M.J. Avedillo, M. Jiménez, A. Todri-Sanial, E. Corti, S. Karg and B. Linares-Barranco
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 10, pp 3356-3360, 2021
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The collective behavior of many coupled oscillator systems is currently being explored for the implementation of different non-conventional computing paradigms. In particular, VO2 based nano-oscillators have been proposed to implement oscillatory neural networks that can serve as associative memories, useful in pattern recognition applications. Although the dynamics of a pair of coupled oscillators have already been extensively analyzed, in this paper, the topic is addressed more practically. Firstly, for the application mentioned above, each oscillator needs to be initialized in a given phase to represent the input pattern. We demonstrate the impact of this initialization mechanism on the final phase relationship of the oscillators. Secondly, such oscillatory networks are based on frequency synchronization, in which the impact of variability is critical. We carried out a comprehensive mathematical analysis of a pair of coupled oscillators taking into account both issues, which is a first step towards the design of the oscillatory neural networks for associative memory applications.
Oscillatory Neural Networks using VO2 based Phase Encoded Logic
J. Núñez, M.J. Avedillo, M. Jiménez, J.M. Quintana, A. Todri-Sanial, E. Corti, S. Karg and B. Linares-Barranco
Journal Paper · Frontiers in Neuroscience, vol. 15, article 655823, 2021
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Nano-oscillators based on phase-transition materials are being explored for the implementation of different non-conventional computing paradigms. In particular, vanadium dioxide (VO 2) devices are used to design autonomous non-linear oscillators from which oscillatory neural networks (ONNs) can be developed. In this work, we propose a new architecture for ONNs in which sub-harmonic injection locking (SHIL) is exploited to ensure that the phase information encoded in each neuron can only take two values. In this sense, the implementation of ONNs from neurons that inherently encode information with two-phase values has advantages in terms of robustness and tolerance to variability present in VO2 devices. Unlike conventional interconnection schemes, in which the sign of the weights is coded in the value of the resistances, in our proposal the negative (positive) weights are coded using static inverting (non-inverting) logic at the output of the oscillator. The operation of the proposed architecture is shown for pattern recognition applications.
Approaching the Design of Energy Recovery Logic Circuits using Tunnel Transistors
J. Núñez and J.M. Avedillo
Journal Paper · IEEE Transactions on Nanotechnology, vol. 19, pp 500-507, 2020
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Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope, and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account that problems associated with the inverse current of their intrinsic p-i-n diode. In this paper, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.
Hybrid Phase Transition FET Devices for Logic Computation
M. Jiménez, J. Núñez and M.J. Avedillo
Journal Paper · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, pp 1-8, 2020
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Hybrid Phase Transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON to OFF current ratio. In this paper, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ONOFF current tradeoffs are evaluated at circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, on the basis of this analysis, the paper proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained which were lower than those achieved with low standby power (LSTP) FinFETs and high performance (HP) FinFETs. The paper also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.
Phase Transition Device for Phase Storing
M.J. Avedillo, J.M. Quintana and J. Núñez
Journal Paper · IEEE Transactions on Nanotechnology, vol. 19, pp 107-112, 2020
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Nano-oscillators based on phase transitions materials (PTM) are being explored for the implementation of different non-conventional computing paradigms. This paper describes the capability of such autonomous non-linear oscillators to store phase-encoded information. A latch based in sub-harmonic injection locking using an oscillator composed of a PTM device and a transistor is described. Resistive coupling is used to inject both a required synchronization signal and the input to be stored. Operation of the proposed latch implementation, the embedding of functionality into the latch and its application to frequency division are illustrated and validated by simulation.
Power and Speed Evaluation of Hyper-FET Circuits
J. Núñez and M.J. Avedillo
Journal Paper · IEEE Access, vol. 7, pp 6724-6732, 2019
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Many emerging devices are currently being explored as potential alternatives to complementary metal-oxide-semiconductor (CMOS) technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at circuit level. In this paper, we investigate the speed and power performance of Hyper-Field Effect Transistor (Hyper-FET) circuits, comparing them with both high-performance (HP) and low stand-by power (LSTP) Fin-Shaped Field Effect Transistor (FinFET) designs on the same technology node. The evaluation, which was carried out at gate and circuit level, includes characterization of 8 bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from transistor and gate level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated which support the obtained results.
Phase Transition FETs for Improved Dynamic Logic Gates
M.J. Avedillo, M. Jiménez and J. Núñez
Journal Paper · IEEE Electron Device Letters, vol. 39, no. 11, pp 1776-1779, 2018
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Transistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. In addition to the replacement of the transistors in conventional static CMOS logic circuits, the distinguishing features of Phase Change FETs can be exploited in other application domains or can be useful for solving specific design challenges. In this paper, we take advantage of them to implement a smart dynamic gate in which undesirable contention currents are reduced, leading to speed advantage without power penalties.
Impact of the RT-level architecture on the power performance of tunnel transistor circuits
M.J. Avedillo and J. Núñez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 46, no. 3, pp 647-655, 2018
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Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer-level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.
Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
J. Nuñez and M.J. Avedillo
Journal Paper · IEEE Journal of the Electron Devices Society, vol. 5, no. 6, pp 530-534, 2017
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RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this paper, we analyze the limitations of typical TFET rectifier topologies associated with the forward biasing of their intrinsic diode and show that this can occur at relatively weak input signals depending on the specific characteristic of the used tunnel device. We propose a simple modification in the implementation of the rectifiers to overcome this problem. The impact of our proposal is evaluated on the widely used gate cross-coupled topology. The proposed designs exhibit similar peak PCE and sensitivity but significantly improve PCE for larger input signal amplitude and larger input power.
Insights into the Operation of Hyper-FET-Based Circuits
M.J. Avedillo and J. Nuñez
Journal Paper · IEEE Transactions on Electron Devices, vol. 64, no. 9, pp 3912-3918, 2017
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Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the I-ON/I-OFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called hyper-FET to simulate different circuits, and to analyze the impact of the degraded dc output voltage levels of hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements. We show that these estimations can reduce, cancel, or even lead to power penalties in low switching and/or low-frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design.
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
J. Núñez and M.J. Avedillo
Journal Paper · IEEE Transactions on Nanotechnology, vol. 16, no, 1, pp 83-89, 2017
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Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four MOSFET and FinFET transistors. The impact of logic depth, switching activity and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
J. Núñez and M.J. Avedillo
Journal Paper · IEEE Transactions on Electron Devices, vol. 63, no. 12, pp 5012-5020, 2016
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In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas.
Improving speed of tunnel FETs logic circuits
M.J. Avedillo and J. Núñez
Journal Paper · Electronics Letters, vol. 51, no. 21, pp 1702-1704, 2015
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Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital tunnel FET circuits leading to delay degradation. A minor modification of the complementary gate topology to avoid the bootstrapping problem is proposed and its impact on speed at the circuit level is shown. Speed improvements up to 33% have been obtained for 8-bit ripple carry adders when implemented with the solution.
Experimental validation of a two-phase clock scheme for fine-grained pipelined circuits based on monostable to bistable logic elements
J. Nuñez, M.L. Avedillo and J.M. Quintana
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp 2238-2242, 2014
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Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating two series connected negative differential resistance devices with a clock bias. This brief describes and experimentally validates a two-phase clock scheme for such MOBILE-based ultragrained pipelines. Its advantages over other reported interconnection schemes for MOBILE gates, and also over pure CMOS two-phase counterparts, are stated and analyzed. Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE circuit to have been reported with this interconnection architecture.
Novel pipeline architectures based on Negative Differential Resistance devices
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper · Microelectronics Journal, vol. 44, no. 9, pp 807-813, 2013
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Devices exhibiting Negative Differential Resistance (NDR) in their I-V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.
Two-phase RTD-CMOS pipelined circuits
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper · IEEE Transactions on Nanotechnology, vol. 11, no. 6, pp 1063-1066, 2012
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MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have been reported using different clock schemes including a four-phase strategy and a single-phase clock scheme. In particular, significant power advantages of single-phase RTD-CMOS MOBILE circuits over pure CMOS have been shown. This letter compares the RTD-CMOS realizations using a single clock and a novel two-phase clock solution. Significant superior robustness and performance in terms of power and area are obtained for the two-phase implementations.
Domino inspired MOBILE networks
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper · Electronics Letters, vol. 48, no. 5, pp 292-293, 2012
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MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported that alternates rising and falling edge-triggered MOBILE gates. A novel two-phase interconnection scheme resembling conventional domino pipelines is proposed and validated. It exhibits advantages in terms of speed with respect to both four-phase and single-phase interconnection schemes. In addition, the new architecture improves logic flexibility regarding the domino pipeline counterpart, since inverting and non-inverting stages can be interspersed.
RTD-CMOS pipelined networks for reduced power consumption
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper · IEEE Transactions on Nanotechnology, vol. 10, no. 6, pp 1217-1220, 2011
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The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work in this direction is required. In this letter, we compare RTD-CMOS and pure CMOS realizations of a logic gate network which can be operated in a gate-level pipeline. Significantly lower average power is obtained for RTD-CMOS implementations.
Simplified single-phase clock scheme for MOBILE networks
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper · Electronics Letters, vol. 47, no. 11, pp 648-649, 2011
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MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required for this. A single-phase scheme is possible adding latches to the MOBILE gates. Proposed and experimentally validated is a new single-phase interconnection scheme that simplifies the inter-stage element, which translates in power, area and clock load advantages with respect to using latches.
Improved nanopipelined RTD adder using generalized threshold gates
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Journal Paper · IEEE Transactions on Nanotechnology, vol. 10, no. 1, pp 155-162 2011
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Many logic circuit applications of resonant tunneling diodes are based on the monostable-bistable logic element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e., these circuits are built from threshold gates (TGs). This paper describes the design of full adders (FAs), using TG-based circuit topologies. Both the selection of different MOBILE TG networks and the use of gates that can be considered extensions of the MOBILE TG are addressed. The FAs are applied to the design of nanopipelined carry propagations adders, which are evaluated and compared to a previously reported one, showing advantages in terms of speed, power, and power-delay product.
Efficient realisation of MOS-NDR threshold logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper · Electronics Letters, vol. 45, no. 23, pp 1158-1159, 2009
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A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.
Operation limits for RTD-based MOBILE circuits
J.M. Quintana, M.J. Avedillo, J. Nuñez and H.P. Roldan
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 2, pp 350-363, 2009
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Resonant-tunneling-diode (RTD)-based MOnostable-BIstable Logic Element (MOBILE) circuits operate properly in a certain frequency range. They exhibit both a minimum operating frequency and a maximum one. From a design point of view, it should be desirable to have gates with a correct operation from do up to the maximum operating frequency (i.e., without the minimum bound). This paper undertakes this problem by analyzing how transistors and RTDs interact in RTD-based circuits. Two malfunctions have been identified: the incorrect evaluation of inputs and the lack of self-latching operation. The difficulty to study these problems in an analytical way has been overcome by resorting to series expansions for both the RTD and the heterojunction field-effect transistor I-V characteristics in the points of interest. We have obtained analytical expression linking representative device parameters and technological setup, for a MOBILE-based circuit to operate correctly.
Single phase clock scheme for mobile logic gates
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Journal Paper · Electronics Letters, vol. 42, no. 24, pp 1382-1383, 2006
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Many logic circuit applications of resonant tunnelling diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Cascaded MOBILE gates are operated in a pipelined fashion using a four phase overlapping clocking scheme. To improve the robustness of MOBILE networks, a simpler clock scheme is desirable. It is demonstrated that a network of MOBILE gates can be operated with a single clocked bias signal. Both schemes are compared.
Increased logic functionality of clocked series-connected RTDS
M.J. Avedillo, J.M. Quintana and H.P. Roldan
Journal Paper · IEEE Transactions on Nanotechnology, vol. 5, no. 5, pp 606-611, 2006
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The augmentation of transistor technologies with resonant tunnelling diodes (RTDs) has demonstrated improved circuit performance. The negative differential resistance exhibited by these devices can be exploited to increase the functionality implemented by a single gate in comparison to transistor-only technologies. Complex threshold gates (TGs) are efficiently realized by resorting to the operation principle of the clocked series connection of a pair of RTDs (MOBILE). This paper focuses the implementation of logic blocks using RTDs and transistors which further increase the functionality of previously reported topologies. Multithreshold-threshold gates (MTTGs) is the logic concept underlying the proposed realizations. The MOBILE principle is extended to three or more RTDs in series which allows us to implement MTTGs. Novel and extremely compact realizations of programmable gates using the MTTG topology are presented. A number of logic blocks useful for digital design are shown and their operation is verified through simulation with extensively validated models for actual devices.
Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors
M.J. Avedillo, J.M. Quintana and H. Pettenghi
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 5, pp 334-338, 2006
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One of the most attractive features of MOBILE-based circuits is their self-latching operation, which allows pipelining at the gate level, and thus very high through-output, without any area overhead associated to the addition of the latches. However, the self-latching behavior is not inherent to the practical circuit topologies employed to implement MOBILE circuits. This paper reports on very simple MOBILE structures supporting this statement. The analysis performed is useful in extracting design guidelines to guarantee the required behavior.
Analysis of frequency divider RTD circuits
J.M. Quintana and M.J. Avedillo
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 10, pp 2234-2247, 2005
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The behavior of a novel circuit topology able to implement a frequency divider is studied. This circuit is composed of a resonant tunnelling diode (RTD), an inductor, and a capacitor, so it exhibits a very high operating frequency and low power consumption. It employs the peRíod-adding sequences which appear in its bifurcation diagram to perform the frequency division. Compared to a previously reported similar circuit, it has wider operation windows and a higher division factor for the driver frequency, while maintaining the extremely high operating frequency, its simplicity, and the division factor tunability through the selection of circuit parameters. Simulation results using the HSPICE RTD model from project LOCOM as well as several realistic parasitics elements are given, which confirm the theoretical capabilities previously analyzed.
Transistor critical sizing in MOBILE follower
J.M. Quintana and M.J. Avedillo
Journal Paper · Electronics Letters, vol. 41, no. 10, pp 583-584, 2005
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Analyses are presented of how the presence of the HFET transistor modifies the DC operation of a resonant tunnelling logic follower MOBILE. The difficulty of an analytical study for the resulting circuit has been overcome by resorting to simplified descriptions for both the RTD and the HFET I-V characteristics. We have obtained an analytical expression for the relation of the ratio of gate width to the gate length of the HFET below which a theoretically well designed follower does not operate correctly.
A practical parallel architecture for stacks filters
M.J. Avedillo, J.M. Quintana, H. El Alami and A. Jiménez-Calderón
Journal Paper · Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, vol. 38, no. 2, pp 91-100, 2004
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Stack filters belong to the class of non-linear filters and include the well-known median filter, weighted median filters, order statistic filters and weighted order statistic filters. Any stack filter can be implemented by using the parallel threshold decomposition architecture which allows implementing their non-linear processing by means of a collection of identical binary filters (Boolean logic circuits). Although it is conceptually simple and useful to study the filter properties, this architecture is not practical for direct hardware implementation because as many as (M-1) binary filters are required for a M-valued input signal and M is large in many applications. In this paper we introduce a new parallel architecture for stack filter implementations. The complexity is now proportional to the window width L of the filter, instead of to M. In most applications L is much smaller than M which translates into efficient hardware implementations. The attractive characteristic of ease of design exhibited by the threshold decomposition architecture is kept. In fact, for a given stack filter both in the conventional implementation and in the proposed one, the same binary filter is required. The key concept supporting the new architecture is a modified decomposition scheme which generates L binary signals for a multi-valued input. As an application example, a complex WOS filter is designed and prototyped in an FPGA.
Pass-transistor based implementations of threshold logic gates for WOS filtering
M.J. Avedillo, J.M. Quintana and R. Jiménez-Naharro
Journal Paper · Microelectronics Journal, vol. 35, no. 11, pp 869-873, 2004
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This paper presents a systematic procedure to implement threshold functions by using a pass-transistor network. A main feature of the threshold gates (TGs) produced by this technique is that they do not exhibit the fan-in limitations usual when other implementation techniques are used. Thus, they are especially useful for Weighted Order Statistical (WOS) filters because the binary filters required are threshold functions which usually present a high total sum of weights. A WOS filter with its binary filters implemented as pass-transistor TGs is demonstrated in an standard 0.35 mum CMOS technology at 3.3 V. The filter shows a sample frequency well over 100 MHz at the nominal process condition and it is cheaper, faster and consumes less power than a conventional approach. (C) 2004 Elsevier Ltd. All rights reserved.
Nonlinear dynamics in frequency divider RTD circuits
J.M. Quintana and M.J. Avedillo
Journal Paper · Electronics Letters, vol. 40, no. 10, pp 586-587, 2004
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A novel and extremely compact circuit topology able to implement a selectable frequency divider using the peRíod-adding sequences which appear in the bifurcation diagram for the circuit is presented. It is based on resonant tunnelling devices (RTDs), so allowing very high operating frequency and a low power consumption. Compared to a previous similar reported circuit, it has wider operation windows, narrower chaos regions and a higher division factor.
Weighted order statistics filter for real-time signal processing applications based on pass transistor logic
M.J. Avedillo, J.M. Quintana and H. El Alami
Journal Paper · IEEE Proceedings-Circuits Devices and Systems, vol. 151, no. 1, pp 31-36, 2004
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The authors describe the rationale of the design of complex weighted order statistics filters (WOS filters) suitable for real-time signal processing applications. It is based on a simple stack-like architecture that decomposes the M-valued signals into a reduced number of binary signals which are filtered by identical boolean logic circuits (binary filters). The main distinguishing feature of the proposed procedure is the efficient implementation of both the decomposition stage and the binary filters. The former is achieved on the basis of introducing a new decomposition scheme which can be economically translated to hardware. The latter comes from realising that the binary filters required for WOS filtering are threshold functions and from the development of a systematic methodology for building pass-transistor networks that implement them. Results for a complex example filter show a sample frequency of over 175 MHz in a 0.35 mum MOS technology at 3.3 V.
Simplified Reed-Muller expressions for residue threshold functions
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Journal Paper · Circuits Systems and Signal Processing, vol. 23, no.1, pp 45-56, 2004
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Residue threshold functions are a broad class of symmetric functions that include all the unit-weighted threshold functions. In this paper, we investigate the complexity of the Reed-Muller (RM) expressions for these functions. We prove that an important subclass of the functions has very simple RM expansions and determine the conditions that define such a subclass. Additionally, we show that such an expansion is also the optimal one concerning its polarity. As an interesting practical application, an analysis of the RM expansion of the output functions for parallel counters is performed.
VLSI implementations of threshold logic - A comprehensive survey
V. Beiu, J.M. Quintana and M.J. Avedillo
Journal Paper · IEEE Transactions on Neural Networks, vol. 14, no. 5, pp 1217-1243, 2003
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This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.
Multi-threshold threshold logic circuit design using resonant tunnelling devices
M.J. Avedillo, J.M. Quintana, H. Pettenghi, P.M. Kelly and C.J. Thompson
Journal Paper · Electronics Letters, vol. 39, no. 21, pp 502-1504, 2003
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A novel and extremely compact circuit topology able to implement a gencralised threshold logic function with two thresholds is presented. The circuit consists of resonant tunnelling diodes and heterostructure field effect transistors.
COPAS: A new algorithm for the partial input encoding problem
M. Martinez, M.J. Avedillo, J.M. Quintana and J.L. Huertas
Journal Paper · VLSI Design, vol. 14, no. 2, pp 171-181, 2002
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Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols should be chosen to optimize the final implementation. Conventionally, this input encoding (IE) problem has been solved in a two-step process. First step generates constraints on the relationship between codes for different symbols, called group constraints. In a following step, symbols are encoded such that constraints are satisfied. This paper addresses the partial input encoding problem (PIE), a variation of the IE problem which generates codes of minimum length. The role of group constraints within the framework of the PIE problem has been questioned. This paper describes an algorithm that unlike conventional approaches, which try to maximize the number of satisfied constraints, targets the economical implementation of each input constraint. The proposed approach is based on a powerful heuristic that produces high quality results in shorter time compared to previous algorithm.
Congresos
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices
J. Núñez, M.J. Avedillo and M. Jiménez
Conference · International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2023
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Abstract not available
Energy-efficient Brain-inspired Oscillatory Neural Networks using Phase-Transition Material
M. Jiménez, B. Linares-Barranco, M.J. Avedillo and J. Núñez
Conference · Workshop on Deep Learning meets Neuromorphic Hardware. European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases ECML PKDD 2023
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Oscillatory Neural Network (ONN) is a promising neuromorphic computing approach which uses networks of frequency-locked coupled oscillators, and their inherent parallel synchronization to compute. Also, ONN can be im-plemented using phase-transition materials using nano-scale area, low voltage amplitude and reduced power consumption, being an efficient way to im-plement oscillator-based computing. In state-of-theart, ONN is built with a fully-connected architecture, with coupling configured depending on the tar-get application. Its most widespread use has been as associative memory, but recently it is gathering interest as a solver for non-deterministic polynomial time problem (NP-hard). This is performed on the basis of encoding the NP-problem in the Ising model, so ONN operates as an Ising machine. ONN state naturally evolves to minimum points in the Hamiltonian energy function re-sorting to its rich non-lineal dynamics, supposing a promising paradigm of fast, low-power, parallel computation.
Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks
M. Jiménez, J. Núñez, J. Shamsi, B. Linares-Barranco and M.J. Avedillo
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
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The utilization of phase-transition materials-based nano-oscillators is being investigated to apply various non-traditional computing paradigms. Specifically, vanadium dioxide (VO2) devices are used to design self-sustained non-linear oscillators that can be employed for oscillatory neural networks (ONNs). In addition, in these ONN architectures sub-harmonic injection locking (SHIL) can be exploited to ensure that each neuron's phase information can only adopt one of two possible values. An integrated circuit demonstrator of an analog 9-neuron ONN using a deep-submicron commercial technology have been designed and fabricated. The oscillators forming the neurons closely resemble those designed using VO2 devices. The capability of the fabricated ONN to work as an associative memory has been tested. An example of two store patterns has been used to show that the ONN successfully stores the two patterns and exhibits the associative memory functionality.
Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
M. Jiménez, M.J. Avedillo, B. Linares-Barranco and J. Núñez
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
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Alternative paradigms to the von Neumann computing scheme are currently arousing huge interest. Oscillatory neural networks (ONNs) using emerging phase-change materials constitute an energy-efficient, massively parallel, brain-inspired, in-memory computing approach. The encoding of information in the phase pattern of frequency-locked, weakly coupled oscillators makes it possible to exploit their rich nonlinear dynamics and their synchronization phenomena for computing. A single fully connected ONN layer can implement an auto-associative memory comparable to that of a Hopfield network. Hebbian learning rule is the most widely adopted method for configuring ONNs for such applications, despite its well-known limitations. Other approaches that perform better than the Hebbian rule are not useful for ONN training due to the constraints imposed by its physical implementation. This paper proposes a new approach and compares it with previous work. The proposed method has been shown to produce competitive results in terms of pattern recognition accuracy with reduced precision in synaptic weights, and to be suitable for online learning.
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory
M. Jiménez, M.J. Avedillo, J. Núñez and B. Linares-Barranco
Conference · XXXVII Conference on Design of Circuits and Integrated Systems DCIS 2022
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Solving Combinatorial Optimization Problems with Coupled Phase Transition based Oscillators
J. Núñez, M.J. Avedillo and M. Jiménez
Conference · XXXVII Conference on Design of Circuits and Integrated Systems DCIS 2022
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Abstract not available
Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications
J. Núñez, S. Thomann, H. Amrouch and M.J. Avedillo
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2022
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Coupled oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. Coupled nano-oscillator implementations using emerging devices have arisen, but the immaturity of these technologies has allowed only simple experimental demonstrations. The potential of Negative Capacitance FET (NCFET) for such applications has recently been recognized, which is a step towards the physical realization given their ease of co-integration with commercial CMOS technologies. However, the design of circuits using these devices can be seriously compromised by the variability inherent in them. In this paper, we will highlight this problem through the design of an oscillatory neural network for pattern recognition applications. We propose the application of subharmonic injection mechanisms to mitigate the impact of NCFET transistor variability and present results showing that the performance of these circuits improves significantly.
Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4
M. Abernot, T. Gil, E. Kurylin, T. Hardelin, A. Magueresse,T. Gonos, M. Jiménez-Través, M.J. Avedillo de Juan and A. Todri-Sanial
Conference · IEEE International Joint Conference on Neural Networks IJCNN 2022
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Neuromorphic computing aims to emulate biological neural functions to overcome the memory bottleneck challenges with the current Von Neumann computing paradigm by enabling efficient and low-power computations. In recent years, there has been a tremendous engineering effort to bring neuromorphic computing for processing at the edge. Oscillatory Neural Networks (ONNs) are braininspired neural networks made of oscillators to mimic neuronal brain waves, typically visible on Electroencephalograms (EEG). ONNs provide massive parallelism using coupled oscillators and low power computation using oscillator phase dynamics. In this paper, we present for the first time how to use ONNs to perform obstacle avoidance on a mobile robot. Digitally implemented ONNs on FPGA are used and configured for obstacle avoidance inside the industrial surveillance robot E4 from the company, A.I.Mergence. We show that ONNs can perform real-time obstacle avoidance based on the sensory data from proximity sensors embedded on the E4 robot. The highly parallel architecture of ONNs not only allows fast real-time computation for obstacle avoidance applications but also opens up a novel computing paradigm for edge AI to enable low power and real-time sensing to action computing.
FeFETs for Phase Encoded Oscillatory based Computing
J. Núñez, M. Jiménez, B. Linares-Barranco and M.J. Avedillo
Conference · Design, Automation and Test in Europe DATE 2022
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Coupled nano-oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. The potential of Ferroelectric Field-Effect Transistor (FeFET) for such applications has recently been recognized, which is a step towards the physical realization given their ease of cointegration with commercial CMOS technologies. This paper investigates the design of oscillators using FeFETs and their potential for oscillator-based computing in which information is encoded in phase. As applications, we present the operation of FeFET coupled oscillators systems for graph coloring and Max-Cut problems, including subharmonic injection mechanism to discretize the phase in the second one.
FeFETs for Phase Encoded Oscillatory based Computing
J. Nunez, M. Jimenez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2021
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Coupled oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. Coupled nano-oscillator implementations using emerging devices have arisen, but the immaturity of these technologies has allowed only simple experimental demonstrations. The potential of Ferroelectric Field-Effect Transistor (FeFET) for such applications has recently been recognized, which is a step towards the physical realization given their ease of cointegration with commercial CMOS technologies. This paper investigates the design of oscillators using FeFETs and their potential for oscillatory-based computing (OBC) in which information is encoded in phase. After analyzing the FeFET-based oscillator, the operation of an Oscillatory Hopfield Neural Network (OHNN) for image classification applications in a 2x2 size example is illustrated. Finally, it is shown that this type of oscillator can also be combined with a subharmonic injection mechanism to discretize the phase as it is required in coupled oscillator’s networks for solving combinatorial optimization problems.
An Approach to the Device-Circuit Co-Design of HyperFET Circuits
M. Jiménez, J. Núñez and M.J. Avedillo
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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In this paper, we describe device-circuit co-design experiments for Hybrid Phase Transition FETs (HyperFETs). HyperFET transistors, built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON current without triggering the OFF current. This enables reducing supply voltage and so power consumption. HyperFETs with different ON-OFF currents tradeoffs are analyzed. Inverter chains and ring oscillators built with them are evaluated in terms of power and compared to reference designs using FETs alone. Power reductions up to 32% are shown for a HyperFET with similar OFF current and higher ON current than its FET counterpart when nodes frequently switch. However, power penalties by a factor of 400 have been obtained for other simulation stimuli. Our results identify switching activity as critical for obtaining power savings and suggest guidance both at device and circuit level to take full advantage of these devices.
Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks
J. Shamsi, M.J. Avedillo and B. Linares-Barranco
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
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Hebbian rule plays an important role in training of artificial neural networks. According to this rule, a synaptic weight between two neurons is increased or decreased depending on the activity of the presynaptic and postsynaptic neurons. In this paper, an oscillatory version of the Hebbian rule is proposed for ONNs and is called Oscillatory Hebbian Rule (OHR). OHR simply expresses the weight change as a function of the phase difference between the presynaptic and postsynaptic neurons. Similar to STDP that weight change is an exponential function of the time difference between the presynaptic and postsynaptic spikes, OHR relates weight change to the phase difference between the presynaptic and postsynaptic neurons using exponential functions. Specifically, when two neurons are in-phase, the weight between them is increased while a weight between two anti-phase neurons is decreased. Simulation results show the capability of OHR for both supervised and unsupervised learning. In supervised learning, a basic block of feedforward architectures is trained as a classifier. When the basic block is used in unsupervised mode, it is capable to learn patterns while the output phase is converged to a specific phase.
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits
J. Núñez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
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Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope (SS), and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account the problems associated with their inverse current due to their intrinsic p-i-n diode. In this paper, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially at medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits, both at gate and architecture levels, with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.
Device circuit co-design of HyperFET transistors
J. Núñez, M. Jiménez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
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In this paper, we describe device-circuit co-design experiments for Hybrid Phase Transition FETs (HyperFETs). HyperFET transistors, built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON current without triggering the OFF current. This enables reducing supply voltage and so power consumption. HyperFETs with different ON-OFF currents tradeoffs are analyzed. Inverter chains and ring oscillators built with them are evaluated in terms of power and compared to reference designs using FETs alone. Power reductions up to 50% are shown for a HyperFET with similar OFF current and higher ON current than its FET counterpart when nodes frequently switch. However, power penalties by a factor of 80 have been obtained for other simulation stimuli. Our results identify switching activity as critical for obtaining power advantages from the supply voltage reduction permitted by HyperFETs, and suggest guidance both at device and circuit level to take full advantage of these devices.
Device Circuit Co-Design of HyperFET Transistors
J. Núñez and M.J. Avedillo
Conference · International Forum on Information Systems and Technologies INFOS 2019
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In this paper, we describe a device-circuit codesign experiment for Hybrid Phase Transition FETs (HyperFETs) transistors. Inverter chains and ring oscillators are evaluated using three HyperFETs devices. Our results suggest guidance for device design to avoid known power penalty mechanisms at the circuit level.
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jimenez, M.J. Avedillo and J. Núñez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
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Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.
Exploring Logic Architectures Suitable for TFETs Devices
J. Núñez and M.J. Avedillo
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
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Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are critical for IoT development. Although they show higher ON currents than CMOS at low supply voltages, currently TFETs do not reach those exhibited by CMOS at its nominal supply voltage and so they have being identified to be competitive for moderate operating frequencies. However, in many cases, architectural choices are not taken into account when benchmarking them against CMOS. In this paper we claim that the logic architecture should be selected in order to take full advantage of the specific characteristics of these devices. Widely used circuits are designed and evaluated showing how properly tuning the logic architecture results in raising the frequency up to which TFETs are competitive or in increasing power savings at lower frequencies.
Complementary Tunnel Gate Topology to Reduce Crosstalk Effects
J. Núñez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
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Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated.
Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits
M.J. Avedillo and J. Núñez
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2016
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Tunnel transistors are one of the most attractive steep sub threshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, we analyze the impact of the logic depth into the power consumption and energy efficiency of logic circuits and show critical differences between tunnel transistors and CMOS technologies, due to the distinct delay versus supply voltages exhibited by each type of device. Obtained results show that reducing logic depth as a power reduction technique is more efficient for tunnel transistors circuits than for their CMOS counterparts. A simple model to estimate the power reductions achieved when using pipeline to cut down logic depth, and taking into account the power overheads associated to the pipelined registers is developed. It shows that in CMOS power benefits cancels with the incorporation of a number of flip-flops equal to the 5% of the number of gates in the original circuit while this number rises to 90% for tunnel circuits. Simulation experiments of a simple adder tree are carried out to validate our analysis. No power savings are obtained by the CMOS pipelined circuit while the TFET pipelined circuit saves 77% of power. The results of this work suggest that architectural issues should be considered in the evaluation of this type of transistors.
Experiencia en desarrollo de sistemas empotrados hardware-software como Trabajo Fin de Grado
J.M. Calahorro, L. Acasandrei, A. Barriga and M.J. Avedillo
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
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Se presenta en esta comunicación el desarrollo de un Trabajo Fin de Grado (TFG) de la Titulación de Ingeniería Informática-Ingeniería de Computadores. El objetivo es mostrar la experiencia en el desarrollo de un TFG que aúne aspectos multidisciplinares, que permitan desarrollar en el alumno las capacidades adquiridas durante el proceso educativo en el Grado en Ingeniería de Computadores. En concreto se plantea la especificación de un sistema empotrado hardware-software dentro del campo de aplicación del reconocimiento de caras en imágenes y/o video, competitivo en términos de velocidad respecto a una implementación puramente software.
Hardware-Software Embedded Face Recognition System
M.J. Avedillo, A. Barriga, L. Acasandrei and J.M. Calahorro
Conference · International Conferences in Central Europe on Computer Graphics, Visualization and Computer Vision WSCG 2016
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This paper describes the design and implementation of a hardware-software embedded system for face recognition applications in images and/or videos. The system has hardware components to speed up the face detection and recognition stages. It is a system suitable for applications requiring real-time, due that the response times are deterministic and bounded. The system is based on a previous implementation that had accelerated the image capturing process, and the face detection. This paper will focuses in the face recognition acceleration.
Assessing application areas for tunnel transistor technologies
M.J. Avedillo and J. Núñez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
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Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.
Improving robustness of dynamic logic based pipelines
H.J. Quintero, M.J. Avedillo and J. Núñez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
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Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the non-inverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its non-inverting feature.
DOE Based High-Performance Gate-Level Pipelines
J. Núñez, M.J. Avedillo and H.J. Quintero
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2014
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Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the noninverting behavior of domino gates, there are also performance disadvantages when compared to inverting dynamic gates, which can be related to this feature. These penalties rise from the fact that in order to produce a logic one, a non-inverting gate requires one or more of its inputs to be also at logic one. We analyze the operation of gate-level pipelines implemented with domino and with Delayed Output Evaluation (DOE), an inverting dynamic gate we have recently proposed, and compare their performance. Using domino and DOE gates similar in terms of delay, improvements in operating frequencies around 50% have been obtained by the DOE pipelines.
Novel dynamic gate topology for superpipelines in DSM technologies
J. Nuñez, M.J. Avedillo and J.M. Quintana
Conference · Euromicro Conference on Digital System Design DSD 2013
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Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high throughput. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and the Carry-Merge chain of a Kogge-Stone adder is designed as an application example.
Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications
J. Núñez, M.J. Avedillo, J.M. Quintana and H.J. Quintero
Conference · Conference on the Design of Circuits and Integrated Systems DCIS 2013
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Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high through-output. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and a gate per phase Carry Look Ahead adder is designed as an application example.
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J. Nuñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an 'all MOS' version of one previously reported which uses Resonant Tunneling Diodes (RTDs). The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications
J. Núñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2012
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Monostable to Bistable (MOBILE) gates are very suitable for the implementation of gate-level pipelines which can be achieved without resorting to memory elements. MOBILE operating principle is implemented using two series connected Negative Differential Resistance (NDR) devices with a clocked bias. This paper describes and experimentally validates a two-phase clock scheme for such MOBILE based ultra-grain pipelines. Up to our knowledge it is the first MOBILE working circuit reported with this interconnection architecture. The proposed interconnection architecture is applied to the design of a 4-bit Carry Look-ahead Adder.
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J. Núñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference · Iberchip XVIII Workshop IWS 2012
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The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an ¿all MOS¿ version of one previously reported which use Resonant Tunneling Diodes (RTDs) The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.
Compact and Power Efficient MOS-NDR Muller C-Elements
J. Núñez-Martínez, M. J. Avedillo and J.M. Quintana-Toledo
Conference · IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems DoCEIS 2012
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Recently there is a renewed interest in the development of transistor circuits which emulate the Negative Differential Resistance (NDR) exhibited by different emerging devices like Resonant Tunneling Diodes (RTDs). These MOS-NDR circuits easily allow the prototyping of design concepts and techniques developed for such NDR devices. The importation of those concepts into transistor technologies can result in circuit realizations which are advantageous for some functionalities and application fields. This paper describes a Muller C-element which illustrates this statement which is inspired in an RTD-based topology. The required RTD is implemented by means of the MOS-NDR device. A 4-input Muller C-element has been fabricated and experimentally validated. The proposed circuit compares favorably with respect to a well-known conventional gate realization.
Efficient realization of RTD-CMOS logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference · Great Lakes Symposium on VLSI GLSVLSI 2011
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The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined. Lower average power and energy per cycle are obtained for RTD/CMOS implementations. Copyright © 2011 by ASME.
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs
J. Nuñez, M.J. Avedillo and J.M. Quintana
Conference · SPIE Microtechnologies for the New Millennium 2011
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The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. We compare RTD-CMOS and pure CMOS realizations of a network of logic gates which can be operated in a gate-level pipeline. Significant lower average power is obtained for RTD-CMOS implementations.
Redes MOBILE MOS-NDR operando con reloj de una fase
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference · Iberchip XVI Workshop IWS 2010
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La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative Differential Resistance, NDR) resulta atractiva desde el punto de vista del diseño de circuitos, como ha sido demostrado por los circuitos que usan diodos basados en el efecto túnel resonante (Resonant Tunneling Diodes, RTDs). Ideas procedentes de diseños con RTDs pueden exportarse a un entorno 'todo CMOS' en el que la característica NDR se obtiene mediante transistores (MOS-NDR). En este artículo se proponen estructuras MOS-NDR para realizar puertas lógicas (Threshold Gates, TGs) que operan según el principio de operación MOBILE (MOnostable to BIstable Logic Element). Además, se demuestra que estas puertas pueden interconectarse para formar redes que operan en modo pipeline usando un esquema de reloj de una fase.
Evaluation of RTD-CMOS logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference · Euromicro Conference on Digital System Design DSD 2010
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The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined fashion, thus allows estimating logic networks operating frequency. Lower power-delay products are obtained for RTD/CMOS implementations. © 2010 IEEE.
An improved RNS generator 2 n ± k based on threshold logic
H. Pettenghi, R. Chaves, L. Sousa and M.J. Avedillo
Conference · IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2010
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This paper presents a new scheme for designing residue generators using threshold logic. This approach is based on the periodicity of the series of powers of 2 taken modulo 2 n± k. In addition, a new algorithm is proposed to obtain a new set of partitions which are more advantageous in terms of area and delay for the presented topology. Experimental results in the analized range of k and n show that new proposed circuits using the novel partitioning are 70% faster and provide area savings of 64%, when compared with similar circuits using the partitioning methods presented to date. © 2010 IEEE.
Single phase MOS-NDR mobile networks
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
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Devices with an I-V characteristic exhibiting Negative Differential Resistance (NDR) are attractive from the circuit design point of view as it has been demonstrated by Resonant Tunneling Diodes (RTDs) circuits. Ideas coming from RTD-based designs can be exported to an "all CMOS" environment by using transistor circuits to generate the NDR characteristic (MOS-NDR). In this paper novel programmable MOS-NDRs are proposed and used to realize threshold logic gates on the basis of the MOnostable to BIstable Operating principle. It is shown that these gates can be connected to build up networks that are operated in a pipelined fashion using a single phase clock scheme.
Fast and area efficient multi-input Muller C-element based on MOS-NDR
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2009
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A new multi-input Muller C-element based on a MOS-NDR device is proposed in this contribution. This design overcomes some drawbacks of previously proposed structures. A comparison in terms of area, delay and power consumption over another efficient CMOS Muller C-element circuit has been performed, resulting that our structure improves this performance.
Transient Response in MOBILE-based Circuits
J.M. Quintana and M.J. Avedillo
Conference · IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2008
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Abstract not avaliable
RTD based Logic Circuits using Generalized Threshold Gates
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference · IEEE Conference on Design of Circuits and Integrated Systems DCIS 2008
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Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates (TGs). The MOBILE realization of generalized threshold gates is being investigated. Multi-Threshold Threshold Gates (MTTGs) have been proposed which further increase the functionality of the original TGs. Recently, we have proposed a novel MOBILE circuit topology obtained by fundamental properties of threshold functions. This paper describes the design of n-bit adders using these novel MOBILE circuit topologies. A comparison with designs based on TGs and MTTGs is carried out showing advantages in terms of speed and power delay product and device counts.
Observation of Frequency Division and Chaos Behavior in a Laser Diode
B. Romeira, J.M.L. Figueiredo, T.J. Slight, L. Wang, E. Wasige, C.N. Ironside, J.M. Quintana and M.J. Avedillo
Conference · Conf. on Lasers and Electro-Optics/Quantum Electronics and Laser Science CLEO/QELS 2008
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We report optical experimental frequency division and chaos results in a resonant tunneling diode laser diode driver configuration that forms a self-oscillating circuit. Circuit behavior and laser output results are well predicted using Lienardpsilas equation.
Analysis of the critical rise time in MOBILE-based circuits
J.M. Quintana and M.J. Avedillo
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2008
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It is well known that there is a critical value for the rising time of the clocked bias signal which limits the operating speed of MOBILE-based circuits. This paper analyzes the transient response of a MOBILE-based follower and obtains analytical expressions to calculate the critical value for the rising time of the bias signal below which the circuit does not operate correctly. This analysis has been extended to more complex circuits such as threshold gates, we have also derived operating speed limits for these circuits. Results obtained have been validated through extensive simulations with HSPICE. © 2008 IEEE.
Design of RTD-based NMIN/NMAX gates
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE Conference on Nanotechnology, IEEE-NANO 2008
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A novel implementation of NMIN/NMAX gates based on RTDs and transistors is presented. In this paper we will derive the relations that circuit representative parameters must verify to obtain a correct behaviour by means of the principles of the Monostable-to-Multistable Logic (MML). HSPICE simulations will be used to check our theoretical results. © 2008 IEEE.
Synchronisation and chaos in a laser diode driven by a resonant tunnelling diode
B. Romeira, J.M.L. Figueiredo, T.J. Slight, L. Wang, E. Wasige, C.N. Ironside, J.M. Quintana and M.J. Avedillo
Conference · Conference on Semiconductor Integrated Optoelectronics SIOE 2008
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The authors report on a hybrid integration of a resonant tunnelling diode laser diode driver configuration that can operate as a self-oscillating circuit, and when externally perturbed shows regions of frequency division and frequency multiplication, quasi-peRíodic and chaotic oscillations, both in the optical and electrical outputs. The authors also demonstrate that this optoelectronic circuit is well described as a Lienard's oscillator. The synchronisation capabilities of the circuit have potentially novel functions for optical communications systems including clock recovery, clock division and data encryption.
Limits to a correct operation in RTD-based ternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2008
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.
A novel contribution to the RTD-based threshold logic family
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference · International Symposium on Circuits and Systems ISCAS 2008
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Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates. More recently, generalized threshold gates, also suitable to be realized with MOBILE RTD structures, are being investigated. In this paper we propose a novel MOBILE circuit topology obtained by exploiting threshold logic concepts and properties. A comparison in terms of speed and power performance between the proposed topologies and previous reported ones is carried out.
Limits to a correct evaluation in RTD-based quaternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · International Symposium on Multiple-Valued Logic ISMVL 2007
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML quaternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.
A quasi-differential quantizer based on SMOBILE
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2007
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A quasi-differential quantizer based on a Symmetric-MOBILE (SMOBILE) configuration is proposed and compared to traditional structures based on MOBILE. This novel structure is adequate for high frequency operation since it can operate at a double clock-rate. A previous analysis before any frequency study should be done in order to obtain the correct operation region. In this paper, this region is analyzed for the proposed quantizer and it is compared to the corresponding ones based on MOBILE. The obtained results show that the correct operation regions are very similar, thus the advantages regarding to the operation frequency make our proposal very attractive.
Operation limits in RTD-based ternary quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · Great Lakes Symposium on VLSI GLSVLSI 2007
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary quantizer, and determines the relations that circuit representative parameters must verify to obtain a correct DC operation.
Holding preserving in RTD-based multiple-valued quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE Conference on Nanotechnology IEEE-NANO 2007
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are of the basis of advanced circuits for communications. The operation of a quantizer has two steps: sampling and holding. Once the quantizer samples the signal, it must maintain the sampled value even if the input changes. However, holding property is not inherent to RTD-based MML circuit topologies. A procedure to obtain the relation between circuit parameters in order to achieve a correct operation is described.
Correct operation in SMOBILE-based quasi-differential quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · European Conference on Circuit Theory and Design ECCTD 2007
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A quasi-differential quantizer based on a Symmetric-MOBILE (SMOBILE) configuration is proposed and compared to traditional structures based on MOBILE. This novel structure is adequate for high frequency operation since it can operate at a double clock-rate. A previous analysis before any frequency study should be to obtain the correct operation region. In this paper, this region is analyzed for the proposed quantizer and it is compared to the corresponding based on MOBILE. The obtained results show that the correct operation regions are very similar, thus the advantages regarding to the operation frequency make our proposal very attractive.
Non return mobile logic family
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference · International Symposium on Circuits and Systems ISCAS 2007
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Many logic circuit applications of RTDs are based on the MOnostable-BIstable Logic Element (MOBILE). Cascaded MOBILE gates are operated in a pipelined fashion using a four phase overlapping clocking scheme. To improve the robustness of MOBILE networks, a simpler clock scheme is desirable. We have demonstrated that removing the return to a "precharge" voltage behaviour of conventional MOBILE gates, operation with a single phase clock scheme is possible. In this paper, a non return MOBILE logic family is described and its single phase operation shown. A comparison between return and non return gates is carried out showing that in addition to the simpler clock scheme required, speed and power-delay product improvements can be achieved with the proposed ones.
Correct DC operation in RTD-based ternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE International Conference of Nano/Micro Engineered and Molecular Systems IEEE-NEMS 2007
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.
Operation limits for MOBILE followers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE Conference on Nanotechnology IEEE-NANO 2006
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This paper analyses how the presence of the HFET transistor modifies the DC operation of a Resonant Tunneling Logic Follower MOBILE, and can prevent its correct operation. The difficulty of an analytical study for the resulting circuit has been overcome by resorting to series expansions for both the RTD and the HFET I-V characteristics in the points of interest. We have obtained analytical expressions describing the regions where a MOBILE follower operates correctly. © 2006 IEEE.
Monostable-bistable transition logic elements: Threshold logic vs. boolean logic comparison
D. Bol, J.D. Legat, J.M. Quintana and M.J. Avedillo
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2006
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Threshold logic is an interesting alternative to Boolean logic in the field of high-performance arithmetic circuits. It offers reduced logic depth and gate count. A competitive implementation of threshold logic uses MOnostable-BIstable transition Logic Elements (MOBILE). The aim of this contribution is to evaluate a specific implementation of MOBILE based on Negative-Differential-Resistance (NDR) MOS structures. This implementation is compared as fairly as possible to Boolean-logic circuits. Simulations of majority-voting gates with 1 to 7 inputs are carried out using the same CMOS process for both logic styles. Results show the improvement brought by the MOBILE implementation regarding to area, power consumption and power-delay product, when the number of inputs becomes large. © 2006 IEEE.
Limits to a correct evaluation in RTD-based ternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2006
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a correct DC evaluation is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct operation.
Design guides for a correct DC operation in RTD-based threshold gates
J.M. Quintana, M.J. Avedillo and J. Núñez
Conference · Conference on Digital System Design - Architectures, Methods and Tools EUROMICRO 2006
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A correct DC operation is essential before analyzing other aspects of the circuit behavior. This paper analyzes how the presence of the HFET transistor modifies the DC operation of follower circuits based on MOBILE, and can prevent its correct operation. On the basis of this analysis, guidelines for the design of threshold gates which are implemented as a generalization of the follower circuit topology are derived.
Self-latching operation limits for MOBILE circuits
J.M. Quintana, M.J. Avedillo and H. Pettenghi
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2006
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One of the most attractive feature of MOBILE-based circuits is their self-latcbing operation, which allows pipelining at the gate level, and thus very high tbrough-output, without any area overhead associated to the addition of the latches. However, the self-latching behavior is not inherent to the practical circuit topologies employed to implement MOBILE circuits. This paper reports on very simple MOBILE structures supporting this statement. The analysis performed allow extracting design guidelines to guarantee the required behavior.
DC correct operation in MOBILE inverters
J.M. Quintana, M.J. Avedillo and J. Núñez
Conference · IEEE International Midwest Symposium on Circuits and Systems MWSCAS 2006
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The verification of an appropriate DC behavior is essential before analyzing other aspects of the operation of a circuit. This paper analyses the case of MOBILE inverters and determines the relations that circuit representative parameters (such as the relation of the ratio of gate width to the gate length of the HFET, and the area factors in the RTDs) must verify to obtain a MOBILE inverter which operates correctly. The difficulty of an analytical study has been overcome by resorting to series expansions for both the RTD and the HFET I-V characteristics in the points of interest, so obtaining simplified descriptions for describing these behaviors.
Holding Dissapearance in RTD-based Quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference · European Nano Systems Worshop ENS 2005
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Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. The operation of such quantizer has two steps : sampling and holding. Once the quantizer samples the signal, it must maintain the sampled value even if the input changes. However, holding property is not inherent to MML circuit topologies. This paper analyses the case of an MML ternary inverter used as a quantizer, and determines the relations that circuit representative parameters must verify to avoid this malfunction.
New circuit topology for logic gates based on RTDs
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference · IEEE Conference on Nanotechnology IEEE-NANO 2005
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The augmentation of transistor technologies with Resonant Tunnelling Diodes (RTDs) has demonstrated improved circuit performance and it has been claimed that it could be the way to extend lifetime of current technologies. Thus the research on circuit topologies using RTDs and transistors is of critical importance for these emergent technologies. In particular, threshold logic gates (TGs) and multi threshold gates (MTTGs) have been efficiently implemented. In this Letter we propose a novel circuit topology to implement MTTGs which exhibits advantages in terms of speed and power consumption with respect to a previously reported circuit. A comparison between both topologies is carried out for an useful logic block: a gate which simultaneously implements the EXOR and the NAND functions. ©2005 IEEE.
Using multi-threshold threshold gates in RTD-based logic design: A case study
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference · European Nano Systems Worshop ENS 2005
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The basic building blocks for resonant tunneling diode (RTD) logic circuits are threshold gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, TGs can be implemented as efficiently as conventional ones, but realize more complex functions. Recently, RTD structures implementing multi-threshold threshold gates (MTTGs) have been proposed which further increase the functionality of the original TGs while maintaining their operating principle and allowing also the implementation of nanopipelining at the gate level. This paper describes the design of n-bit adders using these MTTGs. A comparison with a design based on TGs is carried out showing advantages in terms of power consumption and power delay product. (C) 2007 Elsevier Ltd. All rights reserved.
Novel improved RTD-based implementation of multi-threshold logic gates
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference · International Conference on PhD Research in Microelectronics and Electronics PRIME 2005
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The augmentation of transistor technologies with Resonant Tunnelling Diodes (RTDs) has demonstrated improved circuit performance and it has been claimed that it could be the way to extend lifetime of current technologies. Thus the research on circuit topologies using RTDs and transistors is of critical importance for these emergent technologies. In particular, threshold logic gates (TGs) and multi threshold gates (MTTGs) have been efficiently implemented. In this paper we propose a novel circuit topology to implement MTTGs which exhibits advantages in terms of speed and power consumption with respect to the previously reported circuit. A comparison between both topologies is carried out for an useful logic block: a gate which simultaneously implements the EXOR and the NAND functions.
Logic models supporting the design of MOBILE-based RTD circuits
M.J. Avedillo,J.M. Quintana and H. Pettenghi
Conference · IEEE International Conference on Application-Specific Systems, Architecture and Processors ASAP 2005
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Threshold logic is a computational model widely used in the design of Resonant Tunnelling Diodes (RTDs) based circuits, i.e. these circuits are built from threshold gates. This paper explores two other computational models, Generalized Threshold Gates (GTG) and Multi-Threshold Threshold Gates (MTTGs), also suitable to be realized with MOBILE based RTD structures. Circuits implementing them are described Both logic models are generalizations of threshold logic and so the proposed circuit topologies further increase the functionality of the original TGs. Implementations of a non threshold function with the GTG and MTTG topologies are shown and compared.
Robust frequency divider based on resonant tunneling devices
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2005
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The behaviour of a novel and extremely compact resonant tunnelling diode (RTD)-based circuit able to implement a frequency divider is studied. It exhibits very high operating frequency and low power consumption. Compared to a previous similar reported circuit, it has wider operation windows, narrower quasi-peRíodicity regions and an higher division factor for the driver frequency, while maintaining the extremely high operating frequency, simplicity, and division factor tunability by selection of circuit parameters.
Useful logic blocks based on clocked series-connected RTDs
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference · IEEE Conference on Nanotechnology IEEE-NANO 2004
resumen
This paper presents novel and extremely compact implementations, based of the multi-threshold threshold gate concept, for some useful building blocks for logic design. The circuits consist of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs). They can be used in nanopipelined architectures enabling high frequency operation of systems.
A threshold logic synthesis tool for RTD circuits
M.J. Avedillo and J.M. Quintana
Conference · Symposium on Systems on Digital System Design EUROMICRO 2004
resumen
Functional devices and circuits based on Resonant Tunnelling Diodes (RTDs) are receiving much attention since they allow high speed and/or low power operation. RTDs exhibit a negative differential resistance in their current-voltage characteristic which can be exploited to significantly increase the functionality implemented by a single gate in comparison to other technologies. In particular they have proven to efficiently implement threshold gates which are a generalization of conventional boolean gates. Suitable logic synthesis tools are required to handle these complex building blocks in order to translate the advantages of this emergent technology to the circuit and system levels. This paper describes an efficient approach to the automatic design of networks of threshold gates from functional specifications. Results for widely used logic functions and standard benchmark circuits are reported.
Programmable logic gate based on resonant tunneling devices
J.M. Quintana, M.J. Avedillo and H. Pettenghi
Conference · International Symposium on Circuits and Systems ISCAS 2004
resumen
This paper presents a novel and extremely compact circuit able to implement a two-input programmable gate on the basis of the multi-threshold threshold gate concept. The circuit consists of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs). We provide detailed analysis on circuit design and simulation of such a programmable gate.
RTD-based compact programmable gates
J.M. Quintana, M.J. Avedillo and H. Pettenghi
Conference · IEEE International Joint Conference on Neural Networks IJCNN 2004
resumen
This paper presents novel and extremely compact implementations of programmable gates on the basis of the multi-threshold threshold gate concept. The circuit consists of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs) and its operating principle is based on the controlled quenching of clocked series-connected RTDs. The proposed generic circuit topology is presented and the methodology to design specific programmable gates is introduced. A number of programmable gates are shown and their operation is validated.
Design of residue generators using threshold logic
J.M. Quintana, M.J. Avedillo and H. Pettenghi
Conference · International Midwest Symposium on Circuits and Systems MWSCAS 2003
resumen
A new design for residue generators modulo 3 is presented. It resorts to the potential of the computational model which uses threshold gates to significantly reduce both the complexity and depth of the resulting circuit.
A LP-LV high performance monolitic DTMF receiver with on-chip test facilities
D. Vázquez, G. Huertas, M.J. Avedillo, J.M. Quintana, A. Rueda and J.L. Huertas
Conference · Conference on VLSI Circuits and Systems 2003
resumen
This paper presents a mixed-signal DTMF receiver implemented in a double-poly double-metal 0.6um technology able to operate in the range of 2.7V-5V of voltage supply with a low current consumption (<1mA). An smart digital detector and decoder algorithm provides a very good speech immunity. On-chip test facilities for the analog part have.. been incorporated into the chip. A modified opamp (called sw-opamp) has been used to provide external accessing to inputs and outputs of the main analog blocks for off-line testing purposes. The so-called Oscillation-Based-Test (OBT) has also been integrated to perform a structural testing of the analog part. The additional cost of such on-chip test facilities is very small: just one extra pin and an area overhead of around 7%. Experimental results demonstrate the good performance of the design and the feasibility of the testing approaches.
Review of capacitive threshold gate implementations
V. Beiu, M.J. Avedillo and J.M. Quintana
Conference · Joint Int. Conf. on Artificial Neural Networks ICANN 2003/Int. Conf. on Neural Inf. Processing ICONIP 2003
resumen
This is an in-depth survey paper on capacitive hardware implementations of threshold logic gates. The different VLSI solutions include the switched capacitor and the floating gate and their variations. It will be shown how the distinct original proposals from both categories have evolved to become quite similar. The problems with this kind of implementations are pointed out, and their applications are discussed.
Threshold-logic-based design of compressors
J.M. Quintana, M.J. Avedillo, E. Rodríguez-Villegas and A. Rueda
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
resumen
The design of efficient compressor circuits is a key problem in the design of high-performance applications where the impact of carry propagation must be reduced as much as possible. Examples of application for these compressors extend from arithmetic units such as parallel multipliers to high-performance, high-capacity digital neural networks (DNNs). This paper proposes new, threshold logic based, compressors to improve the delay in the critical signal path. Optimal design of such compressors has been addressed in both logical and electrical directions and our results show that such compressors have the best performance in delay and power-delay product when compared to conventional implementations.
Simplified Reed-Muller expressions for residue threshold functions
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
Residue threshold functions are a broad class of boolean functions which includes all the unit-weighted threshold functions. In this Paper we investigate the complexity of the Reed-Muller (RM) expressions for these functions. We prove that an important subclass of them have very simple RM expansions and determine the conditions that define it. As an interesting practical application, we show that the output functions of parallel counters belong to this subclass.
Simple parallel weighted order statistic filter implementations
M.J. Avedillo, J.M. Quintana and E. Rodríguez-Villegas
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
This paper describes a simple parallel architecture for the implementation of Weighted Order Statistic Filters (WOS), an important class of digital non-linear filters. The new architecture combines the design easiness of stack architectures with the area efficiency of those based in ordering matrices. It decomposes the M-valued signals into a reduced number of binary signals which are filtered by identical boolean logic circuits. Both area-efficient and fast implementations are obtained straight-forward from filter specifications. The design of a complex WOS filter is described. Results show a sample frequency over 60 Mhz in a 0.35mum MOS technology.
An encoding technique for low power CMOS implementations of controllers
M. Martínez, M.J. Avedillo, J.M. Quintana, M. Koegst, S. Rulke and H. Susse
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2002
resumen
Power consumption is becoming one of the most critical parameters in VLSI design. In this paper we describe a novel state assignment algorithm targeting towards low power CMOS realizations of controllers. The main features of the new approach can be summarized as follows: 1) flexible column encoding strategy which allows handling the area and the register activity cost functions separately and 2) preliminary analysis of the FSM to control relative weight of each cost function. Experimental results show that on average there is a 25% reduction in power consumption compared to an standard tool and without area penalty.
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Analytic Approach to the Operation of RTD Ternary Inverters Based on MML
J. Núñez, J.M. Quintana and M.J. Avedillo
Book Chapter · Cutting Edge Nanotechnology, pp 97-112, 2010
resumen
doi pdf
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaMultiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.
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