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Autor: Carlos Fernández García
Año: Desde 2002
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Congresos
Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
resumen
doi
This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.
Implementación hardware de un algoritmo ligero de cifrado
C. Fernández-García, V. Zúñiga-Ginzález, A. Casado-Galán, E. Tena-Sácnhez, F.E. Potestad-Ordóñez and C.J. Jiménez-Fernández
Conference · IX Jornadas de I+D+i & 1st International Workshop on STEM
resumen
Abstract not available
Desarrollo de setup experimental para la realización de cartografía EM en sistemas criptográficos
A. Casado-Galán, V. Zúñiga-González, F.E. Potestad-Ordóñez, C. Fernández-García, C.J. Jiménez- Fernández and E. Tena-Sácnhez
Conference · IX Jornadas de I+D+i & 1st International Workshop on STEM
resumen
El objetivo de la criptografía es garantizar la confidencialidad, integridad y disponibilidad de la información. En los dispositivos electrónicos, protegemos la información por medio de algoritmos criptográficos. Estos transforman la secuencia mediante operaciones matemáticas en diversas iteraciones haciendo que la información sea, con la potencia computacional de la que disponemos actualmente, imposible de recuperar sin conocer una determinada clave. Si bien teóricamente estos algoritmos son seguros, la implementación en circuitos electrónicos abre la puerta a vulnerabilidades que se pueden explotar para obtener información sobre el mensaje cifrado. Midiendo, por ejemplo, la emisión electromagnética (EM) de un circuito con instrumental apropiado para ello y tenemos un modelo matemático de este lo suficientemente preciso, podemos hackear el dispositivo y obtener la clave o mensaje cifrado. Este trabajo se centra en el desarrollo experimental de un setup de medida para realizar la cartografía EM de los sistemas criptográficos. Esto permite determinar los puntos de máxima emisión de información atacable. El setup experimental propuesto está totalmente automatizado desde un PC, donde con una mesa XY y el posicionamiento fijo de la sonda EM se puede barrer el área completa del dispositivo bajo test y capturar la emisión EM en cada punto.
Review of Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA
F.E. Potestad-Ordoñez, E. Tena-Sánchez, C. Fernández-García, V. Zúñiga-González, J.M. Mora Gutiérrez, C. Baena-Oliva, P. Parra-Fernández, A.J. Acosta-Jiménez and C.J. Jiménez-Fernández
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen
In this paper, we present a review of the work [1]. In this work a complete setup to break ASIC implementations of standard Trivium stream cipher was presented. The setup allows to recover the secret keys combining the use of the active noninvasive technique attack of clock manipulation and Differential Fault Analysis (DFA) cryptanalysis. The attack system is able to inject transient faults into the Trivium in a clock cycle and sample the faulty output. Then, the internal state of the Trivium is recovered using the DFA cryptanalysis through the comparison between the correct and the faulty outputs. The secret key of the Trivium were recovered experimentally in 100% of the attempts, considering a real scenario and minimum assumptions.
[1] F.E. Potestad-Ordoñez, M. Valencia-Barrero, C. Baena-Oliva, P. Parra-Fernández, C.J. Jiménez-Fernández, "Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA". In Sensors, vol. 20, num. 6909, pp. 1-19, 2020.
Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
E. Tena-Sánchez, F.E. Potestad-Ordoñez, V. Zúñiga-González, C. Fernández-García, J.M. Mora Gutiérrez, C.J. Jiménez-Fernández and A.J. Acosta-Jiménez
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen
In this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of proposals have been presented to design circuits resistant to Power Analysis attacks. In this paper a deep review of the state of the art of gate-level countermeasures against Power Analysis attacks has been done, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison.
[1] E. Tena-Sánchez, F.E. Potestad-Ordoñez, C.J. Jiménez-Fernández, A.J. Acosta and R. Chaves, "Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks," Applied Sciences, 12(5), 2390, 2022.
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