Publicaciones del IMSE

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Autor: Charanraj Mohan
Año: Desde 2002

Artículos de revistas

Neuromorphic Low-power Inference on Memristive Crossbars with On-chip Offset Calibration
C. Mohan, L.A. Camuñas-Mesa, J.M. de la Rosa, E. Vianello, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · IEEE Access, vol. 9, pp 38043-38061, 2021
resumen      doi      

Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired neuromorphic circuits. One drawback of OxRAM based neuromorphic systems is the relatively low ON resistance of OxRAM synapses (in the range of just a few kilo-ohms). This requires relatively large currents (many micro amperes per synapse), and therefore imposes strong driving capability demands on peripheral circuitry, limiting scalability and low power operation. After learning, however, a read inference can be made low-power by applying very small amplitude read pulses, which require much smaller driving currents per synapse. Here we propose and experimentally demonstrate a technique to reduce the amplitude of read inference pulses in monolithic neuromorphic CMOS OxRAM-synaptic crossbar systems. Unfortunately, applying tiny read pulses is non-trivial due to the presence of random DC offset voltages. To overcome this, we propose finely calibrating DC offset voltages using a bulk-based three-stage on-chip calibration technique. In this work, we demonstrate spiking pattern recognition using STDP learning on a small 4x4 proof-of-concept memristive crossbar, where on-chip offset calibration is implemented and inference pulse amplitude could be made as small as 2mV. A chip with pre-synaptic calibrated input neuron drivers and a 4x4 1T1R synapse crossbar was designed and fabricated in the CEA-LETI MAD200 technology, which uses monolithic integration of OxRAMs above ST130nm CMOS. Custom-made PCBs hosting the post-synaptic circuits and control FPGAs were used to test the chip in different experiments, including synapse characterization, template matching, and pattern recognition using STDP learning, and to demonstrate the use of on-chip offset-calibrated low-power amplifiers. According to our experiments, the minimum possible inference pulse amplitude is limited by offset voltage drifts and noise. We conclude the paper with some suggestions for future work in this direction.


Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices
C. Mohan, L.A. Camuñas-Mesa, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020

The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired neuromorphic systems. Large-scale neuromorphic hardware platforms are being developed with increasing number of neurons and synapses, having a critical bottleneck in the online learning capabilities. Spike-timing-dependent plasticity (STDP) is a widely used learning mechanism inspired by biology which updates the synaptic weight as a function of the temporal correlation between pre- and post-synaptic spikes. In this work, we demonstrate experimentally that binary stochastic STDP learning can be obtained from a memristor when the appropriate pulses are applied at both sides of the device.

Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020

Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages-coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.


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