Encontrados resultados para:
Autor: Rafael Castro López
Año: Desde 2002
Artículos de revistas
A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs
F. de los Santos-Prieto, F.J. Rubio-Barbero, R. Castro-López, E. Roca and F.V. Fernández
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers (Early Access), 2024
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Silicon Physical Unclonable Functions (PUFs) have emerged as a promising solution for generating cryptographic keys in low-cost resource-constrained devices. A PUF is expected to be reliable, meaning that its response bits should remain consistent each time the corresponding challenges are queried. Unfortunately, the stability of these challenge-response pairs (CRPs) can be seriously eroded by environmental factors like temperature variations and the aging of the integrated circuits implementing the PUF. Several approaches, including bit masking, bit selection techniques, and error-correcting codes, have been proposed to obtain a reliable PUF operation in the face of temperature variations. As for aging, a new kind of aging-resilient silicon PUF has been reported that uses the time-varying phenomenon known as Random Telegraph Noise (RTN) as the underlying entropy source. Although this type of PUF preserves its reliability well when aged, it is not immune to the impact of temperature variations. The work presented here shows that it is possible to improve the thermal reliability of RTN-based PUFs with a proper combination of (a) a novel optimization-based bit selection technique, that is also applicable to other types of PUFs based on differential measurements; and (b) a temperature-aware tuning of the entropy-harvesting function.
Reliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of aging
A. Santana-Andreo, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · AEU - International Journal of Electronics and Communications, Volume 176, 155147, 2024
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Physical Unclonable Functions (PUFs) have gained attention as a lightweight hardware security primitive. In particular, the SRAM-based PUF uses the unpredictable power-up value of the cells within an SRAM. Although these values should ideally be always the same within each SRAM to accomplish a correct PUF operation, this is often not the case, especially when factors like circuit aging are considered. While certain studies explore the effects of aging on SRAM PUFs, they often simplify the analysis. For instance, some studies assume that only Bias Temperature Instability (BTI) contributes to circuit degradation while others evaluate the overall degradation without accounting for the stochastic effects of aging on each individual cell. In this work, we first perform a detailed characterization of the nature of aging in SRAM PUFs, demonstrating that the impact of Non-Conductive Hot-Carrier Injection cannot be neglected. We also show that different cells degrade differently, highlighting the importance of accounting for the stochasticity of aging. After that, a method based on the Data Retention Voltage metric to select the cells with the most stable power-up response is introduced. Using these cells to generate the PUF identifier will result in a more stable response, and thus a better PUF performance.
PACOSYT: A Passive Component Synthesis Tool based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs
F. Passos, N. Lourenço, E. Roca, R. Martins, R. Castro-López, N. Horta and F.V. Fernández
Journal Paper · IEEE Journal of Microwaves, first online, 2023
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In this paper, the application of regression-based supervised machine learning (ML) methods to the modeling of integrated inductors and transformers is examined. Different ML techniques are used and compared to improve accuracy. However, it is demonstrated that none of the ML techniques considered provided good results unless a smart modeling strategy, tailored to the specific design problem, is used. Taking advantage of these modeling strategies, high accuracy can be obtained when compared to full-wave electromagnetic (EM) simulations (less than 2% error) and experimental measurements (less than 5% error). The most accurate model, obtained by the appropriate combination of an ML technique and modeling strategy, has been integrated into a tool called PACOSYT. The tool uses optimization algorithms to allow the designer to obtain an inductor/transformer with optimal performances in just seconds while keeping the accuracy of EM simulations. Furthermore, the tool provides the passive component S parameter description file for seamless use in circuit simulations. The tool can be used standalone or integrated with design frameworks, like Cadence Virtuoso or AIDASoft, a framework for circuit optimization. To illustrate the different usages of the tool, several passive devices are synthesized, and hundreds of millimeter-wave power amplifiers are synthesized using AIDASoft together with PACOSYT. The tool has been developed using open-source Python frameworks and does not use any closed-source licenses. PACOSYT, which also allows other designers to create their models for different technologies, is made publicly available.
Addressing a New Class of Multi-Objective Passive Device Optimization for Radiofrequency Circuit Design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper · Electronics, vol. 11, no. 16, article 2624, 2022
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The design of radiofrequency circuits and systems lends itself to multi-objective optimization and the bottom-up composition of Pareto-optimal fronts. Conventional multi-objective optimization algorithms can effectively attain these fronts, which maximize or minimize a set of competing objective functions of interest. However, some of these real-life optimization problems reveal a non-conventional feature: there is one objective function that calls neither for minimization nor maximization. Instead, using the Pareto front demands this objective function to be swept across so that all its feasible values are available. Such a non-conventional feature, as shown here, emerges in the case of inductor optimization. The problem thus turns into a non-conventional one: determining how to find uniformly distributed feasible values of this function over the broadest possible range (typically unknown) while minimizing or maximizing the remaining competing objective functions. An NSGA-II-inspired algorithm is proposed that, based on the dynamic allocation of objective function slots and a modified dominance definition, can successfully return sets of solutions for inductor optimization problems with one sweeping objective. Furthermore, a mathematical benchmark function modeling this kind of problem is presented, which is also used to exhaustively test the proposed algorithm and obtain insight into its parameter settings.
Determination of the Time Constant Distribution of a Defect-Centric Time-Dependent Variability Model for Sub-100-nm FETs
P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Journal Paper · IEEE Transactions on Electron Devices, vol 69, no. 10, pp 5424-5429, 2022
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The origin of some time-dependent variability phenomena in FET technologies has been attributed to the charge carrier trapping/detrapping activity of individual defects present in devices. Although some models have been presented to describe these phenomena from the so-called defect-centric perspective, limited attention has been paid to the complex process that goes from the experimental data of the phenomena up to the final construction of the model and all its components, specifically the one that pertains to the time constant distribution. This article presents a detailed strategy aimed at determining the defect time constant distribution, specifically tailored for small area devices, using data obtained from conventional characterization procedures.
On the impact of the biasing history on the characterization of Random Telegraph Noise
P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 71, article 2003410, 2022
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Random Telegraph Noise is a time-dependent variability phenomenon that has gained increased attention during the last years, especially in deeply-scaled technologies. In particular, there is a wide variety of works presenting different techniques designed to analyze current traces in scaled FET devices displaying Random Telegraph Noise, and others focused on modeling the phenomenon using the parameters extracted through such techniques. However, very little attention has been paid to the effects that the biasing conditions of the transistors prior to the measurements may have on the extraction of the parameters that characterize this phenomenon. This paper investigates how these biasing conditions actually impact the extracted results. Specifically, it is demonstrated that the results obtained when Random Telegraph Noise is measured immediately after the device is biased may lead to an overestimation of the Random Telegraph Noise impact with respect to situations in which the device has been previously biased for some time. This fact is, first, presented from a theoretical point of view, and, after, demonstrated experimentally through measurements obtained from a CMOS-transistor array.
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs
A. Santana-Andreo, P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · Integration, vol. 85, pp 1-9, 2022
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PUFs based on the power-up values of an array of SRAM cells are a popular solution to provide secure and low-cost key generation suitable for IoT devices. However, SRAM cells do not always power up to the same value due to external factors like noise, temperature, or aging. This results in a decrease of reliability for the SRAM PUF, an issue generally solved by employing complex Error Correction Codes (ECCs). However, ECCs significantly increase the cost of the complete system. A way to alleviate this issue is the use of bit selection methods, which increase the reliability of the SRAM PUF by using only the power-up values of the most reliable cells (i.e., the SRAM cells that consistently power up to the same value). In this work, the reduction in ECC complexity through a bit selection method based on the Data Retention Voltage metric is demonstrated.
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs
A. Canelas, F. Passos, N. Lourenço, R. Martins, E. Roca, R. Castro-Lopez, N. Horta and F.V. Fernandez
Journal Paper · IEEE Access, vol. 9, pp 124152-124164, 2021
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This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances’ calculation aims for the highest possible accuracy. A surrogate model calculates the performances for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical simulator calculates circuit- and system-level performances. Yield is calculated using Monte-Carlo (MC) analysis with the foundry-provided models without any model approximation. The computation of the circuit yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational requirements during the optimization. The yield of the elements not accurately evaluated is assigned using their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the methodology proposed in this work is compared against other methodologies that do not consider yield throughout the system’s complete hierarchy, demonstrating that it is necessary to consider it over the entire hierarchy to achieve robust optimal designs.
Unified RTN and BTI statistical compact modeling from a defect-centric perspective
G. Pedreira, J. Martin-Martinez, P. Saraza-Canflanca, R. Castro-Lopez, R. Rodriguez, E. Roca, F.V. Fernandez and M. Nafria
Journal Paper · Solid-State Electronics, vol. 185, article 108112, 2021
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In nowadays deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented. The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.
Statistical Characterization of Time-Dependent Variability Defects using the Maximum Current Fluctuation
P. Saraza-Canflanca, J. Martin-Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, F.V. Fernandez and M. Nafria
Journal Paper · IEEE Transactions on Electron Devices, vol. 68, no. 8, pp 4039-4044, 2021
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This article presents a new methodology to extract, at a given operation condition, the statistical distribution of the number of active defects that contribute to the observed device time-dependent variability, as well as their amplitude distribution. Unlike traditional approaches based on complex and time-consuming individual analysis of thousands of current traces, the proposed approach uses a simpler trace processing, since only the maximum and minimum values of the drain current during a given time interval are needed. Moreover, this extraction method can also estimate defects causing small current shifts, which can be very complex to identify by traditional means. Experimental data in a wide range of gate voltages, from near-threshold up to nominal operation conditions, are analyzed with the proposed methodology.
Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions
J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, J. Martin-Martinez, R. Castro-Lopez, E. Roca, F.V.Fernandez and M. Nafria
Journal Paper · Solid-State Electronics, vol. 185, article 108037, 2021
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In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and to understand the effects of these variability sources, an extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models and simulation tools needed to achieve reliable integrated circuits. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at nominal and accelerated aging conditions. To this end, a versatile transistor array chip and a flexible measurement setup have been used to reduce the required testing time to attainable values.
Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · Microelectronics Reliability, vol. 118, article 114049, 2021
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The utilization of power-up values in SRAM cells to generate PUF responses for chip identification is a subject of intense study. The cells used for this purpose must be stable, i.e., the cell should always power-up to the same value (either ‘0’ or ‘1’). Otherwise, they would not be suitable for the identification. Some methods have been presented that aim at increasing the reliability of SRAM PUFs by identifying the strongest cells, i.e., the cells that more consistently power-up to the same value. However, these methods present some drawbacks, in terms of either their practical realization or their actual effectiveness in selecting the strongest cells at different scenarios, such as temperature variations or when the circuits have suffered aging-related degradation. In this work, the experimental results obtained for a new method to classify the cells according to their power-up strength are presented and discussed. The method overcomes some of the drawbacks in previously reported methods. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation and temperature variations, which ultimately translates into the construction of reliable SRAM-based PUFs.
An efficient transformer modeling approach for mm-wave circuit design
F. Passos, E. Roca, J. Sieiro, R. Castro-Lopez and F.V. Fernandez
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 128, article 153496, 2021
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In this paper, a Gaussian-process surrogate modeling methodology is used to accurately and efficiently model transformers, which are still a bottleneck in radio-frequency and millimeter-wave circuit design. The proposed model is useful for a wide range of frequencies from DC up to the millimeter-wave range (over 100 GHz). The technique is statistically validated against full-wave electromagnetic simulations. The efficient model evaluation enables its exploitation in iterative user-driven design approaches, as well as automated design exploration involving thousands of simulations. As experimental results, the model is used in several scenarios, such as the design of an inter-stage amplifier operating at 60 GHz, where the model assisted in the simulation of the transformers and baluns used, and the design of individual transformers and a matching network.
Synthesis of mm-Wave Wideband Receivers in 28nm CMOS Technology for Automotive Radar Applications
F. Passos, M. Chanca, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp 4375-4384, 2020
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A new strategy for millimeter-wave circuit and system synthesis, where the accuracy of electromagnetic simulations can be achieved in optimization-based design methodologies without sacrificing efficiency, is presented and tested within a real industrial project. This is done by properly partitioning the system, generating libraries of passive devices which are electromagnetically simulated prior to any circuit optimization, generating performance trade-offs at different hierarchical levels with multi-objective optimization algorithms and hierarchically composing lower level sub-blocks. With this proposed solution, an entire millimeter-wave system, from the passive component level up to the system level, has been designed and compared with the results obtained from a conventional design approach, demonstrating the outstanding capabilities of the methodology.
Ready-to-Fabricate RF Circuit Synthesis using a Layout- and Variability-Aware Optimization-based Methodology
F. Passos, E. Roca, R. Martins, N. Lourenço, S. Ahyoune, J. Sieiro, R. Castro-Lopez, N. Horta and F.V. Fernandez
Journal Paper · IEEE Access, vol. 8, pp. 51601-51609, 2020
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In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators that were designed using a fully-automated, layout-and variability-aware optimization-based methodology. The methodology uses a highly accurate model, based on machine-learning techniques, to characterize inductors, and a multi-objective optimization algorithm to achieve a Pareto-optimal front containing optimal circuit designs offering different performance trade-offs. The final outcome of the proposed methodology is a set of design solutions (with their GDSII description available and ready-to-fabricate) that need no further designer intervention. Two key elements of the proposed methodology are the use of an optimization algorithm linked to an off-the-shelf simulator and an inductor model that yield EM-like accuracy but with much shorter evaluation times. Furthermore, the methodology guarantees the same high level of robustness against layout parasitics and variability that an expert designer would achieve with the verification tools at his/her disposal. The methodology is technology-independent and can be used for the design of radio frequency circuits. The results are validated with experimental measurements on a physical prototype.
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Journal Paper · Integration, vol. 72, pp 13-20, 2020
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In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely affect circuit reliability. It becomes therefore imperative to develop reliability-aware design tools to mitigate their impact on circuits. To this end, these phenomena must be first accurately characterized and modeled. And, since all these phenomena reveal a stochastic nature for deeply-scaled integration technologies, they must be characterized massively on devices to extract the probability distribution functions associated to their characteristic parameters. In this work, a complete methodology to characterize these phenomena experimentally, and then extract the necessary parameters to construct a Time-Dependent Variability model, is presented. This model can be used by a reliability simulator.
Flexible Setup for the Measurement of CMOS Time-Dependent Variability with Array-Based Integrated Circuits
J. Diaz-Fortuny, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, F.V. Fernandez and M. Nafria
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 69, no. 2, pp 853-864, 2020
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This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically time-consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals.
A Multilevel Bottom-up Optimization Methodology for the Automated Synthesis of RF Systems
F. Passos, E. Roca, J. Sieiro, R. Fiorelli, R. Castro-López, J.M. López-Villegas and F.V. Fernández
Journal Paper · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 3, pp 560-571, 2020
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In recent years there has been a growing interest in electronic design automation methodologies for the optimizationbased design of radiofrequency circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle radiofrequency systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this work, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multi-objective optimization algorithms are used to design an entire radiofrequency system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.
Two-Step RF IC Block Synthesis with Preoptimized Inductors and Full Layout Generation In-the-Loop
R. Martins, N. Lourenço, F. Passos, R. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. Sieiro, F.V. Fernández and N. Horta
Journal Paper · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 6, pp 989-1002, 2019
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In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.
A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors
P. Saraza-Canflanca, J. Martin-Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Journal Paper · Microelectronic Engineering, vol. 215, article 111004, 2019
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Random Telegraph Noise (RTN) has attracted increasing interest in the last years. This phenomenon introduces variability in the electrical properties of transistors, in particular in deeply-scaled CMOS technologies, which can cause performance degradation in circuits. In this work, the dependence of RTN parameters, namely current jump amplitude and emission and capture time constants, on the bias conditions, both VG and VD, has been studied on a set of devices, with a high granularity in a broad voltage range. The results obtained for the VG dependences corroborate previous works, but suggest a unique trend for all the devices in a VG range that goes from the near-threshold region up to voltages over the nominal operation bias. However, different trends have been observed in the parameters dependence for the case of VD. From the experimental data, the probabilities of occupation of the associated defects have been evaluated, pointing out large device-to-device dispersion in the VD dependences.
A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
Journal Paper · Solid-State Electronics, vol. 159, pp 99-105, 2019
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In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
J. Diaz-Fortuny, J. Martin-Martines, R. Rodriguez, R. Castro-Lopez, E. Roca, X. Aragones, E. Barajas, D. Mateo, F.V. Fernandez and M. Nafria
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp 476-488, 2019
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Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm2.
A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper · Soft Computing, vol. 23, no. 13, pp 4911-4925, 2019
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The knowledge-intensive radiofrequency circuit design and the scarce design automation support play against the increasingly stringent time-to-market demands. Optimization algorithms are starting to play a crucial role; however, their effectiveness is dramatically limited by the accuracy of the evaluation functions of objectives and constraints. Accurate performance evaluation of radiofrequency passive elements, e.g., inductors, is provided by electromagnetic simulators, but their computational cost makes their use within iterative optimization loops unaffordable. Surrogate modeling strategies, e.g., Kriging, support vector machines, artificial neural networks, etc., arise as a promising modeling alternative. However, their limited accuracy in this kind of applications has prevented a widespread use. In this paper, inductor performance properties are exploited to develop a two-step surrogate modeling strategy in order to evaluate the behavior of inductors with high efficiency and accuracy. An automated design flow for radiofrequency circuits using this surrogate modeling of passive components is presented. The methodology couples a circuit simulator with evolutionary computation algorithms such as particle swarm optimization, genetic algorithm or non-dominated sorting genetic algorithm (NSGA-II). This methodology ensures optimal performances within short computation times by avoiding electromagnetic simulations of inductors during the entire optimization process and using a surrogate model that has less than 1% error in inductance and quality factor when compared against electromagnetic simulations. Numerous real-life experiments of single-objective and multi-objective low-noise amplifier design demonstrate the accuracy and efficiency of the proposed strategies.
A comparison of automated RF circuit design methodologies: online vs. offline passive component design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper · IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 11, pp 2386-2394, 2018
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In this paper, surrogate modeling techniques are applied for passive component modeling. These techniques are exploited to develop and compare two alternative strategies for automated radio-frequency circuit design. The first one is a traditional approach where passive components are designed during the optimization stage. The second one, inspired on bottom-up circuit design methodologies, builds passive component Pareto-optimal fronts (POFs) prior to any circuit optimization. Afterward, these POFs are used as an optimized library from where the passive components are selected. This paper exploits the advantages of evolutionary computation algorithms in order to efficiently explore the circuit design space, and the accuracy and efficiency of surrogate models to model passive components.
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Póvoa, A. Canelas, R. Castro-López, N. Horta and F.V. Fernández
Journal Paper · Integration, vol. 63, pp 351-361, 2018
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In this paper a design strategy based on bottom-up design methodologies is used in order to systematically design a voltage controlled oscillator. The methodology uses two computer-aided design tools: AIDA, a multi-objective multi-constraint circuit optimization tool, and SIDe-O, a tool that characterizes and optimizes integrated inductors with high accuracy (around 1% when compared to electromagnetic simulations). By using such tools, the difficult trade-offs inherent to radio-frequency circuits can be explored efficiently and accurately. Furthermore, with the capability that AIDA has at considering process parameter variations during the optimization, the resulting methodology is able to obtain truly robust circuit designs.
Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling
F. Passos, E. Roca, R.Castro-López and F.V. Fernández
Journal Paper · Applied Soft Computing, vol. 60, pp 495-507, 2017
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In recent years, the application of evolutionary computation techniques to electronic circuit design problems, ranging from digital to analog and radiofrequency circuits, has received increasing attention. The level of maturity runs inversely to the complexity of the design task, less complex in digital circuits, higher in analog ones and still higher in radiofrequency circuits. Radiofrequency inductors are key culprits of such complexity. Their key performance parameters are inductance and quality factors, both a function of the frequency. The inductor optimization requires knowledge of such parameters at a few representative frequencies. Most common approaches for optimization-based radiofrequency circuit design use analytical models for the inductors. Although a lot of effort has been devoted to improve the accuracy of such analytical models, errors in inductance and quality factor in the range of 5%-25% are usual and it may go as high as 200% for some device sizes. When the analytical models are used in optimization-based circuit design approaches, these errors lead to suboptimal results, or, worse, to a disastrous non-fulfilment of specifications. Expert inductor designers rely on iterative evaluations with electromagnetic simulators, which, properly configured, are able to yield a highly accurate performance evaluation. Unfortunately, electromagnetic simulations typically take from some tens of seconds to a few hours, hampering their coupling to evolutionary computation algorithms. Therefore, analytical models and electromagnetic simulation represent extreme cases of the accuracy-efficiency trade-off in performance evaluation of radiofrequency inductors. Surrogate modeling strategies arise as promising candidates to improve such trade-off. However, obtaining the necessary accuracy is not that easy as inductance and quality factor at some representative frequencies must be obtained and both performances change abruptly around the self-resonance frequency, which is particular to each device and may be located above or below the frequencies of interest. Both, offline and online training methods will be considered in this work and a new two-step strategy for inductor modeling is proposed that significantly improves the accuracy of offline methods The new strategy is demonstrated and compared for both, single-objective and multi-objective optimization scenarios. Numerous experimental results show that the proposed two-step approach outperforms simpler application strategies of surrogate modelling techniques, getting comparable performances to approaches based on electromagnetic simulation but with orders of magnitude less computational effort.
Parametric macromodeling of integrated inductors for RF circuit design
F. Passos, Y. Ye, D. Spina, E. Roca, R. Castro-López, T. Dhaene and F.V. Fernández
Journal Paper · Microwave and Optical Technology Letters, vol. 59, no. 5, pp 1207-1212, 2017
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Nowadays, parametric macromodeling techniques are widely used to describe electromagnetic structures. In this contribution, the application of such parametric macromodeling techniques to the design of integrated inductors and radio-frequency circuit design is investigated. In order to allow such different operations, a new modeling methodology is proposed, which improves the modeling accuracy when compared to former techniques. The new methodology is tailored to the unique characteristics of the devices under study. The obtained parametric macromodel is then used in a synthesis methodology and in the design of a voltage controlled oscillator in a 0.35-μm CMOS technology.
An inductor modeling and optimization toolbox for RF circuit design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper · Integration, the VLSI Journal, vol. 58, pp 463-472, 2017
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This paper describes the SIDe-O toolbox and the support it can provide to the radio-frequency designer. SIDe-O is a computer-aided design toolbox developed for the design of integrated inductors based on surrogate modeling techniques and the usage of evolutionary optimization algorithms. The models used feature less than 1% error when compared to electromagnetic simulations while reducing the simulation time by several orders of magnitude. Furthermore, the tool allows the creation of S-parameter files that accurately describe the behavior of inductors for a given range of frequencies, which can later be used in SPICE-like simulations for circuit design in commercial environments. This toolbox provides a solution to the problem of accurately and efficiently optimizing inductors, which alleviates the bottleneck that these devices represent in the radio-frequency circuit design process.
An automated design methodology of RF circuits by using Pareto-optimal fronts of EM-simulated inductors
R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, J. Sieiro, J.M. López-Villegas and N. Vidal
Journal Paper · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp 15-26, 2017
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A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a single-objective and a multi-objective optimization of a Low Noise Amplifier.
Reliability simulation for analog ICs: Goals, solutions, and challenges
A. Toro-Frías, P. Martín-Lloret, J. Martin-Martinez, R. Castro-López, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernández
Journal Paper · Integration, the VLSI Journal, vol. 55, pp 341-348, 2016
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The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.
Automated generation of the optimal performance trade-offs of integrated inductors
R. González-Echevarría, R. Castro-López, E. Roca, F.V. Fernández, J. Sieiro, N.Vidal and J.M. López-Villegas
Journal Paper · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 8, pp. 1269-1273, 2014
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In this paper, a new methodology for the automated generation of the optimal performance trade-offs of integrated inductors is presented. The methodology combines a multiobjective optimization algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. Unlike reported approaches for inductor synthesis, performance trade-offs are generated offline, i.e., before any specific inductance or quality factor are required. The tight efficiency versus accuracy trade-off of existing approaches is, in this way, avoided and performance evaluation via electromagnetic simulation becomes affordable.
Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors
M. Kotti, R. González-Echevarría, F.V. Fernández, E. Roca, J. Sieiro, R. Castro-López, M. Fakhfakh and J.M. López-Villegas
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 78, no. 1, pp 87-97, 2014
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Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor, self-resonance frequency and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is generated by embedding a performance evaluator into a multi-objective optimization tool. Then, starting from the optimal front samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35-μm CMOS technology are provided.
Introduction to the special issue on SMACD 2012
F.V. Fernández, E. Roca and R. Castro-López
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 78, no. 1, pp 61-63, 2014
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Abstract not avaliable
A programmable and configurable ASIC to generate piecewise-affine functions defined over general partitions
P. Brox, R. Castro-Ramirez, M.C. Martinez-Rodriguez, E. Tena, C.J. Jimenez, I. Baturone and A.J. Acosta
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 12, pp 3182-3194, 2013
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This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated Circuit (ASIC) to generate Piecewise-Affine (PWA) functions. A Generic PWA form (PWAG) has been selected for integration, because of its suitability to implement any PWA function without resorting to approximation. The design of the ASIC in a 90 nm TSMC technology, its integration, test and characterization through different examples are detailed in the paper. Furthermore, the ASIC verification using an ASIC-in-the-loop methodology for embedded control applications is presented. To assess the characteristics of this verification, the double-integrator, a usual control application example has been considered. Experimental results validate the proposed architecture and the ASIC implementation.
Context-dependent transformation of Pareto-optimal performance fronts of operational amplifiers
E. Roca-Moreno, M. Velasco-Jiménez, R. Castro-López and F.V. Fernández-Fernández
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 73, no. 1, pp 65-76, 2012
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The use of Pareto-optimal performance fronts in emerging design methodologies for analog integrated circuits is a keystone to overcome the limitations of traditional design methodologies. However, most techniques to generate the fronts reported so far neglect the effect that the surrounding circuitry (such as the load impedance) has on the Pareto-front, thereby making it only realistic for the context where the front was generated. This strongly limits the use of the Pareto front because of the strong dependence between the key performances of an analog circuit and its surrounding circuitry, but, more importantly, because this circuitry remains unknown until the Pareto-optimal front is being used. Since performance front generation is a costly process, this paper proposes that performance fronts for a new context of use of a given circuit can be obtained from fronts that were previously generated under some different conditions. Towards this goal, a transformation methodology for performance objectives of operational amplifiers has been developed. Experimental results for a folded-cascode and a Miller-compensated operational amplifiers show that this is a promising approach to reuse the fronts in multiple contexts.
A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications
A. Morgado, R. del Río, J.M. de la Rosa, R. Castro-López and B. Pérez-Verdú
Journal Paper · Microelectronics Journal, vol. 41, no. 5, pp 277-290, 2010
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This paper describes the design and experimental characterization of a 0.13 mu m CMOS switched-capacitor reconfigurable cascade Sigma Delta modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode EA prototype shows an overall performance that is competitive with the current state of the art.(1) (C) 2010 Elsevier Ltd. All rights reserved.
A memetic approach to the automatic design of high-performance analog integrated circuits
B. Liu, F.V. Fernández, G. Gielen, R. Castro-López and E. Roca
Journal Paper · Transactions on Design Automation of Electronic Systems, vol. 14, no. 3, pp 42, 2009
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This article introduces an evolution-based methodology, named memetic single-objective evolutionary algorithm (MSOEA), for automated sizing of high-performance analog integrated circuits. Memetic algorithms may achieve higher global and local search ability by properly combining operators from different standard evolutionary algorithms. By integrating operators from the differential evolution algorithm, from the real-coded genetic algorithm, operators inspired by the simulated annealing algorithm, and a set of constraint handling techniques, MSOEA specializes in handling analog circuit design problems with numerous and tight design constraints. The method has been tested through the sizing of several analog circuits. The results show that design specifications are met and objective functions are highly optimized. Comparisons with available methods like genetic algorithm and differential evolution in conjunction with static penalty functions, as well as with intelligent selection-based differential evolution, are also carried out, showing that the proposed algorithm has important advantages in terms of constraint handling ability and optimization quality.
Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey
J.M. de la Rosa, R. Castro-López, A. Morgado, E.C. Becerra Alvarez, R. del Río, F.V. Fernández and B. Pérez-Verdú
Journal Paper · Microelectronics Journal, vol. 40, no. 1, pp 156-176, 2009
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The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical. These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems. (C) 2008 Elsevier Ltd. All rights reserved.
Multimode Pareto fronts for design of reconfigurable analogue circuits
R. Castro-López, E. Roca and F.V. Fernández
Journal Paper · Electronics Letters, vol. 45, no. 2, pp 95-96, 2009
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Multimode Pareto-optimal fronts are presented. This is a novel concept that can be key in the design of reconfigurable analogue circuits, because it contains information not only on the trade-offs among the circuit performances, but also on its reconfiguration capabilities. A method to generate the front, relying on evolutionary optimisation, and a general dominance sorting algorithm that guides the optimisation, are both described.
Systematic top-down design of reconfigurable ΣΔ modulators for multi-standard transceivers
R. Castro-López, A. Morgado, O. Guerra, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and F. Fernández
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 58, no. 3, pp 227-241, 2009
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This paper addresses the design techniques of reconfigurable analog-to-digital converters for multi-standard wireless communication terminals. While most multi-standard converters reported so far follow an ad hoc design approach, which do not guarantee either efficient silicon area occupation or power efficiency in the different operation modes, the methodology presented here formulates a systematic design flow that ensures that both factors are considered at all hierarchical levels. Expandible cascade modulators are considered as the starting point to further reconfigurability at the architectural level. From here on, and using a combination of accurate behavioral modeling, statistical optimization techniques, and device-level simulation, the proposed methodology handles the design complexity of a reconfigurable converter while ensuring adaptive power consumption and boosting hardware sharing. A case study is presented where a reconfigurable modulator is designed to operate under three communication standards, GSM, Bluetooth, and UMTS, in a 130 nm-CMOS technology.
AMS/RF-CMOS circuit design for wireless transceivers
R. Castro-López, D.R. de Llera, M. Ismail and F.V. Fernández
Journal Paper · Integration, the VLSI Journal, vol. 42, no. 1, pp 1-2, 2009
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Abstract not available
An integrated layout-synthesis approach for analog ICs
R. Castro-López, O. Guerra, E. Roca and F.V. Fernández
Journal Paper · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 7, pp 1179-1189, 2008
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In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided.
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK
A. Morgado, V.J. Rivas, R. del Río, R. Castro-López, F.V. Fernández and J.M. de la Rosa
Journal Paper · Integration, the VLSI Journal, vol. 41, no. 2, pp 269-280, 2008
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This paper presents a SIMULINK block set for the behavioral modeling and high-level simulation of RF receiver front-ends. The toolbox includes a library with the main RF circuit models that are needed to implement wireless receivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the following non-idealities: thermal noise, characterized by the noise figure and the signal-to-noise ratio, and non-linearity, represented by the input-referred second-order and third-order intercept points, IIP2 and IIP3, respectively. In addition to these general parameters, some block-specific errors have also been included, like oscillator phase noise and mixer offset. These models have been incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, which makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As an application of the capabilities of the presented toolbox, a multi-standard direct-conversion receiver intended for 4G telecom systems is modeled and simulated considering the building block requirements for the different standards. (C) 2007 Elsevier B.V. All rights reserved.
Systematic design of high-resolution high-frequency cascade continuous-time sigma-delta modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, E. Roca, A. Rodríguez Vázquez and F.V. Fernández
Journal Paper · ETRI Journal, vol. 30, no. 4, pp 535-545, 2008
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This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigma-delta (SIGMA DELTA) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT SIGMA DELTA modulator in a 1.2 V 130 nm CMOS technology.
Synthesis of a wireless communication analog back-end based on a mismatch-aware symbolic approach
R. Castro-López, O. Guerra, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 40, no. 3, pp 215-233, 2004
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In this paper, a methodology to automate the synthesis of an industrial-purpose analog integrated circuit, namely the back-end of an I&Q transmit interface, is presented. A good matching between both I and Q channels is desirable to ensure the correct circuit functioning. The proposed methodology combines the use of symbolic expressions with numerical approaches. While the symbolic expressions allow a fast iterative evaluation of the circuit performance, the numerical capabilities ensure a rapid optimization of the results. Unlike other approaches, the methodology uses symbolic expressions explicitly considering device mismatch, which are evaluated performing a Monte-Carlo analysis. The expressions have been obtained using an error-control process guided by the mean and standard deviation values of the circuit performance characteristics. This provides two benefits. First, smaller expressions are obtained. Second, expression evaluation is faster: smaller number of operations - symbol products and term sums - are carried out since, at each Monte-Carlo run, only those symbols related to device mismatch are to be changed, while the rest remains constant. A comparison between the presented synthesis technique and other purely numerical and numerical/symbolic approaches is also given.
Congresos
Machine Learning Approaches for Transformer Modeling
F. Passos, N. Lourenço, R. Martins, E. Roca, R. Castro-Lopez, N. Horta and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
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In this paper, several machine learning modeling methodologies are applied to accurately and efficiently model transformers, which are still a bottleneck in millimeter-wave circuit design. In order to compare the models, a statistical validation is performed against electromagnetic simulations using hundreds of passive structures. The presented models using machine learning techniques have proven to be accurate, efficient, and useful for a wide range of frequencies from (around) DC up to the millimeter-wave range (around 100GHz). As an application example, the models are used as a performance evaluator in a synthesis procedure to optimize a transformer and a balun.
Characterization and analysis of BTI and HCI effects in CMOS current mirrors
A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
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This paper presents experimental results on the aging-induced degradation of CMOS current mirrors fabricated in a 65-nm CMOS technology. A dedicated integrated circuit array with custom test structures allowing for accelerated aging tests is used for the characterization, including several geometries of simple current mirrors, in PMOS and NMOS versions. The bi-directional link between device degradation and bias conditions that comes into play during circuit aging, as well as the permanent degradation, are both reported and analysed.
High-level design of a novel PUF based on RTN
E. Camacho-Ruiz, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
resumen
Physically Unclonable Functions (PUFs) have emerged as an alternative to traditional Non-Volatile Memories in the field of lightweight hardware security. Recently, a novel PUF has been presented that uses the Random Telegraph Noise (RTN) phenomenon as the underlying source of entropy. While, in general, the nature of that entropy source largely dictates the quality of a PUF, little attention is often paid, however, to how the PUF architecture and its building blocks impact the PUF quality. This paper addresses the high-level design of the novel PUF to ascertain the extent of that impact and refine the building blocks specifications to mitigate it. Using high-level numerical and mixed-signal electrical simulations, the results demonstrate that it is very important to account for nonidealities in the PUF´s building blocks to prevent PUF quality degradation.
On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF
E. Camacho-Ruiz, A. Santana-Andreo, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
resumen
Physical Unclonable Functions (PUFs) use variability as an entropy source from which to generate secure authentication and identification. While most silicon PUFs exploit the well-known Time-Zero Variability of CMOS technologies, the lack of efficient simulation tools for the Time- Dependent Variability (TDV) has left the potential benefits of this other kind of variability largely unexplored. However, recent advances in the field are allowing this exploration to begin. The objective of this paper is then to take a recently reported simulation tool to design a novel PUF that uses the Random Telegraph Noise (RTN), a TDV phenomenon, as the underlying entropy source. In the ensuing analysis, essential design guidelines are provided to best exploit such entropy source with factors like transistor biasing and sizing.
Impact of BTI and HCI on the reliability of a majority voter
A. Santana-Andreo, E. Roca, R. Castro-Lopez and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
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Triple Modular Redundancy is a commonly used hardware technique in mission- and safety-critical systems to ensure reliability. Although a simple circuit, the majority voter can be the weak link in this system and different designs have been proposed to increase its robustness to single event effects and permanent faults. However, no study has been performed to analyze the effect of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) on a majority voter, which can lead to timing failures or exacerbate other failure mechanisms. This work uses a state-of-the-art aging simulator to estimate the effects of aging on a majority voter.
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation
P. Saraza-Canflanca, J. Martin-Martinez, E. Roca, R. Castro-Lopez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
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This paper addresses the automated parameter extraction of Random Telegraph Noise models in nanoscale fieldeffect transistors. Unlike conventional approaches based on complex extraction of current levels and timing of trapping/detrapping events from individual defects in current traces, the proposed approach performs a simple processing of current traces. A smart optimization problem formulation allows to get distribution functions of the amplitude of the current shifts and of the number of active defects vs. time.
A Novel Physical Unclonable Function Using RTN
E. Camacho-Ruiz, R. Castro-Lopez, E. Roca, P. Brox and F.V. Fernandez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2022
resumen
PUFs have emerged as an alternative to traditional Non-Volatile Memories in the field of hardware security. In this paper, a novel PUF is proposed that uses the Random Telegraph Noise phenomenon as the underlying source of entropy. This phenomenon manifests as discrete and random shifts in the drain current of transistors and it is characterized by several parameters like the number of the defects in the device, as well as the emission and capture time constants and current shifts of these defects. Using the recently reported Maximum Current Fluctuation metric, it is possible to condense all this information and use it for the PUF design. By forming pairs of transistors, measuring, and comparing their Maximum Current Fluctuation over a given time interval, we demonstrate that it is possible to obtain a PUF. Furthermore, the results reported here show that this RNT-based PUF meets, and even outperforms, other silicon PUFs in terms of uniqueness, unpredictability, and reliability with an evident advantage in silicon area.
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, J. Diaz-Fortuny, R. Castro, E. Roca and F.V. Fernandez
Conference · IEEE International Reliability Physics Symposium IRPS 2022
resumen
Time-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.
Characterizing Aging Degradation of Integrated Circuits with a Versatile Custom Array of Reliability Test Structures
A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez and F.V. Fernandez
Conference · IEEE International Conference on Microelectronic Test Structures ICMTS 2022
resumen
Abstract not available
The Two-Faced Variability Challenge in Nanoelectronics: Mitigation and Exploitation... and How to Get There
R. Castro-López
Conference · International Conference on Electrical and Electronics Engineering ELECO 2021
resumen
Electronic devices flood many aspects of our lives. The wondrous evolution of nano-CMOS technologies with the emergence of new materials and devices is behind it.
The demand for integrated circuits (ICs) is not without challenges though: our modern digital economy and society require them to be more functional, more reliable, safer, and more secure, and fields like IoT, Cybersecurity, and High- performance computing are now priorities in many research agendas.
However, one critical obstacle in this evolution is variability, a culprit for the device parametric fluctuations deriving in a reliability loss of the IC. Rising right after fabrication (TZV, Time-Zero Variability) or during the IC lifetime (TDV, Time-Dependent Variability), it ends up critically compromising its functionality or even cutting short its lifetime. If variability is undealt with, ICs will no longer be able to fulfill the capabilities of safety, security, and reliability.
This talk tackles this challenge from two perspectives. It will first describe solutions and new design paradigms to lessen or tolerate variability; the goal is clear: mitigate its negative impact. Second, realizing variability has also a beneficial side, the talk will approach the paradigm of exploiting TZV and TDV for hardware-based security.
In mitigation, this talk will show some results from a reliability-aware design methodology that can create inherently robust ICs.
In exploitation, the goal is not only to analyze the impact of aging in conventional TZV-based cryptographic primitives (like the well-known Physically Unclonable Functions) but also to explore whether TDV could be used as a robust underlying entropy source.
But the first step to both mitigation and exploitation requires a deep understanding of variability. While TZV is well known, TDV needs a holistic approximation to its different effects (aging and RTN), and going from characterization to modeling requires a careful selection of which data and lab setups are needed (for the variables to experiment with are numerous). Only this will lead to efficient models and simulation strategies to design ICs for mitigation or exploitation.
This talk will provide a glimpse into the intricacies that careful TDV modeling requires.
Simulating the impact of Random Telegraph Noise on integrated circuits
P. Saraza-Canflanca, E. Camacho-Ruiz, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2021
resumen
This paper addresses the statistical simulation of integrated circuits affected by Random Telegraph Noise (RTN). For that, the
statistical distributions of the parameters of a defectcentric model for RTN are experimentally determined from a purposely
designed integrated circuit with CMOS transistor arrays. Then, these distribution functions are used in a statistical simulation
methodology that, taking into account transistor sizes, biasing conditions and time, can assess the impact of RTN in the performance
of an integrated circuit. Simulation results of a simple circuit are shown together with experimental measurements of a
circuit with the same characteristics implemented in the same CMOS technology.
Dealing with hierarchical partitioning in bottom-up design methodologies
F. Passos, P. Saraza-Canflanca, R. Castro Lopez, E. Roca and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2021
resumen
This paper deals with the expertise blend of circuit design and design methodology development required to successfully
address hierarchical partitioning of analog, radio-frequency and mm-Wave circuits in bottom-up design methodologies. A set
of guidelines is discussed for the optimal configuration of the bottom-up process that yields sound design results are obtained.
These guidelines are demonstrated with two case studies.
A study of SRAM PUFs reliability using the Static Noise Margin
E. Camacho-Ruiz, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, P. Brox and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2021
resumen
The use of SRAM cells as key elements in a Physical Unclonable Function (PUF) has been widely reported. An essential characteristic
the SRAM cell must feature for a reliable PUF is stability, i.e., it must power up consistently to the same value. Different
techniques to measure this stability (and thus improve the PUF reliability) have been reported, such as the Multiple Evaluation
method and, more recently, the Maximum Trip Supply Voltage method, the latter using the Data Retention Voltage (DRV) concept.
While experimental results have been reported, this paper sheds some light from a different perspective: simulation. In this sense,
and using wellknown concepts like butterfly curves, static noise margin and voltage-transfer curves, an analysis is provided on
why and how stability originates in the cell. Moreover, by simulating the butterfly curve behavior when the supply voltage scales
down, it is possible to correlate DRV with stability, thereby confirming the correct theoretical foundation of the MTSV method.
Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization roadblock
M. Nafria, J. Diaz-Fortuny, P. Saraza-Canflanca, J. Martin-Martinez, E. Roca, R. Castro-Lopez, R. Rodriguez, P. Martin-Lloret, A. Toro-Frias, D. Mateo, E. Barajas, X. Aragones and F.V. Fernandez
Conference · IEEE Latin America Electron Devices Conference LAEDC 2021
resumen
The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.
Improving the reliability of SRAM-based PUFs under varying conditions
P. Sarazá-Canflanca, H. Carrasco-López, P. Brox, R. Castro-López, E. Roca and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
resumen
Abstract not available
Improving the reliability of SRAM-based PUFs in the presence of aging
P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · Design and Technology of Integrated Systems in Nanoscale Era DTIS 2020
resumen
The utilization of power-up values in SRAM cells for the generation of PUF responses has been widely studied. It is important that the cells used for this purpose are stable, i.e., the cells must have a strong tendency towards one of the two possible values (‘ ‘0 ’ or ‘1 ’). Some methods have been presented that aim at increasing the reliability of this type of PUFs by selecting the strongest cells among a set of them. However, they feature some drawbacks, either in terms of their practical feasibility or of their actual effectiveness selecting the strongest cells in different scenarios. In this work, the experimental results obtained for a new method to classify the cells according to their strength are presented and discussed. The technique overcomes some of the drawbacks that the previous methods present. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation, which translates into the construction of reliable SRAM-based PUFs.
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks
P. Martin-Lloret, J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
resumen
This paper presents an integrated circuit (IC) array whose purpose is to observe, quantify and characterize the impact of time-dependent variability effects, like aging, in several widely used digital and analog circuit blocks. With the increasing interest that this kind of mechanism has attracted in the last years, for its potential impact in the reliability of ultra-scaled integrated circuits, it is only relevant that appropriate measures are taken to find out how it can be included (and thus mitigated) in the design process of such integrated circuits. And, while substantial literature exists that covers the device level, time-dependent variability at circuit level has not been as equally studied. This work complements our previous efforts in providing a holistic approach to Reliability-Aware Design: from statistical characterization and modeling at device-level, to simulation, and into optimization-based design with reliability considerations, the array presented here provides one more step towards a thorough and accurate understanding of how time-dependent variability works at the circuit level.
Synthesis of mm-Wave circuits using EM-simulated passive structure libraries
F. Passos, E. Roca, R. Castro-Lopez, N. Horta and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
resumen
Millimeter-wave circuit design is extremely complex and time-consuming. One of the reasons is the dependence on electromagnetic simulators used to accurately predict the performance of the high amount of passive structures that compose such circuits. Also, achieving optimal performances is not trivial in the millimeter-wave regime. Although synthesis methodologies can aid the designer to achieve optimal circuit performances, the usage of electromagnetic simulators is prohibitive in such methodologies due to efficiency issues. In this work, a new synthesis methodology is presented where the accuracy of electromagnetic simulations can be included without losing efficiency.
Experimental Characterization of Time-Dependent Variability in Ring Oscillators
J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
resumen
Reliability in CMOS-based integrated circuits has always been a critical concern. In today′s ultra-scaled technologies, a time-varying kind of variability has raised that, on top of the well-known time-zero variability, threatens to shorten the lifetime of integrated circuits, both analog and digital. Effects like Bias Temperature Instability and Hot Carriers Injection need to be studied, characterized and modeled to include, and, thus, mitigate, their impact in the design of CMOS integrated circuits. This paper presents an array-based integrated circuit whose purpose is precisely that: to observe, quantify and characterize the impact of timedependent variability effects in a specific kind of circuits: Ring Oscillators.
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
resumen
Time-Dependent Variability has attracted
increasing interest in the last years. In particular, phenomena
such as Bias Temperature Instability, Hot Carrier Injection and
Random Telegraph Noise can have a large impact on circuit
reliability, and must be therefore characterized and modeled.
For technologies in the nanometer range, these phenomena
reveal a stochastic behavior and must be characterized in a
massive manner, with enormous amounts of data being
generated in each measurement. In this work, a novel tool with
a user-friendly interface, which allows the robust and fullyautomated
parameter extraction for RTN, BTI and HCI
experiments, is presented.
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Design Automation and Test in Europe DATE 2019
resumen
Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and timeefficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability.
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez
Conference · Design Automation and Test in Europe DATE 2019
resumen
Bias Temperature Instability has become a critical issue for circuit reliability. This phenomenon has been found to have a stochastic and discrete nature in nanometerscale CMOS technologies. To account for this random nature, massive experimental characterization is necessary so that the extracted model parameters are accurate enough. However, there is a lack of automated analysis tools for the extraction of the BTI parameters from the extensive amount of generated data in those massive characterization tests. In this paper, a novel algorithm that allows the precise and fully automated parameter extraction from experimental BTI recovery current traces is presented. This algorithm is based on the Maximum Likelihood Estimation principles, and is able to extract, in a robust and exact manner, the threshold voltage shifts and emission times associated to oxide trap emissions during BTI recovery, required to properly model the phenomenon.
A new time efficient methodology for the massive characterization of RTN in CMOS devices
G. Pedreira, J. Martin-Martinez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
Conference · IEEE International Reliability Physics Symposium IRPS 2019
resumen
Abstract not avaliable
CMOS characterization and compact modelling for circuit reliability simulation
J. Diaz Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · IEEE Int. Symposium on On-Line Testing and Robust System Design IOLTS 2018
resumen
With nowadays nanometer-CMOS technologies, time-zero and time dependent variability effects (like BTI, CHI, RTN, TDDB, EM, etc) have turned into an even more serious threat to the desired performance of analog and digital integrated circuits. Statistical characterization and modelling of these variability effects entail large testing times, which are typically prohibitive, and huge amounts of data, which are complex to post process. This paper describes novel characterization techniques that overcome these limitations, that is, they are capable of statistically testing nanometer CMOS devices with much shorter completion times. To properly handle the massive amounts of data from characterization, new extraction methods, described in this paper as well, have been developed. With these methods, an accurate variability-aware device model is completed, which can subsequently be used in reliability-aware circuit design methodologies.
Analysis of Body Bias and RTN-induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology
E. Barajas, X. Aragones, D. Mateo, F. Moll, J. Martin-Martinez, R. Rodríguez, M. Portí, M. Nafria, R. Castro-López, E. Roca and F.V Fernández-Fernández
Conference · Int. Symposium on Power and Timing Modeling, Optimization and Simulation PATMOS 2018
resumen
Electronic circuits powered at ultra low voltages (500 mV and below) are desirable for their low energy and power consumption. However, RTN (Random Telegraph Noise)-induced threshold voltage variations become very significant at such supply voltages. This paper evaluates the impact of RTN on additional jitter in a ring oscillator. Since FDSOI allows a large range of body bias voltages, this work studies how body biasing affects the oscillation frequency but also the jitter effects. The impact of RTN in NMOS and PMOS devices on frequency as well as the levels of supplementary jitter introduced by RTN are evaluated and compared with classical device noise.
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Castro-López, R. Póvoa, A. Canelas, N. Horta and F.V. Fernández
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen
This paper exposes the problematic issue of not considering device variability and layout parasitic effects in optimization-based design of radiofrequency integrated circuits. Therefore, in order to handle these issues, a new design methodology that performs an all-inclusive optimization is proposed, by taking into account the process variability, and, performing the complete layout automatically while performing an accurate parasitic extraction during the optimization for each candidate solution. Furthermore, the problematic inductor parasitics are also taken into account with EM-accuracy, by using a state-of-the-art surrogate modelling technique. The methodology was applied in the design and optimization of a low-noise amplifier, obtaining a set of extremely robust designs ready for fabrication.
Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen
Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.
Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs
A. Toro-Frías, P. Martín-Lloret, J. Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen
With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability but also the degradation due to time-dependent. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.
A Model Parameter Extraction Methodology Including Time-dependent Variability for Circuit Reliability Simulation
J. Diaz-Fortuny, P. Saraza-Canflanca, A. Toro-Frias, R. Castro-Lopez, J. Martin-Martinez, E. Roca, R. Rodriguez, F.V. Fernandez and M. Nafria
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen
In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by timedependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of aging device effects for reliability circuit
Automated massive RTN characterization using a transistor array chip
P. Saraza-Canflanca, J. Diaz-Fortuny, A. Toro-Frias, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen
In this work, a CMOS transistor array for the massive measurement of random telegraph noise (RTN), together with a dedicated experimental setup, is presented. The array chip, called ENDURANCE, allows the massive characterization of the RTN parameters needed for a complete understanding of the phenomenon. Additionally, some experimental results are presented that demonstrate the convenience of the setup.
Weighted Time Lag Plot Defect Parameter Extraction and GPU-based BTI Modeling for BTI Variability
V.M. van Santen, J. Diaz-Fortuny, H. Amrouch, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez, J. Henkel and M. Nafria
Conference · IEEE International Reliability Physics Symposium IRPS 2018
resumen
Recent MOSFET devices exhibit a strong variability in their Bias Temperature Instability (BTI) induced degradation (e.g., Vth-shift). For identical stress patterns, each device exhibits unique degradation behavior. As BTI variability increases with shrinking device geometries, modeling BTI variability becomes essential. The challenge of modeling BTI variability is the significant time required to characterize a representative set of devices to properly calibrate the BTI variability model. In addition, (SPICE) circuit simulations under BTI variability are extremely time consuming. Both challenges originate from unique uncorrelated BTI behavior in each device. Each device features a unique set of defects with a unique state (occupied/unoccupied) in each defect. In this work, we tackle the characterization challenge by processing the data acquired from our parallel measurement setup with lightweight and fast defect extraction. Our novel weighted time lag plot defect parameter extraction, removes uncorrelated voltage noise and categorizes correlated noise (i.e., Random Telegraph Noise (RTN)) and discrete voltage steps (i.e., BTI). After the measurement data is processed, capture time, emission time and induced degradation of each defect can be extracted. After defect parameters are extracted, we can fit a bi-variate log-normal defect distribution and calibrate our BTI model. To employ a BTI variability model in circuit simulation, it must be able to model thousands of MOSFETs. Circuits consist of thousands of devices, each with unique behavior, resulting in computationally intensive modeling. Our GPU-based BTI variability model employs massive parallelism (beyond 1000 processing cores) found in graphic cards to model thousands of MOSFETs in seconds. Therefore, our novel defect parameter extraction methodology allows lightweight, yet accurate characterization of our model, while our model itself enables circuit simulations in large circuits as it models 100,000 MOSFETs in just 119s.
A noise and RTN-removal smart method for the parameter extraction of CMOS aging compact models
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2018
resumen
This work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔV th ) related to oxide defects in nanometer CMOS transistors during aging tests. The method identifies the V th drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.
Reliability in the circuit design flow: from characterization and modelling to design automation
R. Castro-López, J. Díaz, J. Martín-Martínez, R. Rodríguez, M. Nafría, A. Toro, P. Martín, E. Roca, F.V. Fernández, E. Barajas, X. Aragonés and D. Mateo
Conference · How to survive in an unreliable world, IEEE CEDA Spain Chapter / NANOVAR Workshop 2017
resumen
Designing reliable analog circuits in advanced process technologies requires an accurate understanding of both device performance and variability. The unavoidable and increasingly important process-induced variations is, today, not alone in perturbing the ideal, intended performance of analog circuits: the so-called aging phenomena, like Bias Temperature Instability and Hot Carriers Injection, are altogether making the analog design business a much more tortuous endeavour.
The work presented here will paint a complete picture of how to deal with variability in analog circuits for advanced process technologies. This picture starts with the characterisation and modelling of the aging phenomena at the device level. It then will show how these models can be used in the simulation of analog circuits, explaining the issues to overcome and the solutions that can be adopted. With these accurate models and capable circuit simulation techniques, the picture ends with a proposal for an analog design methodology that, using advanced optimization techniques, can successfully take into accounts all sources of variations (process and aging related) so that reliable analog circuits can be attained.
Reliability in the analog flow: from characterization and modeling to design automation
R. Castro-López
Conference · Int. Workshop on Design Automation for Analog and Mixed-Signal Circuits 2017
resumen
Abstract not avaliable
Efficient Computation of Yield and Lifetime for Analog ICs under Process Variabiliy and Aging
A. Toro-Frías, P. Martin-Lloret, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2017
resumen
With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability (i.e., spatial or process variability) but also the degradation due to time-dependent variability (i.e., aging). While process variability has been extensively treated, solutions to cope with aging-related problems are, nowadays, not yet mature enough, especially in the field of analog circuit simulation. Nevertheless, considerable efforts are currently being made to develop new simulation tools and simulation methodologies to evaluate the impact of reliability effects. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.
Statistical characterization of reliability effects in nanometer CMOS using a versatile transistor array IC
J. Díaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca, F.V. Fernández, E. Barajas-Ojeda, X. Aragones and D. Mateo-Peña
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2017
resumen
In this work, an experimental framework for the characterization of various reliability effects in modern CMOS technologies is described. The main element in this framework is a versatile transistor array chip, designed to accurately characterize process variability, Random Telegraph Noise and BTI/HCI related time dependent variability effects. The measurement setup, the other element in the framework, has been designed to take full advantage of the array architecture, which allows parallel testing of its 3136 MOS transistors, thereby reducing considerably the total measurement time. Thanks to a control toolbox and a user-friendly GUI, the setup also facilitates the programming of any of the required characterization tests.
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca, F.V. Fernandez, E. Barajas, X. Aragones and D. Mateo
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen
In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.
Statistical characterization of unreliability effects in a 65-nm CMOS transistor array
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · International Mixed-Signals Testing Workshop IMSTW 2017
resumen
In this work, a CMOS transistor array is presented which enables characterization of variability, Random Telegraph Noise and BTI/CHC aging. The array integrates 3,136 MOS transistors for massive electrical testing. This array, together with a dedicated test setup with graphical interface feature easy programming of the required characterization tests, visualization of results and post-processing algorithms for the defect characterization required in aging modeling and simulation.
A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs
P. Martín-Lloret, A. Toro-Frías, J. Martin, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
resumen
Variability is one of the main and critical challenges introduced by the continuous scaling in integrated technologies and the need for reliable ICs. In this regard, it is necessary to take into account time-zero (i.e., spatial or process variability) and time-dependent variability (i.e., aging). While process variability has been extensively treated, considerable efforts are currently being made to develop new simulation tools to evaluate the impact of aging, but very few works have been focused on reliability simulation for analog ICs. Most of the up to day models focused on the aging phenomena make use of the stress conditions of the analog circuit during its normal operation. However, many of the available solutions often miss the bi-directional link between stress and biasing and their changes over time and, therefore, accuracy losses occurs while evaluating the impact of aging in the circuit performance. This paper proposes a new size-adaptive time-step algorithm to efficiently update the stress conditions in the reliability simulation of analog ICs. Compared to similar solutions, the work presented here is able to attain similar accuracy levels with lower computational budgets.
Including a stochastic model of aging in a reliability simulation flow
A. Toro-Frías, P. Martin-Lloret, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen
The availability and efficiency of reliability simulators for analog ICs is becoming critical with the scaling of devices down to the nanometer nodes. Two of the main challenges here are how to simultaneously include different sources of unreliability (such as the time-zero or spatial variability and the aging or time-dependent variability), and how to account for the self-induced changes in device biasing (i.e., stress conditions) caused by the device wear-out. In addition to the already existing stochastic models for time-zero variability, new models for the stochastically-distributed aging mechanisms have been developed in recent years. The combination of these challenges with the need for dealing with a stochastic model for aging, causes a serious computational load issue. This paper presents different methods to accurately include reliability in the simulation of analog ICs while preventing the simulation to become unaffordable in terms of CPU time and load.
A strategy to efficiently include electromagnetic simulations in optimization-based RF circuit design methodologies
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, J. Sieiro, and J.M. López-Villegas
Conference · IEEE MTT-S Int. Conf. on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and Terahertz Applications NEMO 2017
resumen
The use of electromagnetic simulations is crucial in radiofrequency and microwave circuits since accurate estimations of parasitics and performances are essential. In addition, design methodologies based on optimization algorithms have been used in order to design such circuits, while efficiently exploring its design trade-offs. However, due to the high computational cost, optimization-based methodologies seldom use electromagnetic simulation. In order to overcome this issue, this paper demonstrates an optimization-based design methodology for radiofrequency circuits which can incorporate electromagnetic simulations without efficiency loss.
Systematic design of a voltage controlled oscillator using a layout-aware approach
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, R. Martins, N. Lourenço, R. Póvoa, A. Canelas and N. Horta
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen
This paper focuses on the systematic design of voltage controlled oscillators (VCO), a commonly used radiofrequency (RF) electronic circuit. RF circuits are among the most difficult analog circuits to design due to its trade-offs and high operation frequencies. At such operation frequencies, layout parasitics and accurate passive component characterization become of upmost importance, causing re-design iterations if they are not considered by the designer. To avoid this problem, and reduce the design time, this paper presents a systematic design of a VCO, entailing layout parasitics and accurate characterization of passive components from early design stages. Results clearly illustrate the benefit of this strategy.
An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Conference · IEEE Congress on Evolutionary Computation CEC 2017
resumen
This paper describes a class of real-life optimization problems that has not been addressed before: a multi-objective optimization in which one objective is neither minimized nor maximized but uniformly swept over a wide range. The limitations of conventional multi-objective optimization algorithms to deal with this kind of problems are illustrated via the optimization of radiofrequency inductors. For the first time, an algorithm is proposed that provides sets of solutions for this kind of problems.
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks
R. Martins, N. Lourenço, R. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca and F.V. Fernández
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen
In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most established computer-aided design tools available nowadays, i.e., off-the-shelf circuit simulator, electromagnetic simulator and layout extractor. The approach intends to bypass the two major bottlenecks of RF-design: the design of reliable integrated inductors and accurate layout parasitic estimates since the early stages of design process.
CASE: A reliability simulation tool for analog ICs
P. Martín-Lloret, A. Toro-Frías, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen
With the evolution in the scale of integration in ICs, aging-related problems are becoming more important and, nowadays, solutions to cope with these issues are not yet mature enough, especially in the field of analog circuit simulation. CASE, the novel simulator presented in this paper, can evaluate the impact of reliability effects in analog circuits through a stochastic physic-based model. The implemented simulation flow is accurate and efficient in terms of CPU. The two main improvements over currently reported and commercial tools, is that the simulator can simultaneously take into account both time-zero and time-dependent variability, and that an adaptive method, to account for the strong link between biasing and stress, can improve the accuracy while keeping acceptable CPU times.
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization
N. Lourenço, R. Martins, R. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca and F. V. Fernández
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen
This paper presents new indexing and mutation operators, in the context of bottom-up hierarchical multi-objective optimization of radio frequency integrated circuits, for pre-optimized sets of solutions from the hierarchical sub-levels when moving up in hierarchy. Two ideas, one based on a Voronoi decomposition and another based on the nearest neighborhood, are explored, where, and unlike previous approaches that are based on sorting, the distance between elements determines the probability of decisions taken during optimization. Three implementations of those ideas were tried in AIDA's NSGAII evolutionary kernel, and successfully used in the optimization of a Voltage Controlled Oscillator and a Low Noise Amplifier with pre-optimized inductor sets obtained using the SIDeO toolbox, showing their strengths when compared to previous state-of-the-art mapping strategies.
TARS: A toolbox for statistical reliability modeling of CMOS devices
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen
This paper presents a toolbox for the automation of the electrical characterization of CMOS transistors. The developed software provides a user-friendly interface to carry out different tests to evaluate time-zero (i.e., process) and time-dependent variability in CMOS devices. Also, the software incorporates a post-processing capability that allows users to visualize the data. Moreover, without loss of generality, the toolbox allows the user, from the measured data, to feed a particular physics-based model that accounts for various aging phenomena.
Dependence of MOSFETs threshold voltage variability on channel dimensions
C. Couso, J. Diaz-Fortuny, J. Martin-Martinez, M. Porti, R. Rodriguez, M. Nafria, F.V. Fernandez, E. Roca, R. Castro-Lopez, E. Barajas, D. Mateo and X. Aragones
Conference · Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2017
resumen
The dependence of the MOSFET threshold voltage variability on device geometry (width (W) and length (L)) has been studied from experimental data. Our results evidence, in agreement with other works, deviations from the Pelgrom's rule, especially in smaller technologies. TCAD simulations were also performed which further support the experimental data and provide physical information regarding the origin of such deviation. Finally, a new empirical model that assumes different impact of W and L in the device variability has been proposed, which reproduces the experimental results.
A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs
P. Martín, A. Toro, R. Castro, E. Roca, F.V. Fernández, J. Martín-Martínez and M. Nafría
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
resumen
Variability is one of the main and critical challenges introduced by the continuous scaling in integrated technologies and the need for reliable ICs. In this regard, it is necessary to take into account time-zero (i.e., spatial or process variability) and time-dependent variability (i.e., aging). While process variability has been extensively treated, considerable efforts are currently being made to develop new simulation tools to evaluate the impact of aging, but very few works have been focused on reliability simulation for analog ICs. Most of the up to day models focused on the aging phenomena make use of the stress conditions of the analog circuit during its normal operation. However, many of the available solutions often miss the bi-directional link between stress and biasing and their changes over time and, therefore, accuracy losses occurs while evaluating the impact of aging in the circuit performance. This paper proposes a new size-adaptive time-step algorithm to efficiently update the stress conditions in the reliability simulation of analog ICs. Compared to similar solutions, the work presented here is able to attain similar accuracy levels with lower computational budgets.
Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms
M. Velasco-Jiménez, R. Castro-López and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
resumen
This demo shows how to use multi-objective evolutionary algorithms for the optimum high-level design of ΣΔ analog-to-digital converters. The methodology illustrated in the demo is based on the combination of SIMSIDES, a SIMULINK-based time-domain behavioral simulator for ΣΔ modulators, with multi-objective optimization techniques. The proposed methodology allows designers to explore the design space in an efficient and intuitive way in order to fulfill a number of different design objectives simultaneously, by finding out the best sets of target specifications - defined as Pareto-optimal fronts. The presented approach can be extended to several kinds of optimizers implemented in MATLAB, and diverse examples are illustrated so that visitors will learn how to apply it to their own designs and projects. Although the demo is focused on ΣΔ ADCs, the tools shown in the demo can be used for the optimization of any other analog integrated circuits and systems.
SIDe-O: A Toolbox for Surrogate Inductor Design and Optimization
F. Passos, E. Roca, R. Castro-López, F. V. Fernández
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2016
resumen
This paper presents SIDe-O, a CAD tool developed for the design and optimization of integrated inductors based on surrogate modeling techniques. This tool provides a solution to the problem of accurately and efficiently optimizing the design of inductors. The models used present less than 1% error when compared to EM simulations while reducing the simulation time by several orders of magnitude. Additionally, the tool provides the ability to create new surrogate models for different technologies and inductor topologies. The tool also allows the creation of an S-Parameter file that accurately describes the behavior of the inductor for a given range of frequencies, which can later be used in SPICE-like simulations.
Frequency-Dependent Parameterized Macromodeling of Integrated Inductors
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, Y. Ye, D. Spina and T. Dhaene
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2016
resumen
Integrated inductors are one of the most important passive elements in radio frequency design, due to their wide usage in wireless communication circuits. Typically, electromagnetic simulators are used in order to estimate the inductors performance with high accuracy as a function of the inductor geometrical and electrical parameters. Such simulations offer high-accuracy, but are computationally expensive and extremely time consuming. In this paper, a frequency-dependent parameterized macromodeling technique is adopted in order to overcome this problem. The proposed approach offers a high degree of automation, since it is based on sequential sampling algorithms, high efficiency and flexibility: a continuous frequency-domain model is given for each value of the chosen inductors parameters in the design space.
High-Level Optimization of Sigma-Delta Modulators using Multi-Objetive Evolutionary Algorithms
M. Velasco-Jiménez, R. Castro-López and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems, ISCAS 2016
resumen
This paper presents a high-level synthesis methodology based on the use of multi-objective evolutionary algorithms for the optimization of Sigma-Delta (SD) modulators. Compared to conventional approaches, the proposed method allows to explore a number of different design objectives simultaneously in the design space in order to find out the best sets of target specifications -- defined as Pareto-optimal fronts. This strategy leads to more efficient designs in terms of effective resolution, bandwidth and power consumption. As an application, the proposed method is applied to the high-level design of a 65-nm CMOS LC-based fourth-order band-pass continuous-time SD modulator, showing a number of experiments to validate the presented approach.
Accurate Synthesis of Integrated RF Passive Components using Surrogate Models
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López and F.V. Fernández
Conference · Design, Automation and Test in Europe DATE 2016
resumen
Passive components play a key role on the design of RF CMOS integrated circuits. Their synthesis, however, is still an unsolved problem due to the lack of accurate analytical models that can replace the computationally expensive electromagnetic simulations (EM). Both, physical-based and surrogate models have been reported that fail to accurately model the complete design space of inductors. Surrogate-assisted optimization techniques, where coarse models are locally enhanced during the inductor synthesis process by using new EM-simulated points to update the model, have been proposed, but either the efficiency is dramatically decreased due to the online EM simulations or the optimization may converge to suboptimal regions. In this paper, we present a new surrogate model, valid in the entire design space with less than 1% error when compared with EM simulations. This model can be generated offline, and, when embedded within an optimization algorithm, allows the synthesis of integrated inductors with high accuracy and high efficiency, reducing the synthesis time in three orders of magnitude.
Aplicación de algoritmos evolutivos multiobjectivo al diseño de circuitos integrados: criterios de detención
E. Roca, R. Castro-Lopez and F.V. Fernández
Conference · Congreso Español de Metaheurísticas, Algoritmos Evolutivos y Bioinspirados MAEB 2015
resumen
Abstract not avaliable
A Fast and Accurate Reliability Simulation Method for Analog Circuits
A. Toro-Frias, R. Castro-Lopez, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
resumen
Reliability has become a critical challenge in integrated circuit design in today's CMOS technologies. Aging problems have been added to the well-known issues due to spatial variations that are caused by imperfections in the fabrication process. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers (HC) cause a time-dependent variability that is added to the spatial variability. In addition, the BTI presents a stochastic behaviour, which may cause, for instance, time-varying mismatch. In this work, a model based on the physics of this phenomenon is implemented to accurately know its impact on the circuit performances. This method is focused on the analysis of analog circuits, taking into account the impact of both temporal and spatial variability. An effient simulation flow is implemented to evaluate the circuit performance at any instant of the circuit lifetime.
Transformation conditions of performance fronts of operational amplifiers
E. Roca, R. Castro-Lopez, M. Velasco-Jiménez and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
resumen
Pareto fronts of circuits whose performance depend on other circuits that they are connected to must be updated for each interconnection conditions. This paper reports, for the first time, the conditions for which a transformation without loss of information is guaranteed.
Surrogate Modeling and Optimization of Inductor Performances using Kriging functions
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
resumen
Integrated inductors are one of the most important passive elements in RF circuits. However, time-consuming simulations, such as electromagnetic simulations, have to be used to evaluate their performances with high accuracy. In order to overcome this problem, analytical models can be used. In this paper, a surrogate model based on Kriging functions is presented that accurately predicts the performance parameters of integrated inductors. The different approaches followed to obtain the model are presented. Finally, the model is linked to an evolutionary algorithm to optimize inductor performances.
A simulation methodology for the reliability-aware design of analog circuits
A. Toro, R. Castro-López, E. Roca, F.V. Fernández, J. Martín-Martinez, R. Rodriguez and M. Nafria
Conference · International Mixed-Signals Testing Workshop IMSTW 2015
resumen
With the scale of integration of modern transistors entering the atomic size and an increase of the gate-oxide
field, reliability of electronic circuits is today more demanding than ever. Both spatial (i.e., process)
variations and time-dependent (i.e., aging) variations dramatically reduce the yield and shortens the circuit
lifetime, which prompt for reliability aspects to be considered in the design flow in order to attain resilient
circuits featuring longer lifetimes. Aging effects such as as Bias Temperature Instability (BTI) and Hot
Carriers Injection (HCI) should be included just as well as process variations are.
Design Space Exploration using Hierarchical Composition of Performance Models
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2015
resumen
Bottom-up synthesis approaches based on the hierarchical composition of performance models have been proposed as a promising alternative to conventional top-down hierarchical synthesis approaches. This paper discusses problems related to the context-dependence of performance models and proposes possible solutions. Techniques for the composition of multi-dimensional performance models so that the efficiency of the design space exploration is maximized are also discussed. An active filter is used to demonstrate the accuracy and efficiency of the techniques discussed here.
Physical vs. Surrogate Models of Passive RF Devices
F. Passos, M. Kotti, R. González-Echevarría, M.H. Fino, M. Fakhfakh, E. Roca, R.Castro-López and F.V. Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2015
resumen
The accuracy of high-frequency models of passive RF devices, e.g., inductors or transformers, presents one of the most challenging problems for RF integrated circuits. Accuracy limitations lead RF designers to time-consuming iterations with electromagnetic simulators. This paper will explore and compare two advanced modeling techniques. The first one is based on the segmented model approach, in which each device segment is characterized with a lumped element model. The second technique is based on the generation of surrogate models from the electromagnetic simulation of a set of device samples. Different modeling strategies (frequency separation, filtering according to self-resonance frequency, etc.) will be considered. Efficiency and accuracy of both, physical and surrogate, modeling techniques will be compared using a Si process technology.
Hierarchical Composition of Pareto-Optimal Fronts of Analog Circuits: Implementation Issues
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2014
resumen
The use of Pareto-optimal fronts (PoFs) is becoming key in the development of new hierarchical design methodologies that aim to reduce the bottleneck in the design of analog and mixed-signal systems caused by the design of the analog components. An important aspect of these new methodologies, the hierarchical composition of lower-level PoFs, has received little attention in the literature. This composition presents two key issues. The first issue is the context-dependent performances of analog circuits, which obligate to re-evaluate the PoFs of these circuits when their surrounding circuitry changes. The second issue is related to how multi-dimensional low-level PoFs are used when generating the PoFs of high-level blocks so that the efficiency of the design space exploration is not affected. This work presents new mechanisms that can be used to solve both issues. The generation of the performance model of an active filter by hierarchical composition of previously generated PoFs of operational amplifiers is used to demonstrate the validity of the approaches presented here.
Doubly-Segmented Current-Steering DAC Calibration
G. Léger
Conference · Design and Technology of Integrated Systems in Nanoscale Era DTIS 2014
resumen
This paper addresses the calibration of segmented current-steering Digital-to-Analog Converters (DACs). In many design cases, current-steering DACs are divided into a thermometer-coded unary section and a binary section. This is done mostly for dynamic reasons. However, the decisions on the segmentation also impact an eventual static calibration. In this paper, we show that the introduction of an intermediate thermometer-coded unary section allows to perform static calibration to a high resolution levels without compromising the dynamic behavior. The individual current sources of the two unary sections are calibrated against two current references and the gain mismatch between sections is calibrated through the biasing circuit.
Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference · Design Automation and Test in Europe DATE 2014
resumen
Emerging hierarchical design methodologies based on the use of Pareto-optimal fronts (PoFs) are promising candidates to reduce the bottleneck in the design of analog circuits. However, little work has been reported about how to transmit the information provided by the PoFs of low hierarchical level blocks through the hierarchy to compose the performance models of higher-level blocks. This composition actually poses several problems such as the dependence of the PoF performances on the surrounding circuitry and the complexity of dealing with multi-dimensional PoFs in order to explore more efficiently the design space. To deal with these problems, this paper proposes new mechanisms to represent and select candidate solutions from multi-dimensional PoFs that are transformed to the changing operating conditions enforced by the surrounding circuitry. These mechanisms are demonstrated with the generation of the performance model of an active filter by composing previously generated PoFs of operational amplifiers.
Systematic Generation of Performance Models of Reconfigurable Analog Circuits
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
resumen
pdf
In this work, a systematic technique to generate performance
models of reconfigurable analog circuits is presented.
The performance models are obtained in the form of multi-mode
Pareto-optimal fronts (mm-PoFs), a new type of Pareto-optimal
front (PoF) that characterizes the set of different performances
that reconfigurable circuits can attain. The technique is based
on the use of an evolutionary algorithm (EA) that acts as an
optimizer, and the simulator HSPICE to measure the circuit
performances. The use of this technique will be illustrated for a
wireless multistandard problem, where a reconfigurable op-amp
will be considered.
Surrogate models of Pareto-optimal planar inductors
M. Kotti, R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, M. Fakhfakh, J. Sieiro and J.M. López-Villegas
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
resumen
pdf
Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is obtained by embedding an electromagnetic simulator into a multi-objective optimization tool. Then, starting from the obtained optimal samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35 μm CMOS technology are provided.
New approaches to bridge the design gap of analog and RF circuits
F.V. Fernández, E. Roca and R. Castro-López
Conference · International Conference on Analog VLSI Circuits AVIC 2012
resumen
The increasing gap between IC complexity and the capacity to deal with it in the design process is worrisome. Design productivity has and must be improved in this sense. The picture is even worse for analog, mixed-signal and radiofrequency circuits due to the lesser development of commercial CAD tools and methodologies with respect to their digital counterparts. From the several directions proposed to bridge this gap, this talk will focus on two of them: improving existing hierarchical synthesis methods and reducing the iterations between separate design stages.
An Automated Layout-Aware Design Flow
A. Toro-Frías, R. Castro-López, E. Roca and F.V. Fernández
Conference · Int. Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
resumen
In analog integrated circuit design, it has always been necessary to improve the designer's productivity. The iterations between the electrical and physical synthesis, required to correct deviations due to parasitics, do degrade that productivity. The inclusion of the physical implementation directly within the electrical synthesis process, would in principle remove many or all of these iterations. This paper presents a fully-automated layout-aware design flow, whose key aspects are: (1) it uses commercially available tools and platforms to attain a highly integrated solution, (2) it provides solutions in the form of Pareto-optimal fronts, which represent the circuit's valuable trade-offs (and can be used in modern design flows), and (3) it allows including the impact of parasitics right into the fronts. This paper details the necessary tools and their integration for automation of the design flow and provides several examples of its use.
A fully automated design flow for planar inductors
R. González-Echevarría, R. Castro-López, E. Roca, F.V. Fernández, J.M. López-Villegas and J. Sieiro
Conference · Int. Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
resumen
Integrated inductors performances are difficult to model due to the parasitic effects present at high frequencies. Typically, RF designers use electromagnetic simulation during the design flow to tune their circuits until all designs requirements are fulfilled or use the set of, not always conveniently tuned, inductors provided by the foundries. In this paper, a multi-objective optimization algorithm is combined with a full-wave electromagnetic evaluator to obtain a tool for synthesis of inductors with optimum performance trade-offs. The automation of layout generation and simulation tasks are described in details.
Layout-aware Pareto fronts of electronic circuits
A. Toro-Frías, R. Castro-López, E. Roca and F.V. Fernández
Conference · European Conference on Circuit Theory and Design ECCTD 2011
resumen
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Pareto-optimal performance fronts have gained popularity as a representation of performance trade-offs of electronic circuits. They are also essential to support efficient bottom-up hierarchical design methodologies. Being such a key element in these methodologies, there have been many reported efforts to enhance the fronts with valuable information that goes beyond the nominal circuit behavior, such as the yield or the reconfiguration capabilities. However, the effect of layout parasitics is the factor that has been missing in the literature: the accuracy may be seriously degraded by layout parasitics not considered during the front generation. In this paper, we present a technique to generate layout-aware Pareto fronts that accurately accounts for the impact of both geometry and parasitics. © 2011 IEEE.
Load-Independent Characterization of Trade-Off Fronts for Operational Amplifiers
E. Roca, M. Velasco-Jiménez, R.l Castro-López and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
resumen
pdf
In emerging design methodologies for analog integrated circuits, the use of performance trade-off fronts, also known as Pareto fronts, is a keystone to overcome the limitations of the traditional top-down methodologies. However, most techniques reported so far to generate the front neglect the effect of the surrounding circuitry (such as the output load impedance) on the Pareto-front, thereby making it only valid for the context where the front was generated. This strongly limits its use in hierarchical analog synthesis because of the heavy dependence of key performances on the surrounding circuitry, but, more importantly, because this circuitry remains unknown until the synthesis process. We will address this problem by proposing a new technique to generate the trade-off fronts that is independent of the load that the circuit has to drive. This idea is exploited for a commonly used circuit, the operational amplifier, and experimental results show that this is a promising approach to solve the issue.
A Pareto-based systematic design technique for reconfigurable analog circuits using an evolutionary optimization algorithm
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
resumen
Abstract not avaliable
A bottom-up approach to the systematic design of LNAs using evolutionary optimization
C. Sánchez-López, R. Castro-López, E. Roca, F.V. Fernández, R. González-Echevarría, J. Esteban-Muller, J.M. López-Villegas, J. Sieiro and N. Vidal
Conference · International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2010
resumen
A systematic design methodology for low-noise amplifiers (LNAs) is introduced. This methodology follows a bottom-up approach that employs a multi-objective evolutionary optimization algorithm, which is used at two levels. First, it is used to generate Pareto-based performance models for integrated planar inductors. To do so, an electromagnetic simulator that takes into account the inductor's layout, thus providing highly accurate performance evaluations, is coupled to the optimizer. Unlike foundry-provided inductor libraries, these Pareto-based models offer a detailed insight of the trade-offs between inductance, quality factor and area. Afterwards the Pareto-based models for the inductors are used as design variables to generate the LNA Pareto surface, thus providing highly accurate performance trade-offs of the LNA.
Multi-objective performance optimization of planar inductors
J. Esteban-Muller, R. González-Echevarría, C. Sánchez-López, E. Roca, R. Castro-López, F.V. Fernández, J.M. López-Villegas, J. Sieiro and N. Vidal
Conference · Int. Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2010
resumen
pdf
Inductors play an essential role in the design of RF circuits. The parasitic effects plaguing integrated planar inductors require an accurate modeling and the careful exploration of their performance trade-offs. In this paper, a multi-objective performance modeling technique of planar inductors is presented, that supports both top-down and bottom-up design of RF circuits. ©2010 IEEE.
Context-independent performance modeling of operational amplifiers using Pareto fronts
E. Roca, M. Velasco-Jiménez, R. Castro-López and F.V. Fernández
Conference · Int. Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2010
resumen
pdf
The use of performance trade-off fronts, also known as Pareto fronts, in emerging design methodologies for analog integrated circuits is a keystone to overcome the limitations of the traditional top-down methodologies. However, most techniques reported so far to generate the fronts neglect the effect of the surrounding circuitry (such as the output load impedance) on the Pareto-front, thereby making it only valid for the context where the front was generated. This strongly limits its use in hierarchical analog synthesis because of the heavy dependence of key performances on the surrounding circuitry, but, more importantly, because this circuitry remains unknown until the synthesis process. We propose a new technique to generate the trade-off fronts that is independent of the load that the circuit has to drive. This idea is exploited for a Miller operational amplifier, and experimental results show that this is a promising approach to solve the issue. ©2010 IEEE.
Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors
F.V. Fernández, J. Esteban-Muller, E. Roca and R. Castro-López
Conference · International Conference on Evolutionary Computation CEC 2010
resumen
In this paper, the application of multi-objective evolutionary algorithms to the evaluation of performance trade-offs of planar inductors, an almost ubiquitous device in radio-frequency microelectronics, is studied. The absence of appropriate stopping criteria in most evolutionary algorithms reveals to be critical in this application. A new stopping criterion based on monitoring a set of performance metrics that account for convergence and diversity is proposed and demonstrated with practical radio-frequency circuit design problems.
Analog Layout Synthesis: Recent advances in topological approaches
H. Graeb, F. Balasa, R. Castro-López, Yao-wen Chang, F.V. Fernandez-Fernandez, Po-hung Lin and M. Strasser
Conference · Design Automation and Test in Europe Conference and Exhibition DATE 2009
resumen
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This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.
Applications of evolutionary computation techniques to analog, Mixed-signal and RF circuit design - an overview
E. Roca, M. Fakhfakh, R. Castro-López and F.V. Fernández
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2009
resumen
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This paper review. The application of evolutionary computation techniques to analog, mixed-signal and radio-frequency design problems. Design needs, limitations of existing approaches and open challenges are pointed out. © 2009 IEEE.
Hierarchical synthesis based on Pareto-optimal fronts
E. Roca, R. Castro-López and F.V. Fernández
Conference · European Conference on Circuit Theory and Design ECCTD 2009
resumen
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Pareto-optimal fronts have recently arisen as a promising alternative for design space exploration, potentially enabling better and more efficient hierarchical synthesis. This paper reviews the Pareto front generation problem, extends this concept to reconfigurable circuits, and discusses alternative applications to hierarchical synthesis approaches.
Using Pareto-optimal fronts in the design of reconfigurable data converters
R. Castro-López, E. Roca and F.V. Fernández
Conference · International Conference on Advances in Circuits, Electronics and Microelectronics CENICS 2009
resumen
Analog design is a bottleneck in the design of integrated circuits. A recently proposed method to cope with the complexity of analog design is the use of a multi-objective bottom-up flow, which makes use of the concept of Pareto-optimal front (POF) to capture performance trade-offs of analog components, and through which these can be exploited during top-down design of a complex (hierarchically-wise) analog circuit. In this paper, we describe a step forward and transform this technique, through a new type of front we call Multi-Mode Pareto-optimal Front, to design reconfigurable Analog-to-Digital Converters (ADCs). We demonstrate that not only design time is shortened but also that design complexity of reconfigurable circuits can be more systematically and efficiently managed.
Quality Metrics of Pareto-Optimal Fronts for Multi-Objective Synthesis of Analog ICs
F.V. Fernández, B. Liu, R. Castro-López and E. Roca
Conference · International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2008
resumen
Evolutionary computation (EC) techniques can be applied to synthesize analog integrated circuits via the Pareto dominance concept and multi-objective optimization. In order to find out which of the EC techniques available yields better results for analog circuit design, a set of metrics are required that compares and characterizes the Pareto-optimal fronts in terms of their analog design quality. In this paper, we select and classify existing, widely used quality metrics and propose new ones for analog multi-objective synthesis. Several experiments are used that back up the proposed metrics.
MSOEA: A New Methodology for Synthesis of High Performance Analog Integrated Circuits
B. Liu, F.V. Fernández, G. Gielen, R. Castro-López, E. Roca and J. Luo
Conference · Xth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2008
resumen
This paper introduces an evolution-based methodology, named memetic single objective evolutionary algorithm (MSOEA), for automated sizing of high performance analog integrated circuits. By combining operators from the differential evolution algorithm, the real-coded genetic algorithm, operators inspired by the simulated annealing algorithm, and a set of constraint handling techniques, MSOEA specializes on handling analog circuit synthesis problems with numerous and tight design constraints. The method has been tested on several analog circuits. Comparisons with available methods show that the proposed algorithm presents important advantages in constraint handling ability and optimization quality.
Hierarchical Design of Reconfigurable Analog Circuits using Multi-Mode Pareto Fronts
R. Castro-López, F.V. Fernández and E. Roca
Conference · Int. Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2008
resumen
Most reconfigurable analog integrated circuits reported follow an ad-hoc design approach, which do not guarantee neither efficient area occupation nor minimized power consumption for all operation modes. A clear example is the Analog-to-Digital Converter (ADC), used in multi-standard transceivers. This paper tries to formulate a hierarchical design approach based on the following elements: (1) An improved top-down synthesis with bottom-up generated low-level design information; (2) An original definition of the reconfiguration capabilities of the building blocks; (3) A optimization-based technique for the exploration of candidate architectures; (4) Last but not least, a clear definition of metrics for reconfigurability to measure how good is a design in terms its reconfiguration capabilities. This methodology is illustrated through the design of a multi-standard ΣΔ modulator.
Towards systematic design of multi-standard converters
V.J. Rivas, R. Castro-López, A. Morgado, O. Guerra, E. Roca, R. del Río, J.M. de la Rosa and F.V. Fernández
Conference · Conference on VLSI Circuits and Systems III, 2007
resumen
In the last few years, we are witnessing the convergence of more and more communication capabilities into a single terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements: (1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels, with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design information. The systematic design methodology is illustrated via the design of a multi-standard YEA modulator meeting the specifications of three wireless communication standards.
A design tool for high-resolution high-frequency cascade continuous-time sigma delta modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V Fernández
Conference · Conference on VLSI Circuits and Systems III, 2007
resumen
This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time (CT) cascade EA modulators. The salient features of this methodology are: (a) flexible behavioral modeling for optimum accuracy efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; and (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Sigma Delta modulator in a 1.2V 130nm CMOS technology.
A 12-bit CMOS current steering D/A converter for embedded systems
J. Ruiz-Amaya, M. Delgado-Restituto, J.F. Fernández-Bootello, D. Brandano, R. Castro-López and J.M. de la Rosa
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2006
resumen
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This paper describes the design of a 12-bit digital-to-analog converter for a wireline modem chip implemented in a 0.13 mu m digital CMOS technology. Transistor-level simulations from extracted layout at the nominal modem data rate of 80MS/s show an Spurious-Free Dynamic-Range (SFDR) better than 62dB at Nyquist rate under industrial operation conditions (40 to 85 degrees temperature range and +/- 10% supply variations) and for all technology process corners. Additionally, the converter achieves a Multi-Tone Power Ratio (MTPR) higher than 59dB for different Discrete MultiTone (DMT) test patterns consisting of 1536 carriers that fall in the Nyquist band. Simulation results at a higher data rate of 200MS/s are also shown in the paper. The converter dissipates less than 150mW from a mixed 3.3/1.2V supply and occupies less than 1.7mm(2).
A reuse-based framework for the design of analog and mixed-signal ICs
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
resumen
Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.
Geometrically-constrained, parasitic-aware synthesis of analog ICs
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
resumen
In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very timeconsuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenaRío is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.
On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
resumen
Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.
Description Languages and Tools for Behavioural Simulation of ΣΔ Modulators: a Comparative Survey
R. Castro-López, J. Ruiz-Amaya, J.M. de la Rosa, R. Romay, R. del Río, F. Medeiro, F.V. Fernández, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Forum on Specification & Design Languages FDL 2003
resumen
Abstract not available
Behavioural modelling and simulation of sigma delta modulators using hardware description languages
R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2003
resumen
Behavioural simulation is the common alternative to the costly electrical simulation of SigmaDelta modulators (EAMs). This paper explores the behavioural modelling and simulation of SigmaDeltaMs by using hardware description languages (HDLs) and commercial behavioural simulators,, as an alternative to the common special-purpose behavioural simulators. A library of building blocks, where a HDL has been used to model a complete set of circuit non-idealities influencing the performance of SigmaAMs, is introduced. Three alternatives for introducing SigmaDeltaM topologies have been implemented Experimental results of the simulation of a fourth-order 2-1-1 cascade multi-bit YAM are given.
Accurate VHDL-based simulation of sigma delta modulators
R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
resumen
Computational cost of transient simulation of SigmaDelta modulators (SigmaDeltaMs) at the electrical level is prohibitively high. Behavioral simulation techniques arise as a promising solution to this problem. This paper demonstrates that both, hardware description languages (HDLs) and commercial HDL simulators, constitute a valuable alternative to traditional special-purpose SigmaDelta behavioral simulators. In this sense, a library of HDL building blocks, modeling a complete set of circuit non-idealities which influence the performance of SigmaDeltaMs, is presented. With these blocks, SigmaDeltaM architectures can be described in two different ways, which are analyzed in detail. Experimental results are provided through several simulations of a fourth-order 2-1-1 cascade multi-bit SigmaDeltaM.
Generation of technology-portable flexible analog blocks
R. Castro-López, F.V. Fernández, M. Delgado-Restituto, F. Medeiro and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen
This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even to different technology processes. By careful integration of the tuning process of design parameters with layout generation, fully functional designs are generated in a few minutes of CPU time.
Libros
Automated Hierarchical Synthesis of Radio-Frequency Integrated Circuits and Systems. A Systematic and Multilevel Approach
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Book · 204 p, 2020
resumen
link
This book describes a new design methodology that allows optimization-based synthesis of RF systems in a hierarchical multilevel approach, in which the system is designed in a bottom-up fashion, from the device level up to the (sub)system level. At each level of the design hierarchy, the authors discuss methods that increase the design robustness and increase the accuracy and efficiency of the simulations. The methodology described enables circuit sizing and layout in a complete and automated integrated manner, achieving optimized designs in significantly less time than with traditional approaches.
- Describes an efficient and accurate methodology to design automatically RF systems, with guaranteed accuracy from the device to the system level.
- Discusses analytical and machine learning techniques for modelling integrated inductors and uses such models in synthesis approaches.
- Compares synthesis strategies for RF circuits based on bottom-up versus flat approaches.
- Discusses layout-aware bottom-up design methodologies for RF circuits.
- Discusses variability-aware bottom-up design methodologies for RF circuits.
- Describes multilevel bottom-up design methodologies from the device up to the system level.
Analog/RF and Mixed-Signal Circuit Systematic Design
M. Fakhfakh, E. Tlelo-Cuautle and R. Castro-López (Eds.)
Book · LNEE, vol. 233, 381 p, 2013
resumen
link
Despite the fact that in the digital domain, designers can take full benefits of IPs and design automation tools to synthesize and design very complex systems, the analog designers' task is still considered as a 'handcraft', cumbersome and very time consuming process. Thus, tremendous efforts are being deployed to develop new design methodologies in the analog/RF and mixed-signal domains.
This book collects 16 state-of-the-art contributions devoted to the topic of systematic design of analog, RF and mixed signal circuits. Divided in the two parts Methodologies and Techniques recent theories, synthesis techniques and design methodologies, as well as new sizing approaches in the field of robust analog and mixed signal design automation are presented for researchers and R/D engineers.
Reuse-Based Methodologies And Tools in the Design of Analog and Mixed-Signal Integrated Circuits
R. Castro-López, F.V. Fernández-Fernández, O. Guerra-Vinuesa and A. Rodríguez-Vázquez
Book · 393 p, 2006
resumen
link
Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits under stringent time-to-market requirements is lagging behind integration capacity, so far keeping pace with still valid Moore Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools, design methodologies and even a design paradigm shift, that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design -more subtle, hierarchically loose, and handicraft-demanding- has hindered a similar level of consensus and development.
Aiming at the core of the problem, Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the first two for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks.
Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits features a very detailed, tutorial, and in-depth coverage of all issues and must-have properties of reusable AMS blocks, as well as a thorough description of the methods and tools necessary to implement them. For the first time, this has been done hierarchically, covering one by one the different stages of the design flow, allowing us to examine how the reusable block yields its benefits, both in design time and correct performance.
Capítulos de libros
On the usage of machine-learning techniques for the accurate modeling of integrated inductors for RF applications
F. Passos, E. Roca, R. Castro-Lopez and F.V. Fernandez
Book Chapter · Modelling Methodologies in Analogue Integrated Circuit Design, pp 155-178, 2020
resumen
doi
This chapter describes an inductor modeling strategy based on machine-learning techniques. The model developed is based on Kriging functions and uses a novel modeling technique based on a two-step strategy, which is able to obtain an extremely accurate model with less than 1% error when compared to electromagnetic (EM) simulations. Due to its extreme accuracy and efficiency, the model can be used in inductor synthesis processes using single- or multi-objective optimization algorithms in order to obtain a single design or a Pareto-optimal front. Also, the model can describe the inductor behavior in frequency and therefore can also be used in circuit design using modern electrical simulators. This chapter discusses both applications (inductor synthesis and circuit design), performing several singleand multi-objective inductor optimizations, using different inductor topologies and operating frequencies. Furthermore, the model is also used in order to accurately model inductors during the design of a voltage-controlled oscillator (VCO) and a low-noise amplifier (LNA).
Modeling of variability and reliability in analog circuits
J. Martin-Martinez, J. Diaz-Fortuny, A. Toro-Frias, P. Martin-Lloret, P. Saraza-Canflanca, R. Castro-Lopez, R. Rodriguez, E. Roca, F.V. Fernandez and M. Nafria
Book Chapter · Modelling Methodologies in Analogue Integrated Circuit Design, pp 179-206, 2020
resumen
doi
This chapter is divided into four sections. In Section 8.1, the probabilistic defect occupancy (PDO) model, a physics-based compact model, is introduced, which can be easily implemented into circuit simulators. Section 8.2 describes a purposely designed IC which contains suitable test structures, together with a full instrumentation system for the massive characterization of TZV and TDV in CMOS transistors, from which aging of the technology under study can be statistically evaluated. Section 8.3 is devoted to a smart methodology, which allows extracting the statistical distributions of the main physical parameters related to TDV from the measurements performed with the instrumentation system. Finally, Section 8.4 describes CASE, a new reliability simulation tool that accounts for TZV and TDV in analog circuits, covering important aspects, such as the device degradation evaluation, by means of stochastic modeling and the link between the device biasing and its degradation. As an example, the shifts of the performance of a Miller operational amplifier related to the device TDV is evaluated using CASE. Finally, in Section 8.5 the main conclusions are summarized.
Computational Intelligence Techniques for Determining Optimal Performance Trade-Offs for RF Inductors
E. Roca, R. Castro-López, F.V. Fernández, R. González-Echevarría, J. Sieiro, N. Vidal and J.M. López-Villegas
Book Chapter · Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp 277-296, 2015
resumen
doi
The automatic synthesis of integrated inductors for radio frequency (RF) integrated circuits is one of the most challenging problems that RF designers have to face. In this chapter, computational intelligence techniques are applied to automatically obtain the optimal performance trade-offs of integrated inductors. A methodology is presented that combines a multi-objective evolutionary algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. The methodology is illustrated with a complete set of examples where different inductor trade-offs are obtained.
Symbolic Pole/Zero Analysis
F.V. Fernández, C. Sánchez-López, R. Castro-López and E. Roca
Book Chapter · Design of Analog Circuits through Symbolic Analysis, pp 287-304, 2012
resumen
doi pdf
Extraction of pole/zero expressions as a function of circuit parameters has traditionally been an essential tool for designers. In this Chapter, the main specific techniques for symbolic pole/zero extraction are described and their pros and cons are discussed. The application of the different techniques is illustrated with experimental results on practical circuits.
Approximation Techniques in Symbolic Circuit Analysis
F.V. Fernández, C. Sánchez-López, R. Castro-López and E. Roca
Book Chapter · Design of Analog Circuits through Symbolic Analysis, pp 173-201, 2012
resumen
doi pdf
Symbolic circuit analysis suffers from the exponential growth of expression complexity with circuit size. Therefore, either if the symbolic expressions are used for gaining insight into circuit operation or for repetitive computer-based evaluations, simplification becomes mandatory. This chapter reviews the different existing techniques for symbolic expression simplification, classifying them into three categories according to the step at which the simplification is performed: on the circuit equations, during the solution of the circuit equations or after the circuit equations have been solved. Pros and cons of each approach are discussed.
Closing the gap between electrical and physical design: the layout-aware solution
R. Castro-López, E. Roca and F.V. Fernández
Book Chapter · Analog layout synthesis. A Survey of Topological Approaches, pp 243-268, 2011
resumen
doi pdf
Iterations between separate phases in any procedural design process, usually a by-product of unexpected (or, simply, very complex to consider) adverse effects, clearly play against any time-to-market requirements. In analog integrated circuit (IC) design, going back and forth between electrical and physical synthe- sis to counterbalance layout-induced performance degradations needs to be thus avoided as much as possible. One possible solution involves the integration of the 1 traditionally separated electrical and physical synthesis phases, by including layout- induced effects, in the form of layout parasitics, right into the electrical synthesis phase, in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of the occu- pied area or fulfillment of certain layout aspect ratio, among others), whose effects on the resulting parasitics are not usually considered during electrical synthesis. In this chapter, a layout-aware solution that tackles both geometric and parasitic-aware electrical synthesis is proposed. This technique uses a combination of simulation- based optimization, procedural layout generation, exhaustive geometric evaluation algorithms, and several mechanisms for parasitic estimation. Thanks to the nature of this combination, the solution benefits from, and also fosters, reuse of analog intellectual property (IP) blocks. Several detailed design examples are provided.
Mixed analogue/digital and RF
R. Castro-López and F.V. Fernández-Fernández
Book Chapter · Medea + Design Automation Roadmap, pp 105-122, 2005
resumen
Abstract not available
Design methodologies for sigma-delta converters
F.V. Fernández, R. del Río, R. Castro-López, F. Medeiro and B. Pérez-Verdú
Book Chapter · CMOS Telecom Data Converters, pp 523-559, 2003
resumen
doi
Oversampling converters have become very popular due to their ability to solve problems found in other architectures, like the need for high-accuracy analog antialiasing filtering and the large sensitivity to circuit imperfections and noisy environments.
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