Encontrados resultados para:
Autor: Piedad Brox Jiménez
Año: Desde 2002
Artículos de revistas
Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management
S. Sánchez-Solano, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 24, no. 17, article 5674, 2024
resumen
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The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4
configurable logic blocks (CLBs) to accommodate the RO bank.
Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 7, no.2, article 29, 2023
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The advent of quantum computing with high processing capabilities will enable brute force attacks in short periods of time, threatening current secure communication channels. To mitigate this situation, post-quantum cryptography (PQC) algorithms have emerged. Among the algorithms evaluated by NIST in the third round of its PQC contest was the NTRU cryptosystem. The main drawback of this algorithm is the enormous amount of time required for the multiplication of polynomials in both the encryption and decryption processes. Therefore, the strategy of speeding up this algorithm using hardware/software co-design techniques where this operation is executed on specific hardware arises. Using these techniques, this work focuses on the acceleration of polynomial multiplication in the encryption process for resource-constrained devices. For this purpose, several hardware multiplications are analyzed following different strategies, taking into account the fact that there are no possible timing information leaks and that the available resources are optimized as much as possible. The designed multiplier is encapsulated as a fully reusable and parametrizable IP module with standard AXI4-Stream interconnection buses, which makes it easy to integrate into embedded systems implemented on programmable devices from different manufacturers. Depending on the resource constraints imposed, accelerations of up to 30-45 times with respect to the software-level multiplication runtime can be achieved using dedicated hardware, with a device occupancy of around 5%.
On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 23, no. 8, article 4070, 2023
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The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive set of on-line tests to obtain the metrics that determine its quality in terms of uniqueness, reliability, and entropy characteristics. The results obtained prove that the proposed module is a suitable candidate for various security applications. As an example, an implementation that uses less than 5% of the resources of a low-cost programmable device is capable of obfuscating and recovering 512-bit cryptographic keys with virtually zero error rate.
True Random Number Generation Capability of a Ring Oscillator PUF for Reconfigurable Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Electronics, vol. 11, no. 23, article 4028, 2022
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This paper presents the validation of a novel approach for a true-random number generator (TRNG) based on a ring oscillator-physical unclonable function (RO-PUF) for FPGA devices. The proposal takes advantage of the different noise sources that affect the electronic implementation of the RO-PUF to extract the entropy required to guarantee its function as a TRNG, without anything more than minimal changes to the original design. The new RO-PUF/TRNG architecture has been incorporated within a hybrid HW/SW embedded system designed for devices from the Xilinx Zynq-7000 family. The degree of randomness of the generated bit streams was assessed using the NIST 800-22 statistical test suite, while the validation of the RO-PUF proposal as an entropy source was carried out by fulfilling the NIST 800-90b recommendation. The features of the hybrid system were exploited to carry out the evaluation and validation processes proposed by the NIST publications, online and on the same platform. To establish the optimal configuration to generate bit streams with the appropriate entropy level, a statistical study of the degree of randomness was performed for multiple TRNG approaches derived from the different implementation modes and configuration options available on the original RO-PUF design. The results show that the RO-PUF/TRNG design is suitable for secure cryptographic applications, doubling its functionality without compromising the resource-efficiency trade-off already achieved in the design.
Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems
M.C. Martínez-Rodríguez, L.F. Rojas-Muñoz, E. Camacho-Ruiz, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 6, no.4, article 51, 2022
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The generation of unique identifiers extracted from the physical characteristics of the underlying hardware ensures the protection of electronic devices against counterfeiting and provides security to the data they store and process. This work describes the design of an efficient Physical Unclonable Function (PUF) based on the differences in the frequency of Ring Oscillators (ROs) with identical layout due to variations in the technological processes involved in the manufacture of the integrated circuit. The logic resources available in the Xilinx Series-7 programmable devices are exploited in the design to make it more compact and achieve an optimal bit-per-area rate. On the other hand, the design parameters can also be adjusted to provide a high bit-per-time rate for a particular target device. The PUF has been encapsulated as a configurable Intellectual Property (IP) module, providing it with an AXI4-Lite interface to ease its incorporation into embedded systems in combination with soft- or hard-core implementations of general-purpose processors. The capability of the proposed RO-PUF to generate implementation-dependent identifiers has been extensively tested, using a series of metrics to evaluate its reliability and robustness for different configuration options. Finally, in order to demonstrate its utility to improve system security, the identifiers provided by RO-PUFs implemented on different devices have been used in a Helper Data Algorithm (HDA) to obfuscate and retrieve a secret key.
Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems
S. Sánchez-Solano, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 22, no. 5, article 2057, 2022
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Concern for the security of embedded systems that implement IoT devices has become a crucial issue, as these devices today support an increasing number of applications and services that store and exchange information whose integrity, privacy, and authenticity must be adequately guaranteed. Modern lattice-based cryptographic schemes have proven to be a good alternative, both to face the security threats that arise as a consequence of the development of quantum computing and to allow efficient implementations of cryptographic primitives in resource-limited embedded systems, such as those used in consumer and industrial applications of the IoT. This article describes the hardware implementation of parameterized multi-unit serial polynomial multipliers to speed up time-consuming operations in NTRU-based cryptographic schemes. The flexibility in selecting the design parameters and the interconnection protocol with a general-purpose processor allow them to be applied both to the standardized variants of NTRU and to the new proposals that are being considered in the post-quantum contest currently held by the National Institute of Standards and Technology, as well as to obtain an adequate cost/performance/security-level trade-off for a target application. The designs are provided as AXI4 bus-compliant intellectual property modules that can be easily incorporated into embedded systems developed with the Vivado design tools. The work provides an extensive set of implementation and characterization results in devices of the Xilinx Zynq-7000 and Zynq UltraScale+ families for the different sets of parameters defined in the NTRUEncrypt standard. It also includes details of their plug and play inclusion as hardware accelerators in the C implementation of this public-key encryption scheme codified in the LibNTRU library, showing that acceleration factors of up to 3.1 are achieved when compared to pure software implementations running on the processing systems included in the programmable devices.
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs
A. Santana-Andreo, P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · Integration, vol. 85, pp 1-9, 2022
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PUFs based on the power-up values of an array of SRAM cells are a popular solution to provide secure and low-cost key generation suitable for IoT devices. However, SRAM cells do not always power up to the same value due to external factors like noise, temperature, or aging. This results in a decrease of reliability for the SRAM PUF, an issue generally solved by employing complex Error Correction Codes (ECCs). However, ECCs significantly increase the cost of the complete system. A way to alleviate this issue is the use of bit selection methods, which increase the reliability of the SRAM PUF by using only the power-up values of the most reliable cells (i.e., the SRAM cells that consistently power up to the same value). In this work, the reduction in ECC complexity through a bit selection method based on the Data Retention Voltage metric is demonstrated.
A Configurable RO-PUF for Securing Embedded Systems Implemented on Programmable Devices
M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Brox and S. Sánchez-Solano
Journal Paper · Electronics, vol. 10, no. 16, article 1957, 2021
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Improving the security of electronic devices that support innovative critical services (digital administrative services, e-health, e-shopping, and on-line banking) is essential to lay the foundations of a secure digital society. Security schemes based on Physical Unclonable Functions (PUFs) take advantage of intrinsic characteristics of the hardware for the online generation of unique digital identifiers and cryptographic keys that allow to ensure the protection of the devices against counterfeiting and to preserve data privacy. This paper tackles the design of a configurable Ring Oscillator (RO) PUF that encompasses several strategies to provide an efficient solution in terms of area, timing response, and performance. RO-PUF implementation on programmable logic devices is conceived to minimize the use of available resources, while operating speed can be optimized by properly selecting the size of the elements used to obtain the PUF response. The work also describes the interface added to the PUF to facilitate its incorporation as hardware Intellectual Property (IP)-modules into embedded systems. The performance of the RO-PUF is proven with an extensive battery of tests, which are executed to analyze the influence of different test strategies on the PUF quality indexes. The configurability of the proposed RO-PUF allows establishing the most suitable ‘cost/performance/security-level’ trade-off for a certain application.
Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm
E. Camacho-Ruiz, S. Sánchez-Solano, P. Brox and M.C. Martínez-Rodríguez
Journal Paper · ACM Journal on Emerging Technologies in Computing Systems, vol. 17, no. 3, article 35, 2021
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Post-quantum cryptographic algorithms have emerged to secure communication channels between electronic devices faced with the advent of quantum computers. The performance of post-quantum cryptographic algorithms on embedded systems has to be evaluated to achieve a good trade-off between required resources (area) and timing. This work presents two optimized implementations to speed up the NTRUEncrypt algorithm on a system-on-chip. The strategy is based on accelerating the most time-consuming operation that is the truncated polynomial multiplication. Hardware dedicated modules for multiplication are designed by exploiting the presence of consecutive zeros in the coefficients of the blinding polynomial. The results are validated on a PYNQ-Z2 platform that includes a Zynq-7000 SoC from Xilinx and supports a Python-based programming environment. The optimized version that exploits the presence of double, triple, and quadruple consecutive zeros offers the best performance in timing, in addition to considerably reducing the possibility of an information leakage against an eventual attack on the device, making it practically negligible.
Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · Microelectronics Reliability, vol. 118, article 114049, 2021
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The utilization of power-up values in SRAM cells to generate PUF responses for chip identification is a subject of intense study. The cells used for this purpose must be stable, i.e., the cell should always power-up to the same value (either ‘0’ or ‘1’). Otherwise, they would not be suitable for the identification. Some methods have been presented that aim at increasing the reliability of SRAM PUFs by identifying the strongest cells, i.e., the cells that more consistently power-up to the same value. However, these methods present some drawbacks, in terms of either their practical realization or their actual effectiveness in selecting the strongest cells at different scenarios, such as temperature variations or when the circuits have suffered aging-related degradation. In this work, the experimental results obtained for a new method to classify the cells according to their power-up strength are presented and discussed. The method overcomes some of the drawbacks in previously reported methods. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation and temperature variations, which ultimately translates into the construction of reliable SRAM-based PUFs.
Implementación de un detector de movimiento para cámaras inteligentes sobre sistemas embebidos
L.M. Garcés-Socarrás, R. Sánchez-Correa, A.J. Cabrera Sarmiento, S. Sánchez-Solano and P. Brox Jiménez
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 41, no. 13, pp 53-65, 2020
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Este artículo describe la implementación sobre hardware reconfigurable de un detector de movimiento para cámaras inteligentes el cual puede ser empleado en varios campos de aplicación. El sistema propuesto detecta el movimiento en una secuencia de vídeo identificando la región de interés para reducir el tiempo de procesado de los algoritmos de análisis e identificación posteriores. Como parte de este trabajo se realizan tres módulos de detección de movimiento basados en el modelo planteado por Reichardt & Hassenstein para la detección bioinspirada de movimiento elemental, así como otros módulos auxiliares. Estos bloques han sido incorporados a la biblioteca de procesado de imágenes y vídeos XIL XSGImgLib, la cual permite simplificar y reducir el tiempo de diseño de las aplicaciones de procesado de imágenes y vídeos sobre los FPGA y SoC FPGA de Xilinx. Para la comprobación de los detectores se presenta una aplicación de detección de movimiento para un flujo espaciotemporal de vídeo, proveniente de un punto de control de tráfico vehicular, en un FPGA Spartan-6 LX45, arrojando mejoras en el tiempo de ejecución de la implementación del bloque de detección de movimiento elemental comparado con desarrollos similares reportados en la literatura consultada.
Hardware Implementation of Authenticated Ciphers for Embedded Systems
M.C. Martínez-Rodríguez, S. Sauro, P. Brox and S. Sánchez-Solano
Journal Paper · IEEE Latin America Transactions, vol. 18, no. 9, pp 1581-1591, 2020
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The demand for embedded systems in applications that handle critical or private information has strongly focused designers' attention on the security aspects of this kind of system. Using the C programs and HDL descriptions available in the repositories of the CAESAR Competition and the ATHENa Project, this work presents a design flow that eases the development and evaluation of different solutions for the hardware implementation of authenticated ciphers and their incorporation as accelerating peripherals in embedded systems for different application cases. Three ciphers, finalists in the different categories established in the contest, have been analyzed, although the described approaches can be applied to any of the proposals submitted to the CAESAR Competition. A Zybo-Z7 development board that incorporates a Zynq-7000 device from Xilinx, which combines programmable logic from the FPGAs of the 7-Series with a dual-core Cortex-A9 ARM processing system, has been used as hardware platform in all the designs. The Vivado environment has been employed to perform the different stages of synthesis and verification necessary to carry out the implementation of the cipher, its conversion into an IP module, and its integration in an embedded system using different interconnection schemes that allow establishing cost/performance tradeoffs for different applications.
Self-modifiable image processing library for model-based design on FPGAs
L. Garces-Socarras, A. Cabrera, S. Sanchez-Solano, P. Brox, E. Ieno and T. Pimenta
Journal Paper · IEEE Latin America Transactions, vol. 17, no. 5, pp 742-750, 2019
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This paper describes highly configurable hardware modules, included in XIL XSGImgLib library, capable of speed up the hardware implementation of video and image processing systems using the model-based design flow provided by Xilinx System Generator. As part of this work, generic architectures were developed to exploit specific characteristics of some processing blocks, which can be self-modified using a novel software procedure developed for MATLAB (R). This procedure, along with the generic architecture and the configuration options, allows the abstraction about the specific details of the hardware implementation, as well as the adjustment of the resources consumption of the high-speed image and video processing application for embedded systems with weight, volume and power consumption constrains like smart cameras, video surveillance and autonomous vehicles. The use of this video and image processing library is illustrated by the development of a segmentation application on a Spartan-6 LX45 FPGA although any Xilinx's FPGA is supported.
A comparative analysis of VLSI trusted virtual sensors
M.C. Martínez-Rodríguez, P. Brox and I. Baturone
Journal Paper · Microprocessors and Microsystems, vol. 61, pp 108-116, 2018
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This paper analyzes three cryptographic modules suitable for digital designs of trusted virtual sensors into integrated circuits, using 90-nm CMOS technology. One of them, based on the keyed-hash message authentication code (HMAC) standard employing a PHOTON-80/20/16 lightweight hash function, ensures integrity and authentication of the virtual measurement. The other two, based on CAESAR (the Competition for Authenticated Encryption: Security, Applicability, and Robustness) third-round candidates AEGIS-128 and ASCON-128, ensure also confidentiality. The cryptographic key required is not stored in the sensor but recovered in a configuration operation mode from non-sensitive data stored in the non-volatile memory of the sensor and from the start-up values of the sensor SRAM acting as a Physical Unclonable Function (PUF), thus ensuring that the sensor is not counterfeit. The start-up values of the SRAM are also employed in the configuration operation mode to generate the seed of the nonces that make sensor outputs different and, hence, resistant to replay attacks. The configuration operation mode is slower if using CAESAR candidates because the cryptographic key and nonce have 128 bits instead of the 60 bits of the key and 32 bits of the nonce in HMAC. Configuration takes 416.8 μs working at 50 MHz using HMAC and 426.2 μs using CAESAR candidates. In the other side, the trusted sensing mode is much faster with CAESAR candidates with similar power consumption. Trusted sensing takes 212.62 μs at 50 MHz using HMAC, 0.72 μs using ASCON, and 0.42 μs using AEGIS. AEGIS allows the fastest trusted measurements at the cost of more silicon area, 4.4 times more area than HMAC and 5.4 times more than ASCON. ASCON allows fast measurements with the smallest area occupation. The module implementing ASCON occupies 0.026 mm2 in a 90-nm CMOS technology.
VLSI Design of Trusted Virtual Sensors
M.C. Martínez-Rodríguez, M.A. Prada-Delgado, P. Brox and I. Baturone
Journal Paper · Sensors, vol. 18, no. 2, article 347, 2018
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This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μs. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).
Model-based implementation of self-configurable intellectual property modules for image histogram calculation in FPGAs
L.M. Garcés-Socarrás, D.A. Romero, A.J. Cabrera, S. Sánchez-Solano and P. Brox
Journal Paper · Ingeniería e Investigación, vol. 37, no. 2, pp 74-81, 2017
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This work presents the development of self-modifiable Intellectual Property (IP) modules for histogram calculation using the modelbased design technique provided by Xilinx System Generator. In this work, an analysis and a comparison among histogram calculation architectures are presented, selecting the best solution for the design flow used. Also, the paper emphasizes the use of generic architectures capable of been adjustable by a self configurable procedure to ensure a processing flow adequate to the application requirements. In addition, the implementation of a configurable IP module for histogram calculation using a model-based design flow is described and some implementation results are shown over a Xilinx FPGA Spartan-6 LX45.
Modificación automática de arquitecturas de módulos hardware de procesado de imágenes
L.M. Garcés-Socarrás, A.J. Cabrera-Sarmiento, S. Sánchez-Solano, P. Brox-Jiménez, E. Ieno and T. Cleber-Pimenta
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 37, no. 3, pp 21-23, 2016
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El presente artículo describe el empleo del flujo de diseño basado en modelos para el desarrollo de bloques reconfigurables automáticamente para el procesado de imágenes sobre FPGA. Para ello se han concebido arquitecturas hardware que aprovechan características específicas de algunos algoritmos de procesado y que pueden ser modificadas a través de un novedoso procedimiento software. Este aspecto, unido a las restantes opciones de parametrización de los diferentes módulos, permite liberar al diseñador de los detalles específicos de las implementaciones hardware así como adaptar el consumo de recursos del FPGA a las necesidades de la aplicación. El proceso de reconfiguración automática se ilustra con el bloque de convolución genérico.
Low-cost dedicated hardware IP modules for background subtraction in embedded vision systems
E. Calvo-Gallego, P. Brox and S. Sanchez-Solano
Journal Paper · Journal of Real-Time Image Processing, vol. 12, no. 4, pp 681-695, 2016
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This paper presents the design and implementation of dedicated hardware IP modules for background subtraction, which are suitable to be implemented in embedded vision systems and are efficient in terms of performance, resource consumption, and operational speed. To achieve this goal, a comprehensive experimental study of different algorithms has been carried out by evaluating a wide range of quality parameters. From the results of this analysis, five candidate algorithms were selected and implemented using a model-based design methodology supported by Matlab and Xilinx FPGA tools. Using only the internal block memory available in the FPGA, they provide adequate solutions for processing low-resolution images with CIF and QCIF formats.
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions
P. Brox, M.C. Martínez-Rodríguez, E. Tena-Sánchez, I. Baturone and A.J. Acosta
Journal Paper · International Journal of Circuit Theory and Applications, vol. 44, no. 1, pp. 4-20, 2015
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This paper presents a fully digital architecture and its application specific integrated circuit implementation for computing multi-input multi-output (MIMO) piecewise-affine (PWA) functions. The work considers both PWA functions defined over regular hyperrectangular and simplicial partitions of the input domains and also lattice PWA representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with application specific integrated circuit (ASIC) integrated in a 90-nm complementary metal-oxide semiconductor standard technology are provided. The proposed architecture is compared with other digital architectures in the state of the art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high-performance and minimum unitary cost are required.
Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach
M.C. Martínez-Rodríguez, P. Brox, P. and I. Baturone
Journal Paper · IEEE Transactions on Control Systems Technology, vol. 23, no. 3, pp 842-854, 2015
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This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture.
Edge-adaptive spatial video de-interlacing algorithms based on fuzzy logic
P. Brox, I. Baturone, S. Sánchez-Solano and J. Gutiérrez-Ríos
Journal Paper · IEEE Transactions on Consumer Electronics, vol. 60, no. 3, pp. 375-383, 2014
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Since the human visual system is especially sensitive to image edges, edge-dependent spatial interpolators have been proposed in literature as a means of successfully restoring edges while avoiding the staircase effect of linear spatial algorithms. This paper addresses the application of video de-interlacing, which constitutes an indispensable stage in video format conversion. Classic edge-adaptive de-interlacing algorithms introduce annoying artifacts when the edge directions are evaluated incorrectly. This paper presents two ways of exploiting fuzzy reasoning to reinforce edges without an excessive increase in computational complexity. The performance of the proposed algorithms is analyzed by deinterlacing a wide set of test sequences. The study compares the two proposals both with each other and with other edge-adaptive de-interlacing methods reported in the recent literature.
Fuzzy logic-based embedded system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · Applied Soft Computing, vol. 14, part C, pp 338-346, 2014
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Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time.
Prototipado rápido de sistemas de procesado de vídeo basados en el VFBC de Xilinx
L.M. Garcés, S. Sánchez-Solano, P. Brox and A.J. Cabrera
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. XXXIV, no. 1, pp 100-109, 2013
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This paper develops hardware modules for rapid prototyping of video processing systems based on the Xilinx video frame buffer controller (VFBC). This implementation allows the storage of video frames in memory external to the programmable device, as well as its proper handle for designing spatio-temporal processing systems using the Xilinx System Generator model-based design flow. The hardware modules are responsible for the configuration and control of writing and reading VFBC interfaces, as well as the manipulation of video synchronization signals for interconnecting input and output peripherals.
The article also include the description of the elaborated modules and the analysis of the results of its use for the development of a temporal video processing demonstrator using a simple motion detector on a Spartan-6 SP605 Evaluation Platform board.
A programmable and configurable ASIC to generate piecewise-affine functions defined over general partitions
P. Brox, R. Castro-Ramirez, M.C. Martinez-Rodriguez, E. Tena, C.J. Jimenez, I. Baturone and A.J. Acosta
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 12, pp 3182-3194, 2013
resumen
doi
This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated Circuit (ASIC) to generate Piecewise-Affine (PWA) functions. A Generic PWA form (PWAG) has been selected for integration, because of its suitability to implement any PWA function without resorting to approximation. The design of the ASIC in a 90 nm TSMC technology, its integration, test and characterization through different examples are detailed in the paper. Furthermore, the ASIC verification using an ASIC-in-the-loop methodology for embedded control applications is presented. To assess the characteristics of this verification, the double-integrator, a usual control application example has been considered. Experimental results validate the proposed architecture and the ASIC implementation.
Library for model-based design of image processing algorithms on FPGAs
L.M. Garcés-Socarrás, S. Sánchez-Solano, P. Brox and A.J. Cabrera
Journal Paper · Revista Facultad de Ingenieria, no. 68, pp 36-47, 2013
resumen
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This paper describes a library (XSGImgLib) that includes parameterizable blocks to implement low-level image processing tasks on FPGAs. A modelbased design technique provided by Xilinx System Generator (XSG) has been used to design the blocks, which implement point operation (binarization) and neighborhood operations (linear and non-linear filtering) in grayscale images. The blocks are parameterizable for input/output data precision, window size, normalization strategy, and implementation options (area versus speed optimization). The paper includes the implementation results obtained after fixing these options and exemplifies the combination of several blocks of the library to build a complete design for image segmentation purposes.
Model-Based Design Methodology for Rapid Development of Fuzzy Controllers on FPGAs
S. Sánchez-Solano, M. Brox, E. del Toro, P. Brox and I. Baturone
Journal Paper · IEEE Transactions on Industrial Informatics, vol. 9, no. 3, pp 1361-1370, 2013
resumen
doi pdf
The complexity reached by current applications of industrial control systems has motivated the development of new computational paradigms, as well as the employment of hybrid implementation techniques that combine hardware and software components to fulfill system requirements. On the other hand, continuous improvements in field-programmable devices today make possible the implementation of complex control systems on reconfigurable hardware, although they are limited by the lack of specific design tools and methodologies to facilitate the development of new products. This paper describes a model-based design approach for the synthesis of embedded fuzzy controllers on field-programmable gate arrays (FPGAs). Its main contributions are the proposal of a novel implementation technique, which allows accelerating the exploration of the design space of fuzzy inference modules, and the use of a design flow that eases their integration into complex control systems and the joint development of hardware and software components. This design flow is supported by specific tools for fuzzy systems development and standard FPGA synthesis and implementation tools, which use the modeling and simulation facilities provided by the Matlab environment. The development of a complex control system for parking an autonomous vehicle demonstrates the capabilities of the proposed procedure to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy controllers for industrial applications.
CAD Tools for Hardware Implementation of Embedded Fuzzy Systems on FPGAs
M. Brox, S. Sánchez-Solano, E. del Toro, P. Brox and F.J. Moreno-Velo
Journal Paper · IEEE Transactions on Industrial Informatics, vol. 9, no. 3, pp 1635-1644, 2013
resumen
doi pdf
This paper describes two computer-aided design (CAD) tools for automatic synthesis of fuzzy logic-based inference systems. The tools share a common architecture for efficient hardware implementation of fuzzy modules, but are based on two different design strategies. One of them is focused on the generation of standard VHDL code, which can be later implemented on a reconfigurable device [field-programmable gate array (FPGA)] or as an application-specific integrated circuit (ASIC). The other one uses the Matlab/Simulink environment and tools for development of digital signal processing (DSP) systems on Xilinx's FPGAs. Both tools are included in the last version of Xfuzzy, which is a specific environment for designing complex fuzzy systems, and they provide interfaces to commercial VHDL synthesis and verification tools, as well as to conventional FPGA development environments. As demonstrated by the included design example, the proposed development strategies speed up the stages of description, synthesis, and functional verification of embedded fuzzy inference systems.
Diseño de bloques de convolución para procesado de imágenes con FPGA
L.M. Garcés-Socarrás, A.J. Cabrera-Sarmiento, S. Sánchez-Solano and P. Brox
Journal Paper · Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. XXXII 3/2011 pp 56-69, 2011
resumen
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Este trabajo analiza distintas opciones de realización de bloques para procesado lineal de imágenes implementados sobre FPGA,
así como los efectos de la elección de diferentes parámetros de diseño. Los bloques han sido desarrollados empleando un flujo de
diseño basado en modelos que se apoya en el entorno MATLAB/Simulink y la herramienta System Generator de Xilinx. Su
implementación física se ha llevado a cabo sobre una placa de desarrollo Spartan-3A DSP 1800 de Xilinx.
Fuzzy motion adaptive algorithm and its hardware implementation for video de-interlacing
J. Gutiérrez-Rios, P. Brox, F. Fernández-Hernández, I. Baturone and S. Sánchez-Solano
Journal Paper · Applied Soft Computing, vol. 11, no. 4, pp 3311-3320, 2011
resumen
doi pdf
Interlacing techniques were introduced in the early analog TV transmission systems as an efficient mechanism capable of halving the video bandwidth. Currently, interlacing is also used by some modern digital TV transmission systems, however, there is a problem at the receiver side since the majority of modern display devices require a progressive scanning. De-interlacing algorithms convert an interlaced video signal into a progressive one by performing interpolation. To achieve good de-interlacing results, dynamical and local image features should be considered. The gradual adaptation of the de-interlacing technique as a function of the level of motion detected in each pixel is a powerful method that can be carried out by means of fuzzy inference. The starting point of our study is an algorithm that uses a fuzzy inference system to evaluate motion locally (FMA algorithm). Our approach is based on convolution techniques to process a fuzzy rulebase for motion-adaptive de-interlacing. Different strategies based on bi-dimensional convolution techniques are proposed. In particular, the algorithm called 'single convolution algorithm' introduces significant advantages: a more accurate measurement of the level of motion using a matrix of weights, and a unique fuzzification process after the global estimation, which reduces the computational cost. Different architectures for the hardware implementation of this algorithm are described in VHDL language. The physical realization is carried out on a RC100 Celoxica FPGA development board. (C) 2010 Elsevier B.V. All rights reserved.
Soft computing techniques for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · IEEE Journal of Selected Topics in Signal Processing, vol. 5, no. 2, pp 285-296, 2011
resumen
doi pdf
This paper presents the application of soft computing techniques to video processing. Especially, the research work has been focused on the de-interlacing task. It is necessary whenever the transmission standard uses an interlaced format but the receiver requires a progressive scanning, as happens in consumer displays such as LCDs and plasma. A simple hierarchical solution that combines three simple fuzzy logic-based constituents (interpolators) is presented in this paper. Each interpolator is specialized in one of three key image features for de-interlacing: motion, edges, and possible repetition of picture areas. The resulting algorithm offers better results than others with less or similar computational cost. A very interesting result is that our algorithm is competitive with motion-compensated algorithms.
Fuzzy motion-adaptive interpolation with picture repetition detection for deinterlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 58, no. 9, pp 2952-2958, 2009
resumen
doi
A novel fuzzy motion-adaptive deinterlacing algorithm is presented in this paper. It uses fuzzy logic to interpolate between two processing modes, i.e., a spatial (IS) and a temporal (IT) interpolator. Furthermore, the temporal interpolator employs a very simple fuzzy inference system to implement a smart temporal interpolation that locally adapts to the features of the television (TV) material, such as possible picture repetition modes in the fields or in part of the fields (hybrid material). The combination of both systems provides effective results with a low cost in terms of computational resources.
Local picture-repetition mode detector for video de-interlacing
P. Brox, L. Woestenberg and G. de Haan
Journal Paper · IEEE Transactions on Consumer Electronics, vol. 53, no. 4, pp 1647-1655, 2007
resumen
doi pdf
The de-interlacing of video material converted from film can be perfect, provided it is possible to recognize the field-pairs that originate from the same film image. VaRíous so-called film-detectors have been proposed for this purpose, mainly in the patent-literature. Typically, these detectors fail in cases where video overlays are merged with film material, or when nonstandard repetition patterns are used. Both problems occur frequently in television broadcast. For these hybrid and/or irregular cases, we propose a detector that can detect ffdifferent picture-repetition patterns locally in the image. This detector combines fuzzy logic rules and spatio-temporal prediction to arrive at a highly robust decision signal, suitable for pixel- accurate de-interlacing of hybrid and irregular video material. In addition to an evaluation of the performance, the paper also provides a complexity analysis.
A fuzzy edge-dependent motion adaptive algorithm for de-interlacing
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutierrez-Ríos and F. Fernández-Hernández
Journal Paper · Fuzzy Sets and Systems, vol. 158, no. 3, pp 337-347, 2007
resumen
doi pdf
De-interlacing algorithms are required to convert interlaced video into progressive scan format. They perform an interpolation technique which doubles the vertical sampling density. This paper presents a de-interlacing algorithm which employs fuzzy logic to adapt the interpolation strategy to the presence of motion and edges. Extensive simulations of video sequences prove the advantages of this novel approach. (c) 2006 Elsevier B.V. All rights reserved.
Modelling and implementation of fuzzy systems based on VHDL
A. Barriga, S. Sánchez-Solano, P. Brox, A. Cabrera and I. Baturone
Journal Paper · International Journal of Approximate Reasoning, vol. 41, no. 2, pp 164-178, 2006
resumen
doi pdf
The number of electronic applications using fuzzy logic-based solutions hits increased considerably in the last few years. Concurrently, new CAD tools that explore different implementation technologies for this type of systems have been developed. In this paper we illustrate a fuzzy logic system design strategy based on a high level description. Employing this high level description, the knowledge base is translated to a format in appearance close to the natural language with the particularity that it uses a hardware description language (VHDL) directly synthesizable on an FPGA circuit.]it addition, we analyze different approaches for FPGA implementations of fuzzy systems in order to characterize them in terms of area and speed. Among them, the use of specific processing architectures implemented oil FPGAs presents as main advantages a good "cost-performance" ratio and an acceptably short development time. The different synthesis facilities provided by the Xfuzzy design environment for the implementation of programmable fuzzy systems, which take advantage of the available resources in the current FPGA families, are also analyzed in this paper. (C) 2005 Elsevier Inc. All rights reserved.
Hardware/software codesign of configurable fuzzy control systems
A. Cabrera, S. Sánchez-Solano, P. Brox, A. Barriga and R. Senhadji
Journal Paper · Applied Soft Computing, vol. 4, no. 3, pp 271-285, 2004
resumen
doi pdf
Fuzzy inference techniques are an attractive and well-established approach for solving control problems. This is mainly due to their inherent ability to obtain robust, low-cost controllers from the intuitive ( and usually ambiguous or incomplete) linguistic rules used by human operators when describing the control process. This paper focuses on the hardware/software codesign of configurable fuzzy control systems. Two prototype systems implemented on general-purpose development boards are presented. In both of them, hardware components are based on specific and configurable fuzzy inference architecture whereas software tasks are supported by a microcontroller. The first prototype uses an off-the-shelf microcontroller and a low-complexity Xilinx XC4005XL field programmable gate array (FPGA). The second one is implemented as a system on programmable chip (SoPC), integrating the microcontroller together with the fuzzy hardware architecture and its interface circuits into a Xilinx Spartan2E200 FPGA. (C) 2004 Elsevier B.V. All rights reserved.
Congresos
Full Open-Source Implementation of an Academic RISC-V on FPGA
P. Navarro-Torrero, M.C. Martínez-Rodríguez, A. Barriga-Barros and P. Brox
Conference · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
resumen
doi
In alignment with the ethos of openness and democracy inherent in the RISC-V architecture, our research endeavors have been directed towards the utilization of open-source tools for the implementation of a simple but didactic RISC-V processor denoted as ASTIRV32I. The paper discusses the design strategies, memory mapping, physical verification procedures, and performance evaluation of the ASTIRV32I processor. Furthermore, it highlights the successful validation of the implemented design through the execution of fundamental algorithms, exemplifying the practicality and viability of the RISC-V-based processor design and serving as a proof-of-concept for open-source FPGA design.
Digital Design Flow Based on Open Tools for Programmable Logic Devices
P. Navarro-Torrero, L.F. Rojas-Muñoz, M.C. Martínez-Rodríguez, A. Barriga-Barros, C.J. Jiménez-Fernández, M. Brox and P. Brox
Conference · 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)
resumen
doi
In this demonstrator, a design flow based on a set of open-source tools is showcased, enabling the simulation, synthesis, implementation, and programming of digital systems on programmable logic devices. Three academic examples, increasing in complexity, are shown running on open hardware development boards to demonstrate the validity of the digital design flow based on the APIO environment.
Exploiting randomly distributed pores in photonic structures for security applications to create hardware-based digital identity
D. Martín-Sánchez and P. Brox
Conference · NanoSpain Conf 2024, Tarragona, España
resumen
In the 2024 edition, the conference will strength collaborations with the COST network Netpore in the field of porous semiconductors and oxides. The intersection of nanoSpain2024 and the thematic network COST will encourage collaborative dialogues and the initiation of potential partnerships between researchers and industry professionals. More info at
https://www.nanospainconf.org/2024 Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
resumen
doi
This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.
Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
P. Navarro-Torrero, L.F. Rojas-Muñoz, P. Brox and S. Sánchez-Solano
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
resumen
Abstract not available
A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem
E. Camacho-Ruiz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Tena-Sánchez and P. Brox
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
resumen
Abstract not available
HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip
A. Karmakar, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · XXXVIII Conference on Design of Circuits and Integrated Systems DCIS 2023
resumen
Abstract not available
A complete SHA-3 hardware library based on a high efficiency Keccak design
E. Camacho-Ruiz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2023
resumen
Hash functions are a crucial part of the cryptographic primitives. So much so that in 2007 a new competition was launched to select new standards for the SHA-3 function, which was won by Keccak. Since then, many software and hardware implementations have been submitted, claiming to reduce the number of operation cycles or increase design efficiency. Thus, this work aims to present a new hardware solution for the Keccak function, which forms the core of SHA-3, that achieves a high degree of tunability and is competitive with the state of the art. In addition, this work presents the integration of these designs into a hardware IP module together with the relevant drivers and functions that allow their use in software environments. Preliminary tests have shown an acceleration of up to 10 times compared to pure software code.
Hardware-assisted solutions to secure embedded systems on programmable logic devices (invited talk)
P. Brox
Conference · Cryptographic architectures embedded in logic devices, 2023
resumen
Abstract not available
Open hardware to build trusted and verifiable chips (invited talk)
P. Brox
Conference · RISC-V Summit Europe 5-9 June, 2023
resumen
Abstract not available
Secure Platform for ICT systems rooted at the silicon manufacturing process
C. Andriamisaina, F. Thabet, J-R Coulon, G. Chauvon, A. Cabrera Aldaya, N. Tuveri, M.C. Martínez-Rodríguez and P. Brox
Conference · RISC-V Summit Europe 5-9 June, 2023
resumen
Abstract not available
Root of Trust Components to Increase Security of RISC-V Based Systems on Chips
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · RISC-V Summit Europe 5-9 June, 2023
resumen
Abstract not available
Análisis y evaluación de un RO-PUF como TRNG
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2023
resumen
Abstract not available
True Random Number Generator based on RO-PUF
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Conference · Conference on Design of Circuits and Integrated Circuits DCIS 2022
resumen
The implementation of true random number generators is of vital importance to preserve the reliability of cryptographic systems. The lack of entropy can compromise their integrity, affecting the security of the entire chain of applications. Ensuring the effectiveness of a random number generator can be understood as reducing the risk of information loss due to possible attacks by third parties. This paper presents a novel approach for a true random number generator based on a Ring Oscillator- Physical Unclonable Function. Since the principle of operation of physical unclonable functions is based on the physical properties of each device, they can be used for security applications such as device identification, counterfeit prevention and increase the robustness of cryptographic functions. In addition, increasing the versatility of the design to use them as a source of entropy, they can also fulfill tasks such as generation of initialization vectors or nonces and keys for symmetric cryptography. The system incorporates multiple operating configurations, which allows a complete analysis of its performance to adapt it to different application scenarios. The randomness and correct operation of the proposed design have been evaluated online, by incorporating it into a hybrid HW/SW embedded system able to run the official test suite published by the National Institute of Standards and Technology without any need for post-processing. The architecture has been designed for Xilinx Zynq-700 family devices and implemented on the Pynq-Z2 development board.
Hardware dedicado para la optimización temporal del algoritmo NTRU
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and Piedad Brox
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen
Los actuales algoritmos criptográficos se encuentran amenazados por la inminente llegada de la computación cuántica, por lo que los organismos internacionales, especialmente aquellos relacionados con la ciberseguridad, están potenciando el estudio e implementación de algoritmos que permitan volver a establecer entornos seguros de comunicación. En concreto, se plantean los algoritmos criptográficos post-cuánticos. Dentro de los algoritmos propuestos se encuentra el NTRU. Su principal inconveniente es el excesivo tiempo que requiere la multiplicación de polinomios usada en el proceso de cifrado. Por ello, este trabajo tiene como principal objetivo estudiar la posibilidad de utilizar hardware dedicado para acelerar la multiplicación. El uso de técnicas de codiseño hardware/software permite una implementación eficiente del criptosistema, donde las partes más costosas se ejecutan a nivel hardware. Este breve resumen recoge las últimas aportaciones que el grupo de investigación ha realizado en esta línea.
Diseño y evaluación de las prestaciones de funciones físicas no clonables basadas en osciladores en anillo sobre FPGAs
M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Brox and S. Sánchez-Solano
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen
Los esquemas de seguridad basados en funciones físicas no clonables aprovechan las características intrínsecas del hardware para mejorar la seguridad de los dispositivos electrónicos. Este resumen presenta dos trabajos para diseñar y caracterizar funciones físicas no clonables basados en osciladores en anillo propuestas por nuestro grupo de investigación. El primero se centra en el flujo de diseño y caracterización basado en una herramienta incluida en el entorno de Matlab, mientras que el segundo presenta y caracteriza una función física no clonable basada en osciladores en anillo muy compacta y altamente configurable usando un flujo de diseño para sistemas empotrados basado en el entorno PYNQ.
Secure Platform for ICT Systems Rooted at the Silicon Manufacturing Process (SPIRS)
P. Brox, M.C. Martínez-Rodríguez and D. Arroyo
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen
Internet of Things and ubiquitous/pervasive computing are shaping our world where smart devices enter every aspect of our everyday life. This is why privacy-enhancing technologies are all the more important. In this context, the Eufunded ‘Secure Platform for ICT Systems Rooted at the Silicon Manufacturing Process’ project will design a platform that integrates a hardware dedicated Root-of-Trust and a processor core with the capability of offering a full suite of security services. The platform will be able to leverage this capability to support privacy respectful attestation mechanisms and enable trusted communication channels across 5G infrastructures. The project will also provide solutions to integrate the platform in the deployment of cryptographic protocols and network infrastructures in a trustworthy way.
A Novel Physical Unclonable Function Using RTN
E. Camacho-Ruiz, R. Castro-Lopez, E. Roca, P. Brox and F.V. Fernandez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2022
resumen
PUFs have emerged as an alternative to traditional Non-Volatile Memories in the field of hardware security. In this paper, a novel PUF is proposed that uses the Random Telegraph Noise phenomenon as the underlying source of entropy. This phenomenon manifests as discrete and random shifts in the drain current of transistors and it is characterized by several parameters like the number of the defects in the device, as well as the emission and capture time constants and current shifts of these defects. Using the recently reported Maximum Current Fluctuation metric, it is possible to condense all this information and use it for the PUF design. By forming pairs of transistors, measuring, and comparing their Maximum Current Fluctuation over a given time interval, we demonstrate that it is possible to obtain a PUF. Furthermore, the results reported here show that this RNT-based PUF meets, and even outperforms, other silicon PUFs in terms of uniqueness, unpredictability, and reliability with an evident advantage in silicon area.
Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs
M.C. Martínez-Rodríguez, E. Camacho-Ruiz, S. Sánchez-Solano and P. Brox
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2021
resumen
This work presents a unified framework to design, implement and evaluate the performance of Ring Oscillator Physical Unclonable Functions (RO PUFs) on FPGAs. The design flow uses a Digital Signal Processing (DSP) tool integrated into the Matlab environment. The use of this tool eases the evaluation of the PUF performance. The DSP tool provides an environment to apply the challenges to the RO PUF, acquire the responses by using hardware (HW) co-simulation, and compute a set of metrics to quantify the stability, probability and entropy of the PIF response. Additionally, the robustness of the PUF response is proved in the generation of secret keys. The design flow was applied to evaluate the performance of RO PUFs implemented on 17 Basys 3 Artix-7 FPGA Boards.
A study of SRAM PUFs reliability using the Static Noise Margin
E. Camacho-Ruiz, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, P. Brox and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2021
resumen
The use of SRAM cells as key elements in a Physical Unclonable Function (PUF) has been widely reported. An essential characteristic
the SRAM cell must feature for a reliable PUF is stability, i.e., it must power up consistently to the same value. Different
techniques to measure this stability (and thus improve the PUF reliability) have been reported, such as the Multiple Evaluation
method and, more recently, the Maximum Trip Supply Voltage method, the latter using the Data Retention Voltage (DRV) concept.
While experimental results have been reported, this paper sheds some light from a different perspective: simulation. In this sense,
and using wellknown concepts like butterfly curves, static noise margin and voltage-transfer curves, an analysis is provided on
why and how stability originates in the cell. Moreover, by simulating the butterfly curve behavior when the supply voltage scales
down, it is possible to correlate DRV with stability, thereby confirming the correct theoretical foundation of the MTSV method.
Accelerating the Development of NTRU Algorithm on Embedded Systems
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and P. Brox
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
resumen
The advent of quantum computers represents a serious threat to current public key cryptosystems. To face this problem the so-called Post-Quantum (PQ) cryptographic solutions are being developed, many of which have been presented to the competition launched by NIST to evaluate proposals of PQ cryptography for standardization and deployment. This paper addresses the implementation of the NTRU PQ cryptographic algorithm on embedded systems. Using a Python-based development framework to accelerate the design process, software-only and hybrid (HW/SW) implementations of NTRU are evaluated in terms of operation speed and resource consumption on a System-on-Chip (SoC). Results show that hardware implementation of critical operations in conjuction with a Python+C programming allows an increase in performance that ranges from 130 to 450 depending on the selected scenario to use the algorithm.
Improving the reliability of SRAM-based PUFs under varying conditions
P. Sarazá-Canflanca, H. Carrasco-López, P. Brox, R. Castro-López, E. Roca and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
resumen
Abstract not available
Improving the reliability of SRAM-based PUFs in the presence of aging
P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · Design and Technology of Integrated Systems in Nanoscale Era DTIS 2020
resumen
The utilization of power-up values in SRAM cells for the generation of PUF responses has been widely studied. It is important that the cells used for this purpose are stable, i.e., the cells must have a strong tendency towards one of the two possible values (‘ ‘0 ’ or ‘1 ’). Some methods have been presented that aim at increasing the reliability of this type of PUFs by selecting the strongest cells among a set of them. However, they feature some drawbacks, either in terms of their practical feasibility or of their actual effectiveness selecting the strongest cells in different scenarios. In this work, the experimental results obtained for a new method to classify the cells according to their strength are presented and discussed. The technique overcomes some of the drawbacks that the previous methods present. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation, which translates into the construction of reliable SRAM-based PUFs.
CMOS digital design of a trusted virtual sensor
M.C. Martínez-Rodríguez, M.A. Prada, P. Brox and I. Baturone
Conference · IEEE Nordic Circuits and Systems Conference NORCAS 2017
resumen
This work presents the digital design of a trusted virtual sensor. The virtual sensor implements a piecewise-affine (PWA)-based model to estimate the sensed variable. The measurement is authenticated with the keyed-hash message authentication code (HMAC) standard. To ensure the integrity of the sensor, the static random access memory (SRAM) required by the sensor is also used as physical unclonable function (PUF). Implementation results of the design in a 90-nm CMOS technology show that the security blocks occupy 5.1% of the area occupied by the required PWA blocks and consume 15.4% of the power consumed by the required PWA blocks. The sensor is able to provide trusted outputs in 106.3 microseconds when working at 100 MHz.
Exploiting the variability of semiconductor fabrication process for hardware security
I. Baturone, P. Brox, R. Arjona and M.A. Prada-Delgado
Conference · How to survive in an unreliable world, IEEE CEDA Spain Chapter / NANOVAR Workshop 2017
resumen
Variability of semiconductor fabrication process can be a problem for many electronic designers, but it is a strength for many others who want to increase the security of electronic products. This talk summarizes how to exploit variability to provide, from hardware, identifiers and cryptographic primitives such as secret keys and true random numbers and, hence, how hardware-based security can solve vulnerabilities of software-based security.
DigitalLib: Una librería VHDL de bloques básicos para automatizar la construcción de sistemas digitales complejos
M. Brox, A. Gersnoviez, I. Bujalance, F.J. Quiles, M.A. Ortiz and P. Brox
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
resumen
The objective of this work is the development of a library, named DigitalLib, of basic blocks of digital electronics described in VHDL language (as multiplexers, decoders, adders, subtractors, flip-flops, registers, memories, etc.), whose role is to facilitate and automate the design of advanced digital systems. In the developed blocks have been included parameters in order to adapt them to any size and precision. Hence, the implementation of advanced designs is based only on interconnecting the basic elements developed in the library, and assigning the appropriate parameters for each element. In order to demonstrate the simplification of designs with DigitalLib, which can be used by students of subjects of Advanced Design of Digital Systems, the work includes the description of different complex designs developed with this library.
Diseño de sistemas sensoriales basados en la plataforma Arduino
P. Brox, G. Huertas-Sanchez, A. Lopez-Angulo, M. Alvarez-Mora and I. Haya
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
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Different sensory systems that are implemented using the open hardware platform Arduino are described in this paper. These projects are developed by students from the last course of Bachelor Physics Degree at the University of Seville. The educational purpose of the development of this kind of project is to apply their acquired knowledge in electronics to solve a specific problem.
Hardware implementation of fuzzy inference systems for real-time video processing applications
S. Sánchez-Solano, M. Brox, E. Calvo-Gallego, A. Gersnoviez and P. Brox
Conference · XVIII Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2016
resumen
As a consequence of its ability to handle inaccurate or incomplete information and its capacity to mimic the human reasoning schema, Fuzzy Logic-based techniques have been widely used in many image processing algorithms [1] [2]. Incorporating these algorithms into current embedded video processing systems requires the use of specific hardware designs capable of providing the data-transfer rates demanded by existing applications [3]. This paper presents a hardware architecture for fuzzy inference systems which is able to provide an inference in each clock cycle, thus allowing the usage of fuzzy techniques in low- and middle-level video processing tasks. Even though the architecture imposes some limitations on the membership functions and inference mechanisms that can be used, it may be suitable for hardware implementation of many fuzzy solutions proposed in the literature.
FPGA Implementation of the Two-Dimensional Fuzzy-ELA Algorithm for Image Enlargement
M. Brox, S. Sánchez-Solano, P. Brox, A. Gersnoviez and I. Baturone
Conference · XVIII Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2016
resumen
Resolution improvement of images is today required for many applications, as medical or satellite imaging, where it is very important to distinguish details [1]. The interpolation capability provided by Fuzzy Logic, in addition to its effectivity to incorporate heuristic knowledge into numeric procedures, has motivated its usage in recent algorithms for image enlargement [2]. This paper presents the hardware implementation of the two-dimensional Fuzzy-ELA algorithm proposed in [3]. The 2D Fuzzy-ELA method is a generalization of the basic Fuzzy-ELA algorithm [4], which uses a fuzzy system to adapt the interpolation to the presence of edges in images, achieving better results than many other approaches. The hardware implementation described in this paper includes parameters to allow selecting different scale factors for the image enlargement. In order to simplify the description, Fig.1a illustrates the process when a factor of two is chosen.
Bloques de detección de matrículas sobre hardware reconfigurable
J.C. Gutiérrez, E. Augusto-Perdomo, L.M. Garcés-Socarrás, A.J. Cabrera Sarmiento, S. Sánchez-Solano and P. Brox-Jiménez
Conference · XVI Convención de Ingeniería Eléctrica CIE 2015
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El presente trabajo aborda la implementación de un sistema de localización de regiones de interés sobre hardware reconfigurable, espec'ifico para determinar la ubicación de la matr'icula de un auto para su posterior identificación. Se realiza un estudio de los sistemas de visión, enfocándose en los sistemas de detección de regiones de matrículas, analizando las arquitecturas y algoritmos de procesado que los componen para desarrollar el algoritmo propuesto. En la implementación se emplean bloques de procesado de imágenes de la biblioteca XSGImgLib así como bloques diseñados para etiquetado de la imagen y análisis de selección de matrículas basados en la herramienta Xilinx System Generator. El sistema fue implementado sobre una placa Spartan-6 LX45, cumpliendo con los requerimientos de procesado en tiempo real de las aplicaciones de visión computarizada, con una frecuencia máxima de operación de 30.79 MHz para una imagen de 320x240 pixeles y un máximo de 100 etiquetas. El consumo de recursos del sistema, implementado es de un 10.55% de slices ocupados, dejando recursos suficientes para implementar otras funcionalidades en el dispositivo programable.
Dedicated Hardware IP Module for Fingerprint Recognition
M.C. Martínez-Rodríguez, R. Arjona, P. Brox and I. Baturone
Conference · International Symposium on Consumer Electronics ISCE 2015
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This work presents a dedicated hardware IP module for fingerprints recognition based on a feature, named QFingerMap, which is very suitable for VLSI design. FPGA implementation results of the IP module are given. A demonstrator has been developed to evaluate the IP module behavior in a real scenario.
Hardware implementation of a background substraction algorithm in FPGA-based platforms
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · IEEE International Conference on Industrial Technology ICIT-2015
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Different strategies for the implementation of a fuzzy logic-based background subtraction algorithm are presented in this paper. The goal of this contribution is to obtain an efficient implementation suitable to be integrated into hardware platforms with limited resources. In order to find an adequate performance-resources trade-off, the design space is explored taken into account several strategies and implementation options. The final implementation is encapsulated within an IP core that has been used in a demonstrator, built on a Spartan-3A-DSP FPGA development board, suitable for processing VGA (640x480P) @ 60 Hz.
Programmable ASICs for Model Predictive Control
M.C. Martínez-Rodríguez, P. Brox, E. Tena, A.J. Acosta and I. Baturone
Conference · IEEE International Conference on Industrial Technology ICIT 2015
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Two configurable and programmable ASICs that implement piecewise-affine (PWA) functions have been designed in TSMC 90-nm technology in response to industry demands for embedded, fast response time, and low power solutions for Model Predictive Control (MPC). An automated model-based design flow can extract the parameters necessary for the configuration and the programming of both ASICs. Two application examples in the automotive field illustrate the design flow and the behavior of the ASICs.
Dedicated Hardware IP Module for Extracting Singular Points from Fingerprints
M.C. Martínez-Rodríguez, R. Arjona, P. Brox and I. Baturone
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2014
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In this paper a new digital dedicated hardware IP module for extracting singular points from fingerprints is presented (in particular convex cores). This module comprises four main blocks that implement an image directional extraction, a smoothing process, singular point detection and finally, a post processing to obtain the exact location of the singular point. A Verilog HDL description has been developed for this solution. The description has been synthesized and implemented in FPGAs from Xilinx.
Hardware implementation of smart embedded vision systems
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · Int. Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications VISIGRAPP 2014
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The research presented in this contribution is focused on the efficient hardware implementation of image processing algorithms that are present at different levels of a smart vision system. The system is conceived as a reconfigurable embedded device which, in turn, will be a node of a collaborative sensor network.
The inclusion of fuzzy logic techniques is explored to improve the performance of conventional vision algorithms.
FPGA based embedded systems for video processing
P. Brox, E. Calvo-Gallego and S. Sanchez-Solano
Conference · Workshop on the the Architecture of Smart Cameras WASC 2013
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Abstract not available
A Fuzzy System for Background Modeling in Video Sequences
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · International Workshop on Fuzzy Logic and Applications WILF 2013
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Many applications in video processing require the background modeling as a first step to detect the moving objects in the scene. This paper presents an approach that calculates the updating weight of a recursive adaptive filter using a fuzzy logic system. Simulation results prove the advantages of the fuzzy approach versus conventional methods such as temporal filters.
Reducing bit flipping problems in SRAM physical unclonable functions for chip identification
S. Eiroa, J. Castro, M.C. Martínez-Rodríguez, E. Tena, P. Brox and I. Baturone
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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Physical Unclonable functions (PUFs) have appeared as a promising solution to provide security in hardware. SRAM PUFs offer the advantage, over other PUF constructions, of reusing resources (memories) that already exist in many designs. However, their intrinsic noisy nature produces the so called bit flipping effect, which is a problem in circuit identification and secret key generation. The approaches reported to reduce this effect usually resort to the use of pre- and post-processing steps (such as Fuzzy Extractor structures combined with Error Correcting Codes), which increase the complexity of the system. This paper proposes a pre-processing step that reduces bit flipping problems without increasing the hardware complexity. The proposal has been verified experimentally with 90-nm SRAMs included in digital application specific integrated circuits (ASICs).
Real-Time FPGA Connected Component Labeling System
E. Calvo-Gallego, A. Cabrera-Aldaya, P. Brox and S. Sánchez-Solano
Conference · IEEE Int. Conf. on Electronics, Circuits, and Systems ICECS 2012
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The implementation of a connected component labeling algorithm (CCL) for real-time operation is presented in this paper. The algorithm, which was designed and implemented following a model-based methodology centered on Matlab/Simulink and Xilinx-System Generator, uses horizontal and vertical blanking periods to improve the quality of labeling and increase the operation speed. Its performance, with a VGA 640 x 480 P @ 60 Hz video, is shown by means of its integration on a complete video processing system over a Spartan-3A DSP 3400 development board.
Implementación sobre FPGA de un algoritmo de etiquetado en tiempo real
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA2012
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En esta comunicación se presenta una implementación de un algoritmo de etiquetado de componentes conexos en tiempo real que aprovecha los intervalos de supresión horizontal y vertical en la fuente de la imagen para mejorar la calidad del etiquetado y acelerar la frecuencia de trabajo. El diseño se ha llevado a cabo usando la herramienta System Generator de Xilinx lo que ha permitido reducir los tiempos de implementación y verificación lógica y funcional del modelo.
ASIC-in-the-loop methodology for verification of piecewise affine controllers
M. Martínez-Rodríguez, P. Brox, J. Castro, E. Tena, A. Acosta and I. Baturone
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations.
Un algoritmo en tiempo real para etiquetado de componentes conectados en imágenes
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano
Conference · Iberchip XVIII Workshop IWS 2012
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Esta comunicación presenta un algoritmo de dos pasadas para el etiquetado en tiempo real de los componentes conexos en una imagen. El algoritmo propuesto es una buena opción frente a otras alternativas de dos y múltiples pasadas ya que ha sido diseñado considerando que su implementación en FPGAs ofrezca un buen compromiso entre recursos ocupados y velocidad de operación. Se describen dos implementaciones hardware de este algoritmo, cuyo desarrollo se ha llevado a cabo siguiendo un flujo de diseño basado en la herramienta System Generator de Xilinx.
Librería de módulos IP para la implementación sobre FPGA de algoritmos de procesado de imágenes
L.M. Garcés, P. Brox, S. Sánchez-Solano and A. Cabrera
Conference · Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2011
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En esta comunicación se presenta una librería de módulos IP dedicada a la implementación de algoritmos básicos de procesado de imágenes sobre FPGA. La librería está compuesta por módulos que implementan filtros lineales y no-lineales en el dominio del espacio así como operadores morfológicos.
Design methodology for FPGA implementation of lattice piecewise-affine functions
M.C. Martínez-Rodríguez, I. Baturone and P. Brox
Conference · International Conference on Field-Programmable Technology FPT 2011
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This paper describes a design methodology to implement on FPGAs piecewise-affine (PWA) functions based on representation methods from the lattice theory. An off-line automatic processing starts at the algorithmic formulation of the problem, obtains the parameters required by a parameterized digital architecture, and ends with the bitstream to program an FPGA. The methodology has been proven to implement PWA functions on Xilinx FPGAs. The results are compared with other approaches for FPGA implementations of PWA functions. © 2011 IEEE.
Circuit implementation of piecewise-affine functions based on lattice representation
M.C. Martínez-Rodríguez, I. Baturone and P. Brox
Conference · European Conference on Circuit Theory and Design ECCTD 2011
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This paper introduces a digital architecture to implement piecewise-affine (PWA) functions based on representation methods from the lattice theory. Given an explicit and continuous PWA function, the parameters required to implement the lattice approach can be obtained by an off-line preprocessing that can be automated. Other advantages of the proposal are that it implements a continuous PWA function with potentially no errors and the minimum number of parameters to store. This has been proven experimentally by implementing the proposal in a Xilinx FPGA and comparing its performance with other implementations, all of them addressing a typical non linear control problem. © 2011 IEEE.
Digital implementation of hierarchical piecewise-affine controllers
I. Baturone, M.C. Martínez-Rodríguez, P. Brox, A. Gersnoviez and S. Sánchez-Solano
Conference · IEEE International Symposium on Industrial Electronics ISIE 2011
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This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the hierarchical solution have fewer inputs and/or coarser partitions, so that they can reduce considerably the hardware resources required and/or the time response of the controller. A design methodology aided by CAD tools is employed to design the parameters of the controller, implement its architecture in an FPGA, and verify the static and dynamic behavior of the digital implementation by applying hardware-in-the-loop testing. © 2011 IEEE.
Aplicación de XFuzzy 3 al procesado de imágenes basado en reglas
I. Baturone, P. Brox and R. Arjona
Conference · XIV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2010
resumen
Los entornos de desarrollo de sistemas fuzzy se han empleado normalmente para diseñar sistemas de control y de toma de decisiones pero apenas para diseñar sistemas de procesado de imágenes, a pesar de que este campo cuenta ya con numerosas soluciones basadas en Lógica Fuzzy. En este artículo se muestra cómo el entorno Xfuzzy 3 desarrollado en el Instituto de Microelectrónica de Sevilla posee la versatilidad necesaria para abordar el diseño de estos sistemas, facilitando su descripción, verificación, ajuste y síntesis.
Tuning of a hierarchical fuzzy system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2010
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The tuning of hierarchical fuzzy systems are not supported by the majority of CAD tools available at the market currently. The XFSL tool integrated into Xfuzzy 3 allows the tuning of complex fuzzy systems, for instance, hierarchical systems with modules in cascade. The authors propose the use of this tool for tuning a complex fuzzy system for video de-interlacing in this paper. The parameters obtained after tuning are proven by de-interlacing a wide battery of sequences. The use of tuning techniques improves the quality of de-interlacing and provides an algorithm simplification that facilitates its hardware implementation.
Diseño de sistemas difusos para procesado de imágenes con xfuzzy 3
I. Baturone, P. Brox and R. Arjona
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2010
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La presente comunicación describe la utilización de un software de libre
distribución, Xfuzzy 3, para ilustrar la aplicación de sistemas difusos al
procesamiento de imágenes, en concreto, al problema del aumento de resolución.
El proceso de diseño de sistemas difusos quedará cubierto por el uso de las
herramientas CAD de descripción, verificación, identificación, aprendizaje y
simplificación del entorno XFuzzy en su versión 3.3, que facilitan al alumno la
comprensión de todos los pasos del proceso.
Aplicación de Xfuzzy3 al procesado de imágenes basado en reglas
I. Baturone, P. Brox and R. Arjona
Conference · XV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2010
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Los entornos de desarrollo de sistemas fuzzy se han empleado normalmente para diseñar sistemas de control y de toma de decisiones pero apenas para diseñar sistemas de procesado de imágenes, a pesar de que este campo cuenta ya con numerosas soluciones basadas en Lógica Fuzzy. En este artículo se muestra cómo el entorno Xfuzzy 3 desarrollado en el Instituto de Microelectrónica de Sevilla posee la versatilidad necesaria para abordar el diseño de estos sistemas, facilitando su descripción, verificación, ajuste y síntesis.
Tuning of a hierarchical fuzzy system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE World Congress on Computational Intelligence WCCI 2010
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The tuning of hierarchical fuzzy systems are not supported by the majority of CAD tools available at the market currently. The XFSL tool integrated into Xfuzzy 3 allows the tuning of complex fuzzy systems, for instance, hierarchical systems with modules in cascade. The authors propose the use of this tool for tuning a complex fuzzy system for video de-interlacing in this paper. The parameters obtained after tuning are proven by de-interlacing a wide battery of sequences. The use of tuning techniques improves the quality of de-interlacing and provides an algorithm simplification that facilitates its hardware implementation.
Un algoritmo de desentrelazado adaptativo con la repetición de imágenes basado en lógica difusa
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Iberchip XV Workshop IWS 2009
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Esta comunicación presenta un interpolator temporal basado en lógica difusa que es utilizado para el desentrelazado de la señal de vídeo. El objetivo es que dicho interpolador sea capaz de aprovechar una caracterísctica que cada vez es más frecuente en las secuencias, debido a los estándares de conversión entre distintos formatos de transmisión, como es la repetición de imágenes. Este nuevo interpolador es incluido en un algoritmo adaptativo en función del movimiento, obteniendo una técnica de desentrelazado muy competitiva frente a otros algoritmos que son actualmente utilizados en ASICs de dispositivos comerciales de altas prestaciones. Los resultados de simulación obtenidos al desentrelazar secuencias de distintos materiales (film, vídeo e híbrido) muestran la superioridad del algoritmo propuesto.
Síntesis hardware de módulos de inferencia difusos mediante herramientas de diseño de DSP
M. Brox, S. Sánchez-Solano, P. Brox, I. Baturone, A. Barriga and A. Gersnoviez
Conference · VIII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2008
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En esta comunicación se describe una nueva estrategia de desarrollo de sistemas de control basados en lógica difusa mediante un flujo de diseño que combina las herramientas de modelado y simulación del entorno Matlab y las herramientas de síntesis e implementación de FPGAs de Xilinx. Apoyada en el uso de una librería de módulos específicos para sistemas difusos, esta estrategia acelera las etapas de descripción, síntesis y verificación funcional de los sistemas bajo desarrollo.
A motion and edge adaptive interlaced-to-progressive conversion using fuzzy logic-based systems
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Information Processing and Management of Uncertainty in Knowledge-based Systems IPMU 2008
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This paper presents an algorithm for video de-interlacing. The approach uses three fuzzy logic-based systems to adapt the interpolation strategy to the presence of motion and edges. Furthermore, the algorithm is able to deal with any kind of TV material independently of the source used to acquire the scene. Extensive simulations of standard and real sequences prove the efficiency of the proposed algorithm.
FPGA-based implementation of a fuzzy motion adaptive de-interlacing algorithm
P. Brox, S. Sánchez-Solano and I. Baturone
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2007
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This paper surveys the hardware implementation of a de-interlacing algorithm on Field-Programmable Technology for real-time processing. The algorithm presented evaluates the level of motion at each pixel, and determines the interpolation between a spatial and a temporal method according to the presence of motion. To achieve it the algorithm employs an hierarchical structure with three simple fuzzy systems. The first one performs a set of fuzzy rules to apply reasoning in order to detect motion; the second one selects the most convenient direction to implement an edge-dependent line average method; and the third one is used to choose the most adequate temporal method.
The hardware implementation of this algorithm combines pipeline architecture with a parallel processing of fuzzy rules to accelerate the computation. As result an efficient implementation is developed in terms of computational time and hardware cost.
Aplicación de técnicas de interpolación basadas en lógica difusa al procesado de imágenes de video
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Iberchip XIII Workshop IWS 2007
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Muchas tareas básicas de procesado de imágenes requieren la manipulación de grandes volúmenes de información que, en ocasiones, puede resultar ambigua y/o imprecisa como consecuencia de las características propias de las imágenes (gran cantidad de detalles con grandes contrastes de valores de luminancia y secuencias con un elevado grado de movimiento) o de los defectos de las mismas (presencia de ruido, falta de nitidez, etc.). En esta comunicación se analizan nuevas técnicas de interpolación basadas en lógica difusa que proporcionan soluciones eficaces para dos aplicaciones típicas de procesado de imágenes: el desentrelazado de señales de vídeo y el incremento de resolución de imágenes.
A fuzzy motion adaptive de-interlacing algorithm capable of detecting field repetition patterns
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE International Symposium on Intelligent Signal Processing WISP 2007
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A new motion adaptive algorithm for de-interlacing video is proposed in this paper. It employs two fuzzy systems to interpolate the missing lines of the transmission. One fuzzy system is used to evaluate the motion level at the current pixel, and a second one selects the most adequate temporal interpolation method. The combination of both systems provides an effective result with a low cost in term of hardware resources.
Using xfuzzy environment for the whole design of fuzzy systems
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano, A. Barriga, P. Brox, A.A. Gersnoviez and M. Brox
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2007
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Since 1992, Xfuzzy environment has been improving to ease the design of fuzzy systems. The current version, Xfuzzy 3, which is entirely programmed in Java, includes a wide set of new featured tools that allow automating the whole design process of a fuzzy logic based system: from its description (in the XFL3 language) to its synthesis in C, C++ or Java (to be included in software projects) or in VHDL (for hardware projects). The new features of the current version have been exploited in different application areas such as autonomous robot navigation and image processing.
New features of the fuzzy logic development environment Xfuzzy
A. Barriga, S. Sánchez-Solano, I. Baturone, D.R. López, F.J. Moreno-Velo, F. Montesino, P. Brox and N.M. Hussein
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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The characteristics of the new version of the fuzzy systems development environment Xfuzzy is presented. The environment covers the aspects related to the specification, verification, adjustment and implementation of fuzzy systems. It is an open environment (in the sense that the user can define many functional and structural aspects) and a free distribution tool that allows proving new formalisms and helps the definition and implementation of complex systems.
Image Enlargement using the Fuzzy-ELA Algorithm
P. Brox, I. Baturone, S. Sánchez-Solano and A. Barriga
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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The increase of resolution is one of the most important tasks in image processing. Traditional interpolation algorithms perform a linear interpolation between the closest pixels in the image. This strategy may introduce mistakes specially in the reconstruction of edges and zones with high contrast luminance values. The use of a novel interpolation algorithm for image enlargement is presented in this paper. It employs a fuzzy logic-system to adapt the interpolation to the presence of edges in the image, achieving good results at expense of a low increment in the computational cost.
Fuzzy Motion Adaptive Algorithm for Video De-interlacing
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutiérrez-Ríos and F. Fernández-Hernández
Conference · International Conference on Knowledge-Based and Intelligent Information and Engineering Systems KES 2006
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A motion adaptive algorithm for video de-interlacing is presented in this paper. It is based on a fuzzy inference system, which performs an interpolation between two linear techniques as a function of the motion level. Fuzzy systems with different number of 'if-then' rules have been analyzed and compared in terms of complexity as well as efficiency in de-interlacing benchmark video sequences.
Algoritmo adaptativo con el grado de movimiento para el desentrelazado de vídeo
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutiérrez-Ríos and F. Fernández-Hernández
Conference · XIII Congreso Español de Tecnologías y Lógica Fuzzy ESTYLF 2006
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En esta comunicación se presenta un algoritmo adaptativo con el movimiento para el desentrelazado de vídeo. Se basa en un sistema de inferencia difuso, que realiza una interpolación entre dos técnicas lineales en función del grado de movimiento. Se ha realizado un estudio de diferentes sistemas difusos con distinto número de funciones de pertenencia, analizándose el grado de complejidad de los mismos frente a su eficacia desentrelazando varias secuencias de vídeo.
A Fuzzy Motion Adaptive Algorithm for Interlaced-to-Progressive Conversion
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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Interlaced-to-progressive algorithms are currently required by video format conversion systems in order to display a progressive scanning used in modern visualization equipments. Deinterlacing algorithms use interpolation techniques to calculate missing pixels in transmitted fields. A motion adaptive algorithm which employs fuzzy logic to adapt the interpolation strategy to the presence of motion in the images is proposed in this paper. The performance of this new approach is evaluated by extensive simulation of different video sequences.
Directional motion adaptive fuzzy method for video de-interlacing
J. Gutiérrez-Ríos, F. Fernández-Hernández, P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Conference · Artificial Neural Networks in Engineering ANNIE 2005
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The procedure employed to make de-interlacing of video sequences has great influence in the quality of the obtained image. Reaching good results is not possible if dynamical characteristics of the processed image are not considered. On the other hand, the gradual adjust of the de-interlacing procedure as a function of the motion detected in each pixel of the image is a powerful method that is able to be realised by means of fuzzy inference. Detection of motion direction in each pixel of a frame becomes important in order to choose inclination in the spatial interpolation operations. In this paper we start from a fuzzy algorithm proposed by Van de Ville et al. to succeed in a family of more efficient algorithms under the point of view of execution speed and quality. These algorithms are based on convolution techniques (in substitution of the sum-prod norms) that are able to create a good emphasising distribution on the input variables.
Progressive scan conversion based on edge-dependent interpolation using fuzzy logic
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Conf. of the European Society for Fuzzy Logic and Technology & 11th French Days on Fuzzy Logic and Applications EUSFLAT-LFA 2005
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De-interlacing algorithms realize the interlaced to progressive conversion required in many applications. The most cost efficient are intra-field techniques which interpolate pixels of the same field. Some of these methods use the upper and lower line pixels. Among them, the ELA algorithm is widely employed since it reconstructs the edges of the de-interlaced image with more accuracy eliminating nondesired problems such as blurring and staircase effects. However, the ELA algorithm does not perform well when there are non clear edges or in presence of noise. In order to reduce these drawbacks, a new algorithm is presented in this paper. It is based on a simple fuzzy system which models heuristic rules to improve the ELA algorithm. Two enhancements of this new algorithm are also presented in this paper. Simulation results of video sequences prove the advantageous of the new algorithms.
Interlaced to progressive scan conversion using a fuzzy edge-based line average algorithm
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE International Workshop on Intelligent Signal Processing WISP 2005
resumen
De-interlacing methods realize the interfaced to progressive conversion required in many applications. Among them, intra-field methods are widely used for their good trade off between performance and computational cost. In particular, the ELA algorithm is well-known for its advantages in reconstructing the edges of the images, although it degrades the image quality where the edges are not clear. The algorithm proposed in this paper uses a simple fuzzy system which models heuristic rules to improve the ELA rules. It can be implemented easily in software and hardware since the increase in computational cost is very low. Simulation results are included to illustrate the advantages of the proposed fuzzy ELA algorithm in de-interlacing, non noisy and noisy images.
Fuzzy logic activities at the Microelectronics Institute of Seville
A. Barriga, S. Sánchez-Solano, I. Baturone, F. Moreno-Velo, P. Brox, F. Montesino, N.M. Hussein, M. Brox and A. Gersnoviez
Conference · XVI Italian Workshop on Neural Nets WIRN 2005
resumen
In this communication we present the activities related to the development of fuzzy logic based systems at the Microelectronics Institute of Seville (Spain). These activities regard with the design of circuits and systems that operate in fuzzy logic, the development of CAD tools for fuzzy logic and the accomplishment of applications that use fuzzy logic in the resolution of certain problems.
FPGA implementation of a fuzzy based video de-interlacing algorithm
P. Brox, S. Sánchez-Solano, I. Baturone and A. Barriga
Conference · Conference on VLSI Circuits and Systems II, 2005
resumen
De-interlacing algorithms are used to convert interlaced video into progressive scan format. Among the different techniques reported in the literature, motion adaptive de-interlacing techniques that combine spatial and temporal interpolation according to the presence of motion achieve good results with a low computational cost. This paper presents the FPGA implementation of a motion adaptive algorithm which employs fuzzy logic in detecting motion and edges. Motion, which is evaluated at each pixel of the deinterlaced frame, determines the interpolation between an enhanced edge-dependent line average method and field insertion. Extensive simulations with video sequences show the advantages performance of the proposed method over other well-known de-interlacing techniques. The hardware implementation of the algorithm has been carried out on a FPGA obtaining a low-cost solution for real-time processing.
Codiseño Hardware/Software de controladores difusos mediante módulos de propiedad intelectual
A. Barriga, I. Barturone, P. Brox, A. Cabrera, F.J. Moreno and S. Sánchez-Solano
Conference · VI Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2004
resumen
El uso de técnicas de diseño basadas en módulos de propiedad intelectual (IP) constituye una alternativa válida para salvar la creciente distancia entre los recursos proporcionados por las actuales tecnologías de fabricación de circuitos integrados y la productividad alcanzada por los diseñadores de sistemas. Esta comunicación describe el desarrollo de un sistema de control basado en lógica difusa mediante una técnica de codiseño hardware/software que combina un procesador de propósito general disponible como módulo-IP y hardware específico para la síntesis del módulo de inferencia. La implementación física se ha llevado a cabo mediante una plataforma de desarrollo basada en FPGAs, lo que permite la realización de todo el sistema como un SoPC (System on Programmable Chip).
Development of fuzzy control systems on programmable chips: Application to motion planning of mobile robots
A. Cabrera, S. Sánchez-Solano, I. Baturone, F. Moreno-Velo, P. Brox and A. Barriga
Conference · International Symposium on Robotics and Applications ISORA 2004
resumen
This paper describes the realization of embedded fuzzy control systems for planning the motion of autonomous mobile robots. The development of the controllers is carried out by means of a reconfigurable platform based on FPGAs. This platform combines a general-purpose processor with specific hardware to implement fuzzy inference modules, thus allowing the comparison between a fully software solution and others based on hybrid hardware/software techniques. Both the processing system and the inference modules are configurable using available CAD tools, which make the development of the controllers easier.
Implementación sobre FPGAs de sistemas difusos programables
S. Sánchez-Solano, A. Cabrera, C.J. Jiménez, P. Brox, I. Baturone and A. Barriga
Conference · Workshop IBERCHIP 2003
resumen
El número de aplicaciones electrónicas que utilizan soluciones basadas en lógica difusa se ha incrementado considerablemente en los últimos años y, de forma paralela, se han desarrollado nuevas herramientas de CAD que contemplan diferentes técnicas de implementación para este tipo de sistemas. De entre ellas, el uso de arquitecturas específicas de procesado implementadas sobre FPGAs presenta como principales ventajas una buena relación 'coste-rendimiento' y un ciclo de desarrollo aceptablemente corto. En esta comunicación se analizan las distintas facilidades de síntesis que proporciona el entorno de diseño Xfuzzy para la implementación de sistemas difusos programables que aprovechen los recursos disponibles en las actuales familias de FPGAs.
VHDL high level modelling and implementation of fuzzy systems
A. Barriga, S. Sánchez-Solano, P. Brox, A. Cabrera and I. Baturone
Conference · International Workshop on Fuzzy Logic and Applications WILF 2003
resumen
In this paper we illustrate a fuzzy logic system design strategy based on a high level description. Employing this high level description, the knowledge base is described in a language in appearance close to the natural language with the particularity that it uses a hardware description language (VHDL) directly synthesizable on an FPGA circuit. In addition, we analyze FPCA implementations of different fuzzy inference hardware architectures in order to characterize them in terms of area and speed.
Libros
White Paper 11: Artificial Intelligence, Robotics and Data Science
J.E. Marco de Lucas, M.V. Moreno-Arribas, S. Degli-Esposti, C. Sierra, F. Manyà, A. Colomé, N. Osman, D. López, J. Ramasco, L. Lloret-Iglesias, G. Alenyà, J. Villagrá, M.D. del Castillo, M. Schorlemmer, P. Noriega, T. Ausín, T. Serrano, A. Oyanguren, D. Arroyo-Guardeño and P. Brox
Book · Libros Blancos. Desafíos Científicos 2030 del CSIC, 198 p, 2021
resumen
link
CSIC white paper on Artificial Intelligence, Robotics and Data Science sketches a preliminary roadmap for addressing current R&D challenges associated with automated and autonomous machines. More than 50 research challenges investigated all over Spain by more than 150 experts within CSIC are presented in eight chapters. Chapter One introduces key concepts and tackles the issue of the integration of knowledge (representation), reasoning and learning in the design of artificial entities. Chapter Two analyses challenges associated with the development of theories -and supporting technologies- for modelling the behaviour of autonomous agents. Specifically, it pays attention to the interplay between elements at micro level (individual autonomous agent interactions) with the macro world (the properties we seek in large and complex societies). While Chapter Three discusses the variety of data science applications currently used in all fields of science, paying particular attention to Machine Learning (ML) techniques, Chapter Four presents current development in various areas of robotics. Chapter Five explores the challenges associated with computational cognitive models. Chapter Six pays attention to the ethical, legal, economic and social challenges coming alongside the development of smart systems. Chapter Seven engages with the problem of the environmental sustainability of deploying intelligent systems at large scale. Finally, Chapter Eight deals with the complexity of ensuring the security, safety, resilience and privacy-protection of smart systems against cyber threats.
Fuzzy logic-based algorithms for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Book · STUDFUZZ, vol. 246, 184 p, 2010
resumen
link
The Fuzzy Logic research group of the Microelectronics Institute of Seville is composed of researchers who have been doing research on fuzzy logic since the beginning of the 1990s. Mainly, this research has been focused on the microelectronic design of fuzzy logic-based systems using implementation techniques which range from ASICs to FPGAs and DSPs. Another active line was the development of a CAD environment, named Xfuzzy, to ease such design. Several versions of Xfuzzy have been and are being currently developed by the group. The addressed applications had basically belonged to the control field domain. In this sense, several problems without a linear control solution had been studied thoroughly. Some examples are the navigation control of an autonomous mobile robot and the level control of a dosage system.
This book is organized in five chapters. In Chapter 1, some basic concepts are explained to completely understand the contribution of the algorithms developed in this research work. The evaluation of how motion is present and how it influences on de-interlacing is studied in Chapter 2. The design options of the proposed fuzzy motion-adaptive de-interlacing algorithm is studied in Chapter 3. A spatial interpolator that adapts the interpolation to the presence of edges in a fuzzy way is developed in Chapter 4. A temporal interpolator that adapts the strategy of the interpolation to possible repetition of areas of fields is presented in Chapter 5. Using both interpolators in the fuzzy motion-adaptive algorithm described in Chapter 3 clearly improves the de-interlaced results.
Capítulos de libros
A fuzzy edge-dependent interpolation algorithm
P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Book Chapter · Soft Computing in Image Processing: Recent Advances, STUDFUZZ, vol. 210, pp 157-183, 2007
resumen
doi pdf
Images have always been very important in human life. Their applications range from primitive communication between humans of all ages to advanced technologies in the industrial, medical and military field. The increased possibilities to capture and analyze images have contributed to the largeness that the scientific field of "image processing" has become today. Many techniques are being applied, including soft computing.
Directional motion adaptive fuzzy method for video de-interlacing
J. Gutiérrez-Ríos, F. Fernández-Hernández, P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Book Chapter · Intelligent Engineering Systems Through Artificial Neural Networks, pp 567-577, 2005
resumen
The procedure employed to make de-interlacing of video sequences has great influence in the quality of the obtained image. Reaching good results is not possible if dynamical characteristics of the processed image are not considered. On the other hand, the gradual adjust of the de-interlacing procedure as a function of the motion detected in each pixel of the image is a powerful method that is able to be realised by means of fuzzy inference. Detection of motion direction in each pixel of a frame becomes important in order to choose inclination in the spatial interpolation operations. In this paper we start from a fuzzy algorithm proposed by Van de Ville et al. to succeed in a family of more efficient algorithms under the point of view of execution speed and quality. These algorithms are based on convolution techniques (in substitution of the sum-prod norms) that are able to create a good emphasising distribution on the input variables.
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