Encontrados resultados para:
Autor: Rafaella B. Fiorelli Martegani
Año: Desde 2002
Artículos de revistas
CMOS Front End for Interfacing Spin-Hall Nano-Oscillators for Neuromorphic Computing in the GHz Range
R. Fiorelli, E. Peralias, R. Mendez-Romero, M. Rajabali, A. Kumar, M. Zahedinejad, J. Akerman, F. Moradi, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · Electronics, vol. 12, no. 1, article 230, 2023
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Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4-20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due to their extremely low signal level and high impedance at their output, as well as their microwave-range operating frequency, discerning whether the SHNO is oscillating or not carries a great challenge when its state read-out circuit is implemented using CMOS technologies. This paper presents the first CMOS front-end read-out circuitry, implemented in 180 nm, working at a SHNO oscillation frequency up to 4.7 GHz, managing to discern SHNO amplitudes of 100 mu V even for an impedance as large as 300 ohm and a noise figure of 5.3 dB(300 ohm). A design flow of this front end is presented, as well as the architecture of each of its blocks. The study of the low-noise amplifier is deepened for its intrinsic difficulties in the design, satisfying the characteristics of SHNOs.
Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction
R. Fiorelli, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 3, pp 606-619,2020
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This paper presents a SAR converter based mixed-signal multiplier for the feature extraction of neural signals using quadratic operators. After a thorough analysis of design principles and circuit-level aspects, the proposed architecture is explored for the implementation of two quadratic operators often used for the characterization of neural activity, the moving average energy (MAE) operator and the nonlinear energy operator (NEO). Programmable chips for both operators have been implemented in a HV-180 nm CMOS process. Experimental results confirm their suitability for energy computation and action potential detection and the accomplished area×power performance is compared to prior art. The MAE and NEO prototypes, at a sampling rate of 30kS/s, consume 116 nW and 178 nW, respectively, and digitize both the input neural signal and the operator outcome, with no need for digital multipliers.
A Sub-µW Reconfigurable Front-End for Invasive Neural Recording that Exploits the Spectral Characteristics of the Wideband Neural Signal
J.L. Valtierra, M. Delgado-Restituto, R. Fiorelli and A. Rodriguez-Vazquez
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp 1426-1437, 2020
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This paper presents a sub- µW ac-coupled reconfigurable front-end for invasive wideband neural signal recording. The proposed topology embeds filtering capabilities enabling the selection of different frequency bands inside the neural signal spectrum. Power consumption is optimized by defining specific noise targets for each sub-band. These targets take into account the spectral characteristics of wideband neural signals: local field potentials (LFP) exhibit l/f(x) magnitude scaling while action potentials (AP) show uniform magnitude across frequency. Additionally, noise targets also consider electrode noise and the spectral distribution of noise sources in the circuit. An experimentally verified prototype designed in a standard 180 nm CMOS process draws 815 nW from a 1 V supply. The front-end is able to select among four different frequency bands (modes) up to 5 kHz. The measured input-referred spot-noise at 500 Hz in the LFP mode (1 Hz - 700 Hz) is 55 nV/root Hz while the integrated noise in the AP mode (200 Hz - 5 kHz) is 4.1 µVrms. The proposed front-end achieves sub-µW operation without penalizing other specifications such as input swing, common-mode or power-supply rejection ratios. It reduces the power consumption of neural front-ends with spectral selectivity by 6.1x and, compared with conventional wideband front-ends, it obtains a reduction of 2.5x.
Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs
R. Fiorelli, N. Barabino, F. Silveira and E. Peralias
Journal Paper · Circuits Systems and Signal Processing, vol. 39, pp 2796-2821, 2020
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This paper presents a simple but accurate normalized nonlinear large-signal semiempirical MOS transistor model to be used in monolithic RF Class A-to-C PAs. MOS transistor characteristics, saved in lookup tables, are extracted for different PVT corners, allowing the study of the PA performance spread. Model accuracy is ratified by the excellent matching obtained when comparing data algebraically calculated with electrical simulations of hundreds of PAs, and with the measurement data of a fabricated 2.4 GHz PA.
Offset-calibration with time-domain comparators using inversion-mode varactors
R. Fiorelli, M. Delgado-Restituto and A Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Brief, vol. 67, no. 1, pp 47-51, 2020
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This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit SAR-ADC. The design, fabricated in a 0.18μm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.
A Multilevel Bottom-up Optimization Methodology for the Automated Synthesis of RF Systems
F. Passos, E. Roca, J. Sieiro, R. Fiorelli, R. Castro-López, J.M. López-Villegas and F.V. Fernández
Journal Paper · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 3, pp 560-571, 2020
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In recent years there has been a growing interest in electronic design automation methodologies for the optimizationbased design of radiofrequency circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle radiofrequency systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this work, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multi-objective optimization algorithms are used to design an entire radiofrequency system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.
Semi-empirical RF MOST model for CMOS 65nm technologies: Theory, extraction method and validation
R. Fiorelli and E. Peralías
Journal Paper · Integration, the VLSI Journal, vol. 52, pp 228-236, 2016
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This paper presents a simple but accurate semi-empirical model especially focused on 65. nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5. GHz and 5.3. GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.
MOST Moderate-Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs
R. Fiorelli, F. Silveira and E. Peralias
Journal Paper · IEEE Transactions on Microwave Theory and Techniques, vol. 62, no. 3, pp. 556-566, 2014
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In this paper, the MOS transistor (MOST) moderate- inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto-optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684μW, an NF of 4.36dB, a power gain of 9.7dB, and a third-order intermodulation intercept point of -4dBm with load and source resistances of 50Ω
LC-VCO design optimization methodology based on the g(m)/I(D) ratio for nanometer CMOS technologies
R. Fiorelli, E. Peralias and F. Silveira
Journal Paper · IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 7, pp 1822-1831, 2011
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In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 mu A from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier.
Alternate test of LNAs through ensemble learning of on-chip digital envelope signatures
M.J. Barragán, R. Fiorelli, G. Léger, A. Rueda and J.L. Huertas
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 27, no. 3. pp 277-288, 2011
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This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. A new Figure of Merit (FOM) is proposed to evaluate the prediction accuracy of the statistical model, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445 GHz low-power LNA and a simple envelope detector, and has been developed in a 90 nm CMOS technology. Post-layout simulations are provided to verify the functionality of the proposed test technique.
On-chip characterization of RF systems based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Journal Paper · Electronics Letters, vol. 46, no. 1, pp 36-37, 2010
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A simple on-chip procedure for testing embedded RF blocks is presented. It is based on the detection and spectral analysis of the two-tone response envelope of the device under test (DUT). A main difference with similar methods is its inherent simplicity, avoiding a preprocessing stage and resorting to simpler circuitry to process the envelope. As a consequence, the main nonlinearity specifications of the DUT can be easily estimated from the envelope signal without the need of expensive RF test equipment.
Congresos
A High TCMRR, Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation
J.L. Valtierra, R. Fiorelli, N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2019
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This paper describes a multichannel bidirectional front-end for true closed-loop neuromodulation. Stimulation artefacts are reduced via a 4-channel H-bridge current source sharing stimulators to minimize residual charge drops in the electrodes. The 4-channel sensing front-end is capable of multichannel sensing in the presence of artefacts as a result of its high total common-mode rejection ratio (TCMRR) that accounts for CMRR drop due to electrode mismatch. Experimental verification of a prototype fabricated in 180 nm process shows a stimulator front-end with 0.059% charge balance and 0.275 nA DC current error. The recording front-end consumes 3.24 μW, tolerates common-mode interference up to 1 Vpp and shows a TCMRR > 66 dB for 500 mVpp inputs.
A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression
N. Pérez-Prieto, R. Fiorelli, J.L. Valtierra, P. Pérez-García, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2019
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This paper describes a low-noise, low-power and high dynamic range analog front-end intended for sensing neural signals. In order to reduce interface area, a 32-channel multiplexer is implemented on circuit input. Furthermore, a spatial delta encoding is proposed to compress the signal range. A differential artifact compression algorithm is implemented to avoid saturation in the signal path, thus enabling reconstruct or suppressing artifacts in digital domain. The proposed design has been implemented using 0.18 μm TSMC technology. Experimental results shows a power consumption per channel of 1.0 μW, an input referred noise of 1.1 μVrms regarding the bandwidth of interest and a dynamic range of 91 dB.
A Sub- µW Reconfigurable Front-End for Invasive Neural Recording
J.L. Valtierra, R. Fiorelli, M. Delgado-Restituto and A. Rodriguez-Vazquez
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2019
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This paper presents a sub-microwatt ac-coupled neural amplifier for the purpose of neural signal sensing. A proposed reconfigurable topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180nm CMOS process draws 803nW from a 1V source. The measured input-referred spot-noise at 150Hz is 130nV / Hz while the integrated noise in the 200Hz-5kHz band is 3.6µV rms.
Mixed-Signal Quadratic Operators for the Feature Extraction of Neural Signals
M. Delgado-Restituto, R. Fiorelli, M. Carrasco-Robles and A. Rodríguez-Vázquez
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2016
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This paper presents design principles for reusing charge-redistribution SAR ADCs as digital multipliers. This is illustrated with an 8-b fully-differential rail-to-rail SAR ADC/multiplier, designed in a 180nm HV CMOS technology. This reconfigurability property can be exploited for the extraction of product-related features in neural signals, such as energy content, or for the discrimination of spikes using the Teager operator.
A 76nw, 4ks/S 10-Bit SAR ADC with Offset Cancellation for Biomedical Applications
M. Delgado-Restituto, M. Carrasco Robles, R. Fiorelli, A.J. Gines-Arteaga and A. Rodríguez-Vázquez
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2016
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This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180 nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2 nW at 4 kS/s and achieves 9.5-b ENOB.
A Low-Energy 10-bit SAR ADC with Embedded Offset Cancellation
M. Delgado-Restituto, M. Carrasco-Robles, R. Fiorelli, A.J. Gines-Arteaga and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
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This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180 nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2 nW at 4 kS/s and achieves 9.5-b ENOB.
Effects of capacitors non-idealities in un-even split-capacitor array SAR ADCs
R. Fiorelli, O. Guerra, R. del Rio and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
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This paper studies the effects of capacitors non-idealities in the performance of un-even split-capacitor SAR ADCs. Also, election of the m and l bits of MSB and LSB capacitors banks, respectively, is studied to reduce SAR errors. To exemplify and quantify the non-idealities, MOM capacitors are used. In particular, MOM layout parasitics and effective capacitors' value is obtained with an electrical extraction tool using a flattened view of the MOM. Effects of capacitors layout placement in the SAR and their surroundings in the effective capacitance value are quantified. A quantitative study of a 10-bit un-even split-capacitor SAR is done for different combinations of m and l bits. Finally, a qualitative set of guidelines to choose the distribution of these bits is listed.
Semi-empirical model of MOST and passive devices focused on narrowband RF blocks
R. Fiorelli, F. Silveira, A. Rueda and E. Peralías
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2012
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This paper presents a semi-empirical modeling of MOST and passive elements to be used in narrowband radiofrequency blocks for nanometer technologies. This model is based on a small set of look-up tables (LUTs) obtained via electrical simulations. The MOST description is valid for all-inversion regions of MOST and the data is extracted as function of the gm=ID characteristic; for the passive devices the LUTs include a simplified model of the element and its principal parasitic at the working frequency f0. These semi-empirical models are validated by designing a set of 2.4-GHz LNAs and 2.4-GHz and 5-GHz VCOs in three different MOST inversion regions.
An all-inversion-region MOST design methodology applied to a ratioless differential LC-VCO
R. Fiorelli, F. Silveira and E. Peralías
Conference · Conference on Ph.D. Research in Microelectronics and Electronics PRIME 2012
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This paper presents a general optimization method- ology for analog blocks in RF applications, with CMOS nanome- ter technologies, based on the complete exploration of all-in- version regions of MOS transistor (MOST). The fundamental tool is the systematic use of the MOST gm/ID technique and the description of the real behavior of all devices by means of semi-empirical models. To exemplify this technique, the differen- tial ratioless cross-coupled LC-tank voltage controlled oscillator (LC-VCO) circuit is studied. The implemented design flow minimizes the LC-VCO phase noise considering the constraints of current consumption, output common-mode voltage and output amplitude. To verify the method, six LC-VCO were designed and validated by comparing them with the corresponding electrical simulations.
Improving the accuracy of RF alternate test using multi-VDD conditions: Application to envelope-based test of LNAs
M.J. Barragán-Asián, R. Fiorelli-Martegani, G. Leger, A. Rueda and J.L. Huertas-Díaz
Conference · Asian Test Symposium ATS 2011
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This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.
2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS
R. Fiorelli, A. Villegas, E. Peralías, D. Vázquez and A. Rueda
Conference · European Conference on Circuit Theory and Design ECCTD 2011
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A 2.4-GHz CMOS single ended-input differential-output front-end built with a common source low noise amplifier (CS-LNA) and a switched transconductor mixer (SW-MIX) is presented. The circuit is designed and optimized to work in a ZigBee receiver. Since this is a low power consumption standard, a single-ended LNA is preferred over a fully-differential topology because it leads to lower cost in area and power consumption. Also, moderate and weak inversions regions were selected for the operation of the principal transistors. The front-end prototype has been implemented in a 90 nm RF process and occupies a chip area of 0.74 mm2 including on-chip inductors. Very competitive results are observed: a maximum conversion gain (CG) of 30 dB, a DSB noise figure of 7.5 dB, a maximum IIP3 of -12.8 dBm and IIP2 of 14.4 dBm while it consumes 4.7 mW from a 1.2 V supply. © 2011 IEEE.
A fully differential monolithic 2.4 GHz PA for IEEE 802.15.4 based on efficiency design flow
R. Fiorelli, E. Peralías, N. Barabino and F. Silveira
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2010
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This work presents the design and implementation of a differential class C power amplifier (PA) in a 90nm CMOS technology, specified to be used in a IEEE802.15.4 low power transceiver. The design is based on a PA efficiency design flow implemented in MATLAB which enables to reach very good power efficiency figures. The method is validated comparing MATLAB predicted data and post-layout SpectreRF simulated results. Post-layout simulations show a Power Amplifier Efficiency (PAE) of 46.5%, a power gain Gpow of 26dB, and an output power Pout of 1.9dBm for a 100 Ohm load, working with a supply voltage VDD = 0.65V and a MOS DC current ID of 4.6mA. The total area is 700um x 710um. ©2010 IEEE.
Low-cost signature test of RF blocks based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE European Test Symposium ETS 2010
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This paper presents a novel and low-cost methodology that can be used for testing RP blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach. © 2010 IEEE.
Efficiency based design flow for fully-integrated class C RF power amplifiers in nanometric CMOS
N. Barabino, R. Fiorelli and F. Silveira
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
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In this work a design flow for class C radiofrequency (RF) power amplifiers (PA) with on-chip output networks in nanometric technologies is presented. This is a new parasitic-aware method intended to reduce time-consuming iterations which are normally required in fully-integrated designs. Unlike other methods it is based on actual transistors DC characteristics and inductors data -both extracted by simulation-. Starting from the output power specifications a design space map is generated showing the trade-offs between efficiency and components sizing, thus enabling the selection of the most appropriate design that satisfies the harmonic distortion requirements. As a proof of concept of the proposed method, a design example for an IEEE 802.15.4 2.4 GHz PA in a 90 nm CMOS technology is presented. ©2010 IEEE.
Phase noise-consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies
R. Fiorelli, F. Silveira and E. Peralías
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2009
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An LC-VCO design optimization, based on the gm/ID methodology, is presented throughout this work, highlighting how, by applying all regions of inversion of the MOS transistor, the trade-o! between phase noise and current consumption can be optimized for the application. Both transistor compact model equations and transistor data acquired from simulation are used to obtain gm/ID curves as well as normalized capacitances. Influence of tank elements' characteristics in the VCO performance is also discussed. Results of applying the methodology in the design of two VCOs in 0.35um and 90nm CMOS processes are described. Measurement results for the 915MHz VCO designed in 0.35um CMOS technology are also presented, obtaining a current consumption of 3mA with a phase noise (L) of -107dBc/Hz @1MHz. The 2.4GHz VCO designed in a 90nm radiofrequency technology shows a current consumption of 400uA with a L of -111.4dBc/Hz @600kHz. Copyright 2009 ACM.
A BIST solution for the functional characterization of RF systems based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE Asian Test Symposium ATS 2009
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This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally practical simulation examples show the feasibility of the approach.
A 2.4 GHz LNA in a 90-nm CMOS technology designed with ACM model
R. Fiorelli, F. Silveira, E. Peralías, D. Vazquez, A. Rueda and J.L Huertas
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2008
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As part of a Low-IF ZigBee receiver, a 2.4GHz differential common source low noise amplifier, implemented in a 90nm mixed/RF 7M CMOS process and designed in moderate inversion, is presented in this work. Design methodology and simulation results from Spectre-RF simulator are presented. With 2.5V supply voltage, the LNA achieves a noise figure of 2.5dB, an IIP3 of 1dB and gain higher than 10dB, with a current consumption of 12mA. The LNA area without pads is 720m x 710m. Copyright 2008 ACM.
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Capítulos de libros
Design of an energy efficient ZigBee transceiver
A. Ginés, R. Fiorelli, A. Villegas, R. Doldán, M. Barragán, D. Vázquez, A. Rueda and E. Peralías
Book Chapter · Mixed-Signal Circuits, pp 171-203, 2018
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This chapter tries to summarize our experience in the development of the analog front-end part of 2.4 GHz ZigBee transceivers with the main objective of optimizing power consumption during normal operation in both reception and transmission modes. Other interesting design aspects, such as optimizing the transceiver protocol, the design of the digital subsystems, or managing the sleep modes, have not been included due to space limitation. To gather together the presented design ideas, the chapter concludes in Section 7.5 with an example of a complementary metal-oxide semiconductor (CMOS) integrated transceiver analog front-end. The competitive experimental performances for this integration endorse the employed design flow, procedures, and analysis.
An all-inversion-region gm/ID based design methodology for radiofrequency blocks in CMOS nanometer technologies
R. Fiorelli, E. Peralías and F. Silveira
Book Chapter · Wireless Radio-Frequency Standards and System Design: Advanced Techniques, pp 15-39, 2012
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This chapter presents a design optimization methodology for analog radiofrequency (RF) blocks based on the gm/ID technique and on the exploration of all-inversion regions (from weak inversion or sub-threshold to strong inversion or above threshold) of the MOS transistor in nanometer technologies. The use of semi-empirical models of MOS transistors and passive components, as inductors or capacitors, assures accurate designs, reducing time and efforts for transferring the initial block specifications to a compliant design. This methodology permits the generation of graphical maps to visualize the evolution of the circuit characteristics when sweeping both the inversion zone and the bias current, allowing reaching very good compromises between performance aspects of the circuit (e.g. noise and power consumption) for a set of initial specifications. In order to demonstrate the effectiveness of this methodology, it is applied in the design of two basic blocks of RF transceivers: low noise amplifiers (LNAs) and voltage controlled oscillators (VCOs), implemented in two different nanometer technologies and specified to be part of a 2.4 GHz transceiver. A possible design flow of each block is provided; resulting designs are implemented and verified both with simulations and measurements.
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