Encontrados resultados para:
Autor: Iluminada Baturone Castillo
Año: Desde 2002
Artículos de revistas
Evaluation of a Vein Biometric Recognition System on an Ordinary Smartphone
P. López-González, I. Baturone, M. Hinojosa and R. Arjona
Journal Paper · Applied Sciences, vol. 12, no. 7, article 3522, 2022
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Nowadays, biometrics based on vein patterns as a trait is a promising technique. Vein patterns satisfy universality, distinctiveness, permanence, performance, and protection against circumvention. However, collectability and acceptability are not completely satisfied. These two properties are directly related to acquisition methods. The acquisition of vein images is usually based on the absorption of near-infrared (NIR) light by the hemoglobin inside the veins, which is higher than in the surrounding tissues. Typically, specific devices are designed to improve the quality of the vein images. However, such devices increase collectability costs and reduce acceptability. This paper focuses on using commercial smartphones with ordinary cameras as potential devices to improve collectability and acceptability. In particular, we use smartphone applications (apps), mainly employed for medical purposes, to acquire images with the smartphone camera and improve the contrast of superficial veins, as if using infrared LEDs. A recognition system has been developed that employs the free IRVeinViewer App to acquire images from wrists and dorsal hands and a feature extraction algorithm based on SIFT (scale-invariant feature transform) with adequate pre- and post-processing stages. The recognition performance has been evaluated with a database composed of 1000 vein images associated to five samples from 20 wrists and 20 dorsal hands, acquired at different times of day, from people of different ages and genders, under five different environmental conditions: day outdoor, indoor with natural light, indoor with natural light and dark homogeneous background, indoor with artificial light, and darkness. The variability of the images acquired in different sessions and under different ambient conditions has a large influence on the recognition rates, such that our results are similar to other systems from the literature that employ specific smartphones and additional light sources. Since reported quality assessment algorithms do not help to reject poorly acquired images, we have evaluated a solution at enrollment and matching that acquires several images subsequently, computes their similarity, and accepts only the samples whose similarity is greater than a threshold. This improves the recognition, and it is practical since our implemented system in Android works in real-time and the usability of the acquisition app is high.
Secure Combination of IoT and Blockchain by Physically Binding IoT Devices to Smart Non-Fungible Tokens using PUFs
J. Arcenegui, R. Arjona, R. Román and I. Baturone
Journal Paper · Sensors, vol. 21, no. 9, article 3119, 2021
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Non-fungible tokens (NFTs) are widely used in blockchain to represent unique and non-interchangeable assets. Current NFTs allow representing assets by a unique identifier, as a possession of an owner. The novelty introduced in this paper is the proposal of smart NFTs to represent IoT devices, which are physical smart assets. Hence, they are also identified as the utility of a user, they have a blockchain account (BCA) address to participate actively in the blockchain transactions, they can establish secure communication channels with owners and users, and they operate dynamically with several modes associated with their token states. A smart NFT is physically bound to its IoT device thanks to the use of a physical unclonable function (PUF) that allows recovering its private key and, then, its BCA address. The link between tokens and devices is difficult to break and can be traced during their lifetime, because devices execute a secure boot and carry out mutual authentication processes with new owners and users that could add new software. Hence, devices prove their trusted hardware and software. A whole demonstration of the proposal developed with ESP32-based IoT devices and Ethereum blockchain is presented, using the SRAM of the ESP32 microcontroller as the PUF.
Behavioral and Physical Unclonable Functions (BPUFs): SRAM Example
M.A. Prada-Delgado and I. Baturone
Journal Paper · IEEE Access, vol. 9, pp 23751-23763, 2021
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Physical Unclonable Functions (PUFs) have gained a great interest for their capability to identify devices uniquely and to be a lightweight primitive in cryptographic protocols. However, several reported attacks have shown that virtual copies (mathematical clones) as well as physical clones of PUFs are possible, so that they cannot be considered as tamper-resistant or tamper-evident, as claimed. The solution presented in this article is to extend the PUFs reported until now, which are only physical, to make them Behavioral and Physical Unclonable Functions (BPUFs). Given a challenge, BPUFs provide not only a physical but also a behavioral distinctive response caused by manufacturing process variations. Hence, BPUFs are more difficult to attack than PUFs since physical and behavioral responses associated to challenges have to be predicted or cloned. Behavioral responses that are obtained from several measurements of the physical responses taken at several sample times are proposed. In this way, the behavioral responses can detect if the physical responses are manipulated. The analysis done for current PUFs is extended to allow for more versatility in the responses that can be considered in BPUFs. Particularly, Jaccard instead of Hamming distances are proposed to evaluate the similarity of behavioral responses. As example to validate the proposed solution, BPUFs based on Static Random-Access Memories (SRAM BPUFs), with one physical and one behavioral responses to given challenges, were analyzed experimentally using integrated circuits fabricated in a 90-nm CMOS technology. If an attacker succeeds in cloning the physical responses as reported, but does not attack the way to obtain the behavioral responses, the attacker fails on SRAM BPUFs. The highest probability to succeed in cloning the behavioral responses with a brute-force attack was estimated from experimental results as $1.5 \cdot 10^{-34}$ , considering the influence of changes in the operating conditions (power supply voltage, temperature, and aging).
PUF-derived IoT identities in a zero-knowledge protocol for blockchain
M.A. Prada-Delgado, I. Baturone, G. Dittmann, J. Jelitto and A. Kind
Journal Paper · Internet of Things, vol. 9, article 100057, 2020
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As the internet of things moves into increasingly sensitive domains, connected devices need to be secured against data manipulation and counterfeiting. Where the underlying business processes involve multiple independent parties, a blockchain platform can provide a common source of truth. If changes to the common state depend on IoT devices, the authenticity and integrity of the IoT input must be ensured. Employing a blockchain platform for authenticating devices makes the process independent of the device manufacturer.
This paper shows how cryptographic keys derived from a device´s physical fingerprint can be employed in a zero-knowledge protocol to authenticate a device. As the keys are regenerated at boot time rather than stored, the approach does not need an expensive secure element. An efficient implementation enables even lightweight devices to prove their identity and sign messages. Experimental results demonstrate the robustness of the approach.
Secure Management of IoT Devices based on Blockchain Non-fungible Tokens and Physical Unclonable Functions
J. Arcenegui, R. Arjona and I. Baturone
Journal Paper · Lecture Notes in Computer Science, ACNS 2020: Applied Cryptography and Network Security Workshops, vol. 12418, pp 24-40, 2020
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One of the most extended applications of blockchain technologies for the IoT ecosystem is the traceability of the data and operations generated and performed, respectively, by IoT devices. In this work, we propose a solution for secure management of IoT devices that participate in the blockchain with their own blockchain accounts (BCAs) so that the IoT devices themselves can sign transactions. Any blockchain participant (including IoT devices) can obtain and verify information not only about the actions or data they are taking but also about their manufacturers, managers (owners and approved), and users. Non Fungible Tokens (NFTs) based on the ERC-721 standard are proposed to manage IoT devices as unique and indivisible. The BCA of an IoT device, which is defined as an NFT attribute, is associated with the physical device since the secret seed from which the BCA is generated is not stored anywhere but a Physical Unclonable Function (PUF) inside the hardware of the device reconstructs it. The proposed solution is demonstrated and evaluated with a low-cost IoT device based on a Pycom Wipy 3.0 board, which uses the internal SRAM of the microcontroller ESP-32 as PUF. The operations it performs to reconstruct its BCA in Ethereum and to carry out transactions take a few tens of milliseconds. The smart contract programmed in Solidity and simulated in Remix requires low gas consumption.
A Post-Quantum Biometric Template Protection Scheme based on Learning Parity with Noise (LPN) Commitments
R. Arjona and I. Baturone
Journal Paper · IEEE Access, vol. 8, pp 182355-182365, 2020
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Biometric recognition has the potential to authenticate individuals by an intrinsic link between the individual and their physical, physiological and/or behavioral characteristics. This leads a higher security level than the authentication solely based on knowledge or possession. One of the reasons why biometrics is not completely accepted is the lack of trust in the storage of biometric templates in external servers. Biometric data are sensitive data which should be protected as is contemplated in the data protection regulation of many countries. In this work, we propose the use of biometric Learning Parity With Noise (LPN) commitments as template protection scheme. To the best of our knowledge, this is the first proposal for biometric template protection based on the LPN problem (that is, the difficulty of decoding random linear codes), which offers post-quantum security. Biometric features are compared in the protected domain. Irreversibility, revocability, and unlinkability properties are satisfied as well as resistance to False Acceptance Rate (FAR), cross-matching, Stolen Token, and similarity-based attacks. A recognition accuracy with a 0% FAR is achieved, because user-specific secret keys are employed, and the False Rejection Ratio (FRR) can be adjusted depending on a threshold to preserve the accuracy of the unprotected scheme in the Stolen Token scenario. A good performance in terms of execution time, template storage and operation complexity is obtained for security levels at least of 80 bits. The proposed scheme is employed in a dual-factor authentication protocol from the literature to illustrate how it provides security using authentication and database (cloud) servers that can be malicious. The proposed LPN-based protected scheme can be applied to any biometric trait represented by binary features and any matching score based on Hamming or Jaccard distances. In particular, experimental results are included of a practical finger vein-based recognition .
High-Speed and Low-Cost Implementation of Explicit Model Predictive Controllers
A. Gersnoviez, M. Brox and I. Baturone
Journal Paper · IEEE Transactions on Control Systems Technology, vol. 27, no. 2, pp 647-662, 2019
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This paper presents a new form of piecewise-affine (PWA) solution, referred to as PWA hierarchical (PWAH), to approximate the explicit model predictive control (MPC) law, achieving a very rapid control response with the use of very few computational and memory resources. This is possible because PWAH controllers consist of single-input single-output PWA modules connected in cascade so that the parameters needed to define them increase linearly instead of exponentially with the input dimension of the control problem. PWAH controllers are not universal approximators but several explicit MPC controllers can be efficiently approximated by them. A methodology to design PWAH controllers is presented and validated with application examples already solved by MPC approaches. The designed PWAH controllers implemented in field-programmable gate arrays provide the highest control speed using the fewest resources compared with the other digital implementations reported in the literature.
Trusted Cameras on Mobile Devices based on SRAM Physically Unclonable Functions
R. Arjona, M.A. Prada-Delgado, J. Arcenegui and I. Baturone
Journal Paper · Sensors, vol. 18, no. 10, art, 3352, 2018
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Nowadays, there is an increasing number of cameras placed on mobile devices connected to the Internet. Since these cameras acquire and process sensitive and vulnerable data in applications such as surveillance or monitoring, security is essential to avoid cyberattacks. However, cameras on mobile devices have constraints in size, computation and power consumption, so that lightweight security techniques should be considered. Camera identification techniques guarantee the origin of the data. Among the camera identification techniques, Physically Unclonable Functions (PUFs) allow generating unique, distinctive and unpredictable identifiers from the hardware of a device. PUFs are also very suitable to obfuscate secret keys (by binding them to the hardware of the device) and generate random sequences (employed as nonces). In this work, we propose a trusted camera based on PUFs and standard cryptographic algorithms. In addition, a protocol is proposed to protect the communication with the trusted camera, which satisfies authentication, confidentiality, integrity and freshness in the data communication. This is particularly interesting to carry out camera control actions and firmware updates. PUFs from Static Random Access Memories (SRAMs) are selected because cameras typically include SRAMs in its hardware. Therefore, additional hardware is not required and security techniques can be implemented at low cost. Experimental results are shown to prove how the proposed solution can be implemented with the SRAM of commercial Bluetooth Low Energy (BLE) chips included in the communication module of the camera. A proof of concept shows that the proposed solution can be implemented in low-cost cameras.
A PUF-and biometric-based lightweight hardware solution to increase security at sensor nodes
R. Arjona, M.A. Prada-Delgado, J. Arcenegui and I. Baturone
Journal Paper · Sensors, vol. 18, no. 8, article 2429, 2018
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Security is essential in sensor nodes which acquire and transmit sensitive data. However, the constraints of processing, memory and power consumption are very high in these nodes. Cryptographic algorithms based on symmetric key are very suitable for them. The drawback is that secure storage of secret keys is required. In this work, a low-cost solution is presented to obfuscate secret keys with Physically Unclonable Functions (PUFs), which exploit the hardware identity of the node. In addition, a lightweight fingerprint recognition solution is proposed, which can be implemented in low-cost sensor nodes. Since biometric data of individuals are sensitive, they are also obfuscated with PUFs. Both solutions allow authenticating the origin of the sensed data with a proposed dual-factor authentication protocol. One factor is the unique physical identity of the trusted sensor node that measures them. The other factor is the physical presence of the legitimate individual in charge of authorizing their transmission. Experimental results are included to prove how the proposed PUF-based solution can be implemented with the SRAMs of commercial Bluetooth Low Energy (BLE) chips which belong to the communication module of the sensor node. Implementation results show how the proposed fingerprint recognition based on the novel texture-based feature named QFingerMap16 (QFM) can be implemented fully inside a low-cost sensor node. Robustness, security and privacy issues at the proposed sensor nodes are discussed and analyzed with experimental results from PUFs and fingerprints taken from public and standard databases.
A comparative analysis of VLSI trusted virtual sensors
M.C. Martínez-Rodríguez, P. Brox and I. Baturone
Journal Paper · Microprocessors and Microsystems, vol. 61, pp 108-116, 2018
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This paper analyzes three cryptographic modules suitable for digital designs of trusted virtual sensors into integrated circuits, using 90-nm CMOS technology. One of them, based on the keyed-hash message authentication code (HMAC) standard employing a PHOTON-80/20/16 lightweight hash function, ensures integrity and authentication of the virtual measurement. The other two, based on CAESAR (the Competition for Authenticated Encryption: Security, Applicability, and Robustness) third-round candidates AEGIS-128 and ASCON-128, ensure also confidentiality. The cryptographic key required is not stored in the sensor but recovered in a configuration operation mode from non-sensitive data stored in the non-volatile memory of the sensor and from the start-up values of the sensor SRAM acting as a Physical Unclonable Function (PUF), thus ensuring that the sensor is not counterfeit. The start-up values of the SRAM are also employed in the configuration operation mode to generate the seed of the nonces that make sensor outputs different and, hence, resistant to replay attacks. The configuration operation mode is slower if using CAESAR candidates because the cryptographic key and nonce have 128 bits instead of the 60 bits of the key and 32 bits of the nonce in HMAC. Configuration takes 416.8 μs working at 50 MHz using HMAC and 426.2 μs using CAESAR candidates. In the other side, the trusted sensing mode is much faster with CAESAR candidates with similar power consumption. Trusted sensing takes 212.62 μs at 50 MHz using HMAC, 0.72 μs using ASCON, and 0.42 μs using AEGIS. AEGIS allows the fastest trusted measurements at the cost of more silicon area, 4.4 times more area than HMAC and 5.4 times more than ASCON. ASCON allows fast measurements with the smallest area occupation. The module implementing ASCON occupies 0.026 mm2 in a 90-nm CMOS technology.
VLSI Design of Trusted Virtual Sensors
M.C. Martínez-Rodríguez, M.A. Prada-Delgado, P. Brox and I. Baturone
Journal Paper · Sensors, vol. 18, no. 2, article 347, 2018
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This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μs. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).
Using Physical Unclonable Functions for Internet-of-Thing Security Cameras
R. Arjona, M.A. Prada-Delgado, J. Arcenegui and I. Baturone
Journal Paper · Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering (LNICST), vol. 242, pp 144-153, 2018
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This paper proposes a low-cost solution to develop IoT security cameras. Integrity and confidentiality of the image data is achieved by using the cryptographic modules that implement symmetric key-based techniques which are usually available in the hardware of the IoT cameras. The novelty of this proposal is that the secret key required is not stored but reconstructed from public data and from the start-up values of a SRAM in the camera hardware acting as a PUF (Physical Unclonable Function), so that the physical authenticity of the camera is also ensured. The variability of the start-up values of the SRAM is also exploited to change the IV (initialization vector) in the encryption algorithm, thus increasing security. All the steps to be carried out by the IoT camera at enrollment and normal operation can be included in a simple firmware to be executed by the camera. In addition, this firmware can be trustworthy updated. There is no need to include specific hardware (such as TPMs) but only an SRAM is needed which could be powered down and up by firmware.
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions
P. Brox, M.C. Martínez-Rodríguez, E. Tena-Sánchez, I. Baturone and A.J. Acosta
Journal Paper · International Journal of Circuit Theory and Applications, vol. 44, no. 1, pp. 4-20, 2015
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This paper presents a fully digital architecture and its application specific integrated circuit implementation for computing multi-input multi-output (MIMO) piecewise-affine (PWA) functions. The work considers both PWA functions defined over regular hyperrectangular and simplicial partitions of the input domains and also lattice PWA representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with application specific integrated circuit (ASIC) integrated in a 90-nm complementary metal-oxide semiconductor standard technology are provided. The proposed architecture is compared with other digital architectures in the state of the art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high-performance and minimum unitary cost are required.
A Fingerprint Retrieval Technique Using Fuzzy Logic-Based Rules
R. Arjona and I. Baturone
Journal Paper · Lecture Notes in Computer Science (LNCS), Subserie Lecture Notes in Artificial Intelligence (LNAI), vol. 9119, pp 149-159, 2015
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This paper proposes a global fingerprint feature named QFingerMap that provides fuzzy information about a fingerprint image. A fuzzy rule that combines information from several QFingerMaps is employed to register an individual in a database. Error and penetration rates of a fuzzy retrieval system based on those rules are similar to other systems reported in the literature that are also based on global features. However, the proposed system can be implemented in hardware platforms of very much lower computational resources, offering even lower processing time.
Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs
I. Baturone, M.A. Prada-Delgado and S. Eiroa
Journal Paper · IEEE Transactions on Information Forensics and Security, vol. 10, no. 12, pp 2653-2668, 2015
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This paper presents a method to simultaneously improve the quality of the identifiers, secret keys, and random numbers that can be generated from the start-up values of standard static random access memories (SRAMs). The method is based on classifying memory cells after evaluating their start-up values at multiple measurements in a registration phase. The registration can be done without unplugging the device from its application context, and with no need for a complex laboratory setup. The method has been validated experimentally with standard low-power SRAM modules in two different application specific integrated circuits (ASICs) fabricated with the 90-nm TSMC technology. The results show that with a simple registration the length of the identifiers can be reduced by 45%, the worst case bit error probability (which defines the complexity of the error correcting code needed to recover a secret key) can be reduced by 64%, and the worst case minimum entropy value is improved, thus reducing the number of bits that have to be processed to obtain full entropy by 81%. The method can be applied to standard digital designs by controlling the external power supply to the SRAM using software or by incorporating simple circuitry in the design. In the latter case, a module for implementing the method in an ASIC designed in the 90-nm TSMC technology occupies an active area of 42,025 μm2.
Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach
M.C. Martínez-Rodríguez, P. Brox, P. and I. Baturone
Journal Paper · IEEE Transactions on Control Systems Technology, vol. 23, no. 3, pp 842-854, 2015
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This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture.
Edge-adaptive spatial video de-interlacing algorithms based on fuzzy logic
P. Brox, I. Baturone, S. Sánchez-Solano and J. Gutiérrez-Ríos
Journal Paper · IEEE Transactions on Consumer Electronics, vol. 60, no. 3, pp. 375-383, 2014
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Since the human visual system is especially sensitive to image edges, edge-dependent spatial interpolators have been proposed in literature as a means of successfully restoring edges while avoiding the staircase effect of linear spatial algorithms. This paper addresses the application of video de-interlacing, which constitutes an indispensable stage in video format conversion. Classic edge-adaptive de-interlacing algorithms introduce annoying artifacts when the edge directions are evaluated incorrectly. This paper presents two ways of exploiting fuzzy reasoning to reinforce edges without an excessive increase in computational complexity. The performance of the proposed algorithms is analyzed by deinterlacing a wide set of test sequences. The study compares the two proposals both with each other and with other edge-adaptive de-interlacing methods reported in the recent literature.
Neuro-fuzzy techniques to optimize an FPGA embedded controller for robot navigation
I. Baturone, A. Gersnoviez and Á. Barriga
Journal Paper · Applied Soft Computing, vol. 21, pp 95-106, 2014
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This paper describes how low-cost embedded controllers for robot navigation can be obtained by using a small number of if-then rules (exploiting the connection in cascade of rule bases) that apply Takagi-Sugeno fuzzy inference method and employ fuzzy sets represented by normalized triangular functions. The rules comprise heuristic and fuzzy knowledge together with numerical data obtained from a geometric analysis of the control problem that considers the kinematic and dynamic constraints of the robot. Numerical data allow tuning the fuzzy symbols used in the rules to optimize the controller performance. From the implementation point of view, very few computational and memory resources are required: standard logical, addition, and multiplication operations and a few data that can be represented by integer values. This is illustrated with the design of a controller for the safe navigation of an autonomous car-like robot among possible obstacles toward a goal configuration. Implementation results of an FPGA embedded system based on a general-purpose soft processor confirm that percentage reduction in clock cycles is drastic thanks to applying the proposed neuro-fuzzy techniques. Simulation and experimental results obtained with the robot confirm the efficiency of the controller designed. Design methodology has been supported by the CAD tools of the environment Xfuzzy 3 and by the Embedded System Tools from Xilinx.
Fuzzy logic-based embedded system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · Applied Soft Computing, vol. 14, part C, pp 338-346, 2014
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Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time.
A hardware solution for real-time intelligent fingerprint acquisition
M.R. Arjona-López and I. Baturone
Journal Paper · Journal of Real-Time Image Processing, vol. 9, no. 1, pp 95-109, 2014
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The first step in any fingerprint recognition system is the fingerprint acquisition. A well-acquired fingerprint image results in high-resolution accuracy and low computational effort of processing. Hence, it is very useful for the recognition system to evaluate recognition confidence level to request new fingerprint samples if the confidence level is low, and to facilitate recognition process if the confidence level is high. This paper presents a hardware solution to ensure a successful and friendly acquisition of the fingerprint image, which can be incorporated at low cost into an embedded fingerprint recognition system due to its small size and high speed. The solution implements a novel technique based on directional image processing that allows not only the estimation of fingerprint image quality, but also the extraction of useful information (in particular, singular points). The digital architecture of the module is detailed and their features in terms of resource consumption and processing speed are illustrated with implementation results into FPGAs from Xilinx. Performance of the solution has been verified with fingerprints from several standard databases that have been acquired with sensors of different sizes and technologies (optical, capacitive, and thermal sweeping).
A programmable and configurable ASIC to generate piecewise-affine functions defined over general partitions
P. Brox, R. Castro-Ramirez, M.C. Martinez-Rodriguez, E. Tena, C.J. Jimenez, I. Baturone and A.J. Acosta
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 12, pp 3182-3194, 2013
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This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated Circuit (ASIC) to generate Piecewise-Affine (PWA) functions. A Generic PWA form (PWAG) has been selected for integration, because of its suitability to implement any PWA function without resorting to approximation. The design of the ASIC in a 90 nm TSMC technology, its integration, test and characterization through different examples are detailed in the paper. Furthermore, the ASIC verification using an ASIC-in-the-loop methodology for embedded control applications is presented. To assess the characteristics of this verification, the double-integrator, a usual control application example has been considered. Experimental results validate the proposed architecture and the ASIC implementation.
Model-Based Design Methodology for Rapid Development of Fuzzy Controllers on FPGAs
S. Sánchez-Solano, M. Brox, E. del Toro, P. Brox and I. Baturone
Journal Paper · IEEE Transactions on Industrial Informatics, vol. 9, no. 3, pp 1361-1370, 2013
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The complexity reached by current applications of industrial control systems has motivated the development of new computational paradigms, as well as the employment of hybrid implementation techniques that combine hardware and software components to fulfill system requirements. On the other hand, continuous improvements in field-programmable devices today make possible the implementation of complex control systems on reconfigurable hardware, although they are limited by the lack of specific design tools and methodologies to facilitate the development of new products. This paper describes a model-based design approach for the synthesis of embedded fuzzy controllers on field-programmable gate arrays (FPGAs). Its main contributions are the proposal of a novel implementation technique, which allows accelerating the exploration of the design space of fuzzy inference modules, and the use of a design flow that eases their integration into complex control systems and the joint development of hardware and software components. This design flow is supported by specific tools for fuzzy systems development and standard FPGA synthesis and implementation tools, which use the modeling and simulation facilities provided by the Matlab environment. The development of a complex control system for parking an autonomous vehicle demonstrates the capabilities of the proposed procedure to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy controllers for industrial applications.
Fuzzy models for fingerprint description
R. Arjona, A. Gersnoviez and I. Baturone
Journal Paper · Lecture Notes in Computer Science (LNCS), Subserie Lecture Notes in Artificial Intelligence (LNAI), vol. 6857, pp 228-235, 2011
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Fuzzy models, traditionally used in the control field to model controllers or plants behavior, are used in this work to describe fingerprint images. The textures, in this case the directions of the fingerprint ridges, are described for the whole image by fuzzy if-then rules whose antecedents consider a part of the image and the consequent is the associated dominant texture. This low-level fuzzy model allows extracting higher-level information about the fingerprint, such as the existence of singular points and their fuzzy position within the image. This is exploited in two applications: to provide comprehensive information for users of unattended automatic recognition systems and to extract linguistic patterns to classify fingerprints. © 2011 Springer-Verlag.
Fuzzy motion adaptive algorithm and its hardware implementation for video de-interlacing
J. Gutiérrez-Rios, P. Brox, F. Fernández-Hernández, I. Baturone and S. Sánchez-Solano
Journal Paper · Applied Soft Computing, vol. 11, no. 4, pp 3311-3320, 2011
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Interlacing techniques were introduced in the early analog TV transmission systems as an efficient mechanism capable of halving the video bandwidth. Currently, interlacing is also used by some modern digital TV transmission systems, however, there is a problem at the receiver side since the majority of modern display devices require a progressive scanning. De-interlacing algorithms convert an interlaced video signal into a progressive one by performing interpolation. To achieve good de-interlacing results, dynamical and local image features should be considered. The gradual adaptation of the de-interlacing technique as a function of the level of motion detected in each pixel is a powerful method that can be carried out by means of fuzzy inference. The starting point of our study is an algorithm that uses a fuzzy inference system to evaluate motion locally (FMA algorithm). Our approach is based on convolution techniques to process a fuzzy rulebase for motion-adaptive de-interlacing. Different strategies based on bi-dimensional convolution techniques are proposed. In particular, the algorithm called 'single convolution algorithm' introduces significant advantages: a more accurate measurement of the level of motion using a matrix of weights, and a unique fuzzification process after the global estimation, which reduces the computational cost. Different architectures for the hardware implementation of this algorithm are described in VHDL language. The physical realization is carried out on a RC100 Celoxica FPGA development board. (C) 2010 Elsevier B.V. All rights reserved.
Soft computing techniques for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · IEEE Journal of Selected Topics in Signal Processing, vol. 5, no. 2, pp 285-296, 2011
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This paper presents the application of soft computing techniques to video processing. Especially, the research work has been focused on the de-interlacing task. It is necessary whenever the transmission standard uses an interlaced format but the receiver requires a progressive scanning, as happens in consumer displays such as LCDs and plasma. A simple hierarchical solution that combines three simple fuzzy logic-based constituents (interpolators) is presented in this paper. Each interpolator is specialized in one of three key image features for de-interlacing: motion, edges, and possible repetition of picture areas. The resulting algorithm offers better results than others with less or similar computational cost. A very interesting result is that our algorithm is competitive with motion-compensated algorithms.
Fuzzy motion-adaptive interpolation with picture repetition detection for deinterlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 58, no. 9, pp 2952-2958, 2009
resumen
doi
A novel fuzzy motion-adaptive deinterlacing algorithm is presented in this paper. It uses fuzzy logic to interpolate between two processing modes, i.e., a spatial (IS) and a temporal (IT) interpolator. Furthermore, the temporal interpolator employs a very simple fuzzy inference system to implement a smart temporal interpolation that locally adapts to the features of the television (TV) material, such as possible picture repetition modes in the fields or in part of the fields (hybrid material). The combination of both systems provides effective results with a low cost in terms of computational resources.
Design of embedded DSP-based fuzzy controllers for autonomous mobile robots
I. Baturone, F.J. Moreno-Velo, V. Blanco and J. Ferruz
Journal Paper · IEEE Transactions on Industrial Electronics, vol. 55, no. 2, pp 928-936, 2008
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Fuzzy controllers are used in many applications because of their rapid design by translating heuristic knowledge, robustness against perturbations, and smoothness in the control action. However, they require parallel processing and special operators (such as fuzzification or defuzzification) which are not available in standard digital signal processors (DSPs), thus complicating their direct implementation. This paper describes an efficient design methodology that allows starting with any kind of fuzzy controller and subsequently transforming it until a system suitable for easy DSP implementation is obtained. Such methodology is greatly aided by the design environment Xfuzzy 3. The parking problem of an autonomous robot is described to illustrate the steps of this methodology. Real experiments with the autonomous robot ROMEO 4R demonstrate efficiency of the designed fuzzy controller embedded into a stand-alone card based on a fixed-point DSP from Texas Instruments.
FPGA implementation of embedded fuzzy controllers for robotic applications
S. Sánchez-Solano, A.J. Cabrera, I. Baturone, F.J. Moreno-Velo and M. Brox
Journal Paper · IEEE Transactions on Industrial Electronics, vol. 54, no. 4, pp 1937-1945, 2007
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Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/soffivare solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle.
Automatic tuning of complex fuzzy systems with xfuzzy
F.J. Moreno-Velo, I. Baturone, A. Barriga and S. Sánchez-Solano
Journal Paper · Fuzzy Sets and Systems, vol. 158, no. 18, pp 2026-2038, 2007
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doi
Tuning a fuzzy system to meet a given set of requirements is usually a difficult task that involves many parameters. Since doing it manually is often cumbersome, several CAD tools have been reported to automate this process. The tool we have developed, xfsl, tries to reduce the limitations of other tools. In this sense, it includes a wide set of supervised learning algorithms and is able to cope with complex fuzzy systems. In particular, xfsl is able to adjust hierarchical fuzzy systems; systems that employ fuzzy functions defined freely by the user, like membership or connective functions, defuzzification methods, or even linguistic hedges; and fuzzy systems with continuous outputs (such as fuzzy controllers) as well as categorical outputs (such as fuzzy classifiers). Several examples included in this paper illustrate all these issues. Another relevant advantage is that xfsl is integrated into the fuzzy system development environment Xfuzzy 3, and, hence, it can be easily employed within the design flow of a fuzzy system. (c) 2007 Elsevier B.V. All rights reserved.
A fuzzy edge-dependent motion adaptive algorithm for de-interlacing
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutierrez-Ríos and F. Fernández-Hernández
Journal Paper · Fuzzy Sets and Systems, vol. 158, no. 3, pp 337-347, 2007
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De-interlacing algorithms are required to convert interlaced video into progressive scan format. They perform an interpolation technique which doubles the vertical sampling density. This paper presents a de-interlacing algorithm which employs fuzzy logic to adapt the interpolation strategy to the presence of motion and edges. Extensive simulations of video sequences prove the advantages of this novel approach. (c) 2006 Elsevier B.V. All rights reserved.
Modelling and implementation of fuzzy systems based on VHDL
A. Barriga, S. Sánchez-Solano, P. Brox, A. Cabrera and I. Baturone
Journal Paper · International Journal of Approximate Reasoning, vol. 41, no. 2, pp 164-178, 2006
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The number of electronic applications using fuzzy logic-based solutions hits increased considerably in the last few years. Concurrently, new CAD tools that explore different implementation technologies for this type of systems have been developed. In this paper we illustrate a fuzzy logic system design strategy based on a high level description. Employing this high level description, the knowledge base is translated to a format in appearance close to the natural language with the particularity that it uses a hardware description language (VHDL) directly synthesizable on an FPGA circuit.]it addition, we analyze different approaches for FPGA implementations of fuzzy systems in order to characterize them in terms of area and speed. Among them, the use of specific processing architectures implemented oil FPGAs presents as main advantages a good "cost-performance" ratio and an acceptably short development time. The different synthesis facilities provided by the Xfuzzy design environment for the implementation of programmable fuzzy systems, which take advantage of the available resources in the current FPGA families, are also analyzed in this paper. (C) 2005 Elsevier Inc. All rights reserved.
Special issue on hardware implementations of soft computing techniques
D. Anguita, I. Baturone and J. Miller
Journal Paper · Applied Soft Computing, vol. 4, no. 3, pp 204-205, 2004
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Abstract not available
Automatic design of fuzzy controllers for car-like autonomous robots
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano and A. Ollero
Journal Paper · IEEE Transactions on Fuzzy Systems, vol. 12, no. 4, pp 447-465, 2004
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This paper describes the design and implementation of a fuzzy control system for a car-like autonomous vehicle. The problem addressed is the diagonal parking in a constrained space, a typical problem in motion control of nonholonomic robots. The architecture proposed for the fuzzy controller is a hierarchical scheme which combines seven modules working in series and in parallel. The rules of each module employ the adequate fuzzy operators for its task (making a decision or generating a smoothly varying control output), and they have been obtained from heuristic knowledge and numerical data (with geometric information) depending on the module requirements (some of them are constrained to provide paths of near-minimal lengths). The computer-aided design tools of the environment Xfuzzy 3.0 (developed by some of the authors) have been employed to automate the different design stages: 1) translation of heuristic knowledge into fuzzy rules; 2) extraction of fuzzy rules from numerical data and their tuning to give paths of near-minimal lengths; 3) offline verification of the control system behavior; and 4) its synthesis to be implemented in a true robot and be verified on line. Real experiments with the autonomous vehicle ROMEO 4R (designed and built at the Escuela SupeRíor de Ingenieros, University of Seville, Seville, Spain) demonstrate the efficiency of the described controller and of the methodology followed in its design.
Arquitectura eficiente para la implementación hardware de sistemas de inferencia difusos
A. Cabrera, S. Sánchez-Solano, C.J. Jimémez, A. Barriga and I. Baturone
Journal Paper · Ingeniería Electrónica, Automática y Comunicaciones, vol. XXIII, no. 1, pp. 59-66, 2003
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Se describen los elementos integrantes de una arquitectura de bajo costo y alto desempeño para la implementación hardware de sistemas de inferencia difusos, la cual se basa en el procesado de reglas activas, la limitación del grado de solapamiento de las funciones de pertenencia de las entradas y la utilización de métodos de defusificación simplificados. También se expone el entorno de desarrollo de sistemas difusos Xfuzzy, con énfasis en la herramienta XFVHDL, la cual permite la generación de código VHDL para los diferentes elementos de la arquitectura descrita.
Congresos
A Facial Authentication System using Post-Quantum-Secure Data Generated on Mobile Devices
P. López-González, R. Arjona, R. Román and I. Baturone
Conference · International Conference on Mobile Computing and Networking MOBICOM 2022
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This paper describes a demonstrator of a post-quantum-secure facial authentication system distributed between a mobile device acting as a client and a remote computer acting as an authentication server. Homomorphic encryption based on Classic McEliece, one of the fourth-round candidates of the NIST post-quantum standardization process, is carried out by the client for protecting the biometric data extracted from the users’ faces at enrollment and verification. The remote computer only stores and compares the received protected data, thus preserving user privacy. An Android App and a Graphical User Interface (GUI) were implemented at the client and the server, respectively, to show the system performance in terms of computation and security.
Post-Quantum Secure Communication with IoT Devices Using Kyber and SRAM Behavioral and Physical Unclonable Functions
R. Román, R. Arjona and I. Baturone
Conference · International Workshop on Attacks and Defenses for Internet-of-Things ADIoT 2022
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For a secure Internet-of-Things (IoT) ecosystem, not only the estab-lishment of secure communication channels but also the authentication of devices is crucial. Authenticated key exchange protocols establish shared cryptographic keys between the parties and, in addition, authenticate their identities. Usually, the identities are based on a pair of private and public keys. Physical Unclonable Functions (PUFs) are widely used recently to bind physically the private key to a device. However, since PUFs are vulnerable to attacks, even non-invasive at-tacks without accessing the device, this paper proposes the use of Behavioral and Physical Unclonable Functions (BPUFs), which allow multimodal authentication and are more difficult to be virtually or physically cloned. In order to resist at-tacks from classic and quantum computers, this paper considers a Kyber key ex-change protocol. Recently, Kyber has been selected by the Post-Quantum Cryp-tography standardization process of the National Institute of Standards and Tech-nology (NIST) for key establishment protocols. In this work, we propose to strengthen a Kyber key exchange protocol with BPUFs extracted from SRAMs included in IoT devices. Experimental results prove the feasibility of the proposal in WiPy boards.
A Quantum-Resistant Face Template Protection Scheme using Kyber and Saber Public Key Encryption Algorithms
R. Roman, R. Arjona, P. Lopez-Gonzalez, I. Baturone, A. Bromme, N. Damer, M. Gomez-Barrero, K. Raja, C. Rathgeb, A.F. Sequeira, M. Todisco and A. Uhl
Conference · Conference of the Biometrics-Special-Interest-Group BIOSIG 2022
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Considered sensitive information by the ISO/IEC 24745, biometric data should be stored and used in a protected way. If not, privacy and security of end-users can be compromised. Also, the advent of quantum computers demands quantum-resistant solutions. This work proposes the use of Kyber and Saber public key encryption (PKE) algorithms together with homomorphic encryption (HE) in a face recognition system. Kyber and Saber, both based on lattice cryptography, were two finalists of the third round of NIST post-quantum cryptography standardization process. After the third round was completed, Kyber was selected as the PKE algorithm to be standardized. Experimental results show that recognition performance of the non-protected face recognition system is preserved with the protection, achieving smaller sizes of protected templates and keys, and shorter execution times than other HE schemes reported in literature that employ lattices. The parameter sets considered achieve security levels of 128, 192 and 256 bits.
Rule Simplification Method based on Covering Indexes for Fuzzy Classifiers
A. Gersnoviez and I. Baturone
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2021
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A large number of rules increases the complexity of fuzzy classifiers and reduces the linguistic interpretability of the classification. A tabular rule simplification method that extends the Quine-McCluskey algorithm of Boolean design to fuzzy logic is analyzed in detail in this paper. The method obtains a few compound rules from many initial atomic rules. The influence of membership functions as well as t-norms and s-norms operands, which can be even null if many atomic rules are used, becomes apparent in the classification regions (decision boundaries) induced by the compound rules. Since the compound rules can be ordered according to the covering indexes that measure the number of atomic rules covered, more or less generic classification rules and rules with particular indexes can be further identified, which could ease subsequent classification or decision-making.
HardBlock: Demonstrator of physically binding an IoT device to a non-fungible token in Ethereum blockchain
J. Arcenegui, R. Arjona and I. Baturone
Conference · Design, Automation and Test in Europe DATE 2021
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Nowadays, blockchain is a growing technology in the Internet of Thing (IoT) ecosystem. In this work, we show a demonstrator of an IoT device bound to a Non-Fungible Token (NFT) based on the ERC-721 standard of Ethereum blockchain. The advantages of our solution is that IoT devices can be controlled securely by events from the blockchain and authenticated users, besides being able to carry out blockchain transactions. The IoT device generates its own Blockchain Account (BCA) using a secret seed firstly generated by a True Random Number Generator (TRNG) and then reconstructed by a Physical Unclonable Function (PUF). A Pycom Wipy 3.0 board with the ESP32 microcontroller is employed as IoT device. The internal SRAM of the microcontroller acts as PUF and TRNG. The SRAM is controlled by a firmware developed in ESP-IDF. A smart contract developed in Solidity using Remix IDE creates the token. Kovan testnet and a Graphical User Interface programmed in Python are employed to show the results.
A Quantum-Resistant and Fast Secure Boot for IoT Devices using Hash-Based Signatures and SRAM PUFs
R. Román and I. Baturone
Conference · EAI International Conference on Safety and Security in Internet of Things SaSeIoT 2021
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Abstract not available
Auto-Calibrated Ring Oscillator TRNG Based on Jitter Accumulation
M.A. Prada-Delgado, C. Martínez-Gómez and I. Baturone
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
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This paper provides a mathematical model that describes how deterministic and Gaussian jitter of an oscillating signal accumulated during a time interval are related to the bits of the binary-coded count value of the oscillations. The model is employed to propose a robust TRNG that has a simple interface (an initialization signal as input and the random bits as output) and that features auto-calibration to certify high entropy of the raw bits provided as well as to work at the highest throughput allowed by the available local Gaussian noise. The mathematical analysis is confirmed with experimental results of ring oscillator (RO) TRNGs described in VHDL and implemented in the programmable logic of Zynq family Xilinx FPGAs, using either another RO or the clock of the FPGA board to control the time interval of oscillations.
Calibration of Ring Oscillator PUF and TRNG
C. Martínez-Gómez and I. Baturone
Conference · European Conference on Circuit Theory and Design ECCTD 2020
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This paper describes a circuit structure named RO-PUF-TRNG based on ring oscillators (ROs), which is able to be calibrated to perform as a physically unclonable function (PUF) and a true random number generator (TRNG) with high uniqueness, entropy, and throughput. The calibration is based on a mathematical model that describes how the PUF and TRNG response bits are related to the intrinsic variations of the fabrication process and bitstream generation (in the case of FPGAs) as well as to the Gaussian noise. The results obtained with the proposed calibration are illustrated with the large dataset of RO frequencies from 90-nm FPGAs provided in [1].
Hardware Security for eXtended Merkle Signature Scheme using SRAM-based PUFs and TRNGs
R. Román, R. Arjona, J. Arcenegui and I. Baturone
Conference · International Conference on Microelectronics ICM 2020
resumen
Due to the expansion of the Internet of Things (IoT), there is an increasing number of interconnected devices around us. Integrity, authentication and non-repudiation of data exchanged between them is becoming a must. This can be achieved by means of digital signatures. In recent years, the eXtended Merkle Signature Scheme (XMSS) has gained popularity in embedded systems because of its simple implementation, post-quantum security, and minimal security assumptions. From a hardware point of view, the security of digital signatures strongly depends on how the private keys are generated and stored. In this work, we propose the use of SRAMs as True Random Generators (TRNGs) and Physically Unclonable Functions (PUFs) to generate and reconstruct XMSS keys in a trusted way. We achieve a low-cost solution that only adds lightweight operations to the signature itself, such as repetition decoding and XORing, and does not require additional hardware (like secure non-volatile memories) since the manufacturing variations of the SRAM inside the IoT device are exploited. As a proof of concept, the solution was implemented in an IoT board based on the ESP32 microcontroller.
Using Simulink HDL Coder to implement a Fingerprint Recognition Algorithm into an FPGA
R. Arjona and I. Baturone
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2020
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This work describes a model-based hardware design flow which uses Simulink HDL Coder and Xilinx tools to implement a fingerprint recognition algorithm into a Virtex-6 FPGA. Students can learn how this automated hardware design flow reduces the time to create a prototype since only the high-level description is required. In addition, the fingerprint recognition application allows illustrating how typical processing blocks employed for image processing are used in the context of biometrics security.
How to Implement a Fingerprint Recognition Algorithm into a Wearable Device
R. Arjona, J. Arcenegui and I. Baturone
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2020
resumen
This work describes how to implement a fingerprint recognition algorithm into an ARM Cortex-M3 microcontroller included in a Texas Instruments LaunchPad CC2650 evaluation kit. The application context is the realization of a wearable device for biometrics security. On the one hand, the students become familiar with wearable devices whose basic component is a low power microcontroller. On the other hand, the students learn about a security application based on fingerprint recognition, which employs typical operations of image processing.
Hierarchical fuzzy controllers for explicit MPC control laws: Adaptive cruise control example
A. Gersnoviez, M. Brox and I. Baturone
Conference · IEEE International Conference on Fuzzy Systems FUZZ 2020
resumen
This paper presents a methodology to approximate explicit Model Predictive Control (MPC) laws by hierarchical fuzzy systems, particularly piecewise-affine hierarchical (PWAH) systems. These hierarchical controllers provide high operation speed with low cost in computational and memory resources because they are formed only by single-input and single-output (SISO) fuzzy modules connected in cascade. The methodology employs the CAD tools of Xfuzzy environment to describe, adjust, verify, and implement the controllers in a Field Programmable Gate Array (FPGA). The methodology is illustrated with the design and FPGA implementation of a hierarchical controller for a car adaptive cruise control (ACC) system. The resulting controller is better in terms of speed and FPGA resource consumption than other solutions reported in the literature.
A Dedicated Hardware Implementation for Biometric Recognition based on Finger Veins
R. Arjona, J. Costas and I. Baturone
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2019
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Nowadays, there is an increasing demand of security devices which include biometric authentication. Biometric recognition based on finger veins is very suitable for lightweight devices because it provides distinctiveness and the acquisition can employ small-size camera and low-cost sensors. Among the extraction techniques of features for finger veins, Wide Line Detector offers a good trade-off between recognition accuracy and computational complexity. A generic VHDL description has been developed for this feature extraction technique and the matching of the binary feature images. Implementation results on a Zynq 7020 FPGA are provided.
Securing minutia cylinder codes for fingerprints through physically unclonable functions: An exploratory study
R. Arjona, M.A. Prada-Delgado, I. Baturone and A. Ross
Conference · International Conference on Biometrics ICB 2018
resumen
A number of personal devices, such as smartphones, have incorporated fingerprint recognition solutions for user authentication purposes. This work proposes a dual-factor fingerprint matching scheme based on P-MCCs (Protected Minutia Cylinder-Codes) generated from fingerprint images and PUFs (Physically Unclonable Functions) generated from device SRAMs (Static Random Access Memories). Combining the fingerprint identifier with the device identifier results in a secure template satisfying the discriminability, irreversibility, revocability, and unlinkability properties, which are strongly desired for data privacy and security. Experiments convey the benefits of the proposed dual-factor authentication mechanism in enhancing the security of personal devices that utilize biometric authentication schemes.
CMOS digital design of a trusted virtual sensor
M.C. Martínez-Rodríguez, M.A. Prada, P. Brox and I. Baturone
Conference · IEEE Nordic Circuits and Systems Conference NORCAS 2017
resumen
This work presents the digital design of a trusted virtual sensor. The virtual sensor implements a piecewise-affine (PWA)-based model to estimate the sensed variable. The measurement is authenticated with the keyed-hash message authentication code (HMAC) standard. To ensure the integrity of the sensor, the static random access memory (SRAM) required by the sensor is also used as physical unclonable function (PUF). Implementation results of the design in a 90-nm CMOS technology show that the security blocks occupy 5.1% of the area occupied by the required PWA blocks and consume 15.4% of the power consumed by the required PWA blocks. The sensor is able to provide trusted outputs in 106.3 microseconds when working at 100 MHz.
Exploiting the variability of semiconductor fabrication process for hardware security
I. Baturone, P. Brox, R. Arjona and M.A. Prada-Delgado
Conference · How to survive in an unreliable world, IEEE CEDA Spain Chapter / NANOVAR Workshop 2017
resumen
Variability of semiconductor fabrication process can be a problem for many electronic designers, but it is a strength for many others who want to increase the security of electronic products. This talk summarizes how to exploit variability to provide, from hardware, identifiers and cryptographic primitives such as secret keys and true random numbers and, hence, how hardware-based security can solve vulnerabilities of software-based security.
Demonstrator of a Fingerprint Recognition Algorithm into a Low-Power Microcontroller
J. Arcenegui, R. Arjona and I. Baturone
Conference · Conference on Design and Architectures for Signal and Image Processing DASIP 2017
resumen
A demonstrator has been developed to illustrate the performance of a lightweight fingerprint recognition algorithm based on the fingerprint feature QFingerMap16, which is extracted from a window of the directional image (containing 16 direction values) centered at the convex core of the fingerprint. The algorithm has been implemented into a low-power ARM Cortex-M3 microcontroller included in a Texas Instruments LaunchPad CC2650 evaluation kit. It has been also implemented in a Raspberry Pi 2 so as to show the results obtained at the successive steps of the recognition process with the aid of a Graphical User Interface (GUI).
Trustworthy firmware update for Internet-of-Thing Devices using physical unclonable functions
M.A. Prada-Delgado, A. Vázquez-Reyes and I. Baturone
Conference · Global Internet of Things Summit GIoTS 2017
resumen
Connected devices that are part of the so-called Internet of Things (IoT) need to update their firmware over their lifetime. The problem is that updates can be used by attackers to inject malicious code. This work presents a lightweight protocol to update each device in a secure way. The cryptographic keys employed are fresh and are not stored but reconstructed by exploiting the Physical Unclonable Functions (PUFs) of the device hardware. The feasibility of the proposal is illustrated with experimental results of IoT devices that use the SRAM PUFs in their Bluetooth Low Energy (BLE) system on chips.
A dual-factor access control system based on device and user intrinsic identifiers
R. Arjona and I. Baturone
Conference · IEEE Industrial Electronics Conference IECON 2016
resumen
This paper proposes an access control system based on the simultaneous authentication of what the user has and who the user is. At enrollment phase, the wearable access device (a smart card, key fob, etc.) stores a template that results from the fusion of the intrinsic device identifier and the user biometric identifier. At verification phase, both the device and user identifiers are extracted and matched with the stored template. The device identifier is generated from the start-up values of the SRAM in the device hardware, which are exploited as a Physically Unclonable Function (PUF). Hence, if the device hardware is cloned, the authentic identifier is not generated. The user identifier is obtained from level-1 fingerprint features (directional image and singular points), which are extracted from the fingerprint images captured by the sensor in the access device. Hence, only genuine users with genuine devices are authorized to access and no sensitive information is stored or travels outside the access device. The proposal has been validated by using 560 fingerprints acquired in live by an optical sensor and 560 SRAM-based identifiers.
Physical unclonable keys for smart lock systems using Bluetooth Low Energy
M.A. Prada-Delgado, A. Vázquez-Reyes and I. Baturone
Conference · IEEE Industrial Electronics Conference IECON 2016
resumen
Nowadays, several smart lock systems use Bluetooth Low Energy (BLE) to stablish a wireless communication between the physical key (key fob, card, smartphone, etc.) and the lock. Security is based on creating and storing secret digital keys to establish a cryptographically secure communication. The problem is that several attacks can break such security, particularly the copy of the physical key. In order to increase the difficulty of the attacks, the physical keys described in this paper do not store the secret cryptographic keys but reconstruct them when they are needed and remove them when they are not used. Only the trusted physical keys are able to reconstruct the secrets with the public data stored in them. This is possible by using the start-up values of the SRAM in the BLE chip of the physical key, which acts as a physical unclonable function (PUF), so that if the physical key is copied, the lock cannot be opened. The idea has been proven with the development of a smart lock system with key fobs based on the CC2541 BLE system on chip from Texas Instruments. Experimental results are included to illustrate the performance.
Wearable Biometric Authentication Based on Human and Device Identities
R. Arjona, M.A. Prada-Delgado, A. Vázquez-Reyes and I. Baturone
Conference · BIOMETRICS 2016
resumen
This poster describes the design of a wearable access device that simultaneously authenticates who the user is and what the user has, thus being suitable for dual-factor access control systems. At enrolment phase, the wearable device stores a template that results from the fusion of the human biometric identifier and the intrinsic device identifier. Fusion is done in an obfuscated way so that the template does not contain sensitive information. Hence, no information can be extracted from the device even if it is stolen by attackers. At verification phase, both the human and device identifiers are extracted and matched with the stored template at real time.
The human identifier is obtained from level-1 fingerprint features (directional image and singular points), which are extracted from the fingerprint images captured by the sensor in the access device. The device identifier is generated from the start-up values of the Static Random Access Memory (SRAM) in the device hardware, which are exploited as a Physically Unclonable Function (PUF). Hence, if the device hardware is cloned, the authentic identifier is not generated.
The involved processing has low computational cost so as to satisfy the constraints of time, area and power consumption of wearable devices. The proposal has been validated by using 560 fingerprints acquired in live and 560 SRAM-based identifiers obtained from the Bluetooth Low Energy (BLE) chip selected to provide the wireless communication of the wearable device. Using two fingers per user and two PUFs per device, three samples per finger and PUF at enrolment and two samples per finger and PUF at matching, Equal Error Rate (EER) is zero because the genuine and impostor distributions are well separated. Only genuine users with genuine devices are authorized to access and no sensitive information is stored or travels outside the wearable device.
FPGA Implementation of the Two-Dimensional Fuzzy-ELA Algorithm for Image Enlargement
M. Brox, S. Sánchez-Solano, P. Brox, A. Gersnoviez and I. Baturone
Conference · XVIII Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2016
resumen
Resolution improvement of images is today required for many applications, as medical or satellite imaging, where it is very important to distinguish details [1]. The interpolation capability provided by Fuzzy Logic, in addition to its effectivity to incorporate heuristic knowledge into numeric procedures, has motivated its usage in recent algorithms for image enlargement [2]. This paper presents the hardware implementation of the two-dimensional Fuzzy-ELA algorithm proposed in [3]. The 2D Fuzzy-ELA method is a generalization of the basic Fuzzy-ELA algorithm [4], which uses a fuzzy system to adapt the interpolation to the presence of edges in images, achieving better results than many other approaches. The hardware implementation described in this paper includes parameters to allow selecting different scale factors for the image enlargement. In order to simplify the description, Fig.1a illustrates the process when a factor of two is chosen.
SRAM-based Physical Unclonable Keys for BLE Smart Lock Systems
I. Baturone, M.A. Prada-Delgado, A. Vázquez-Reyes, L. Acasandrei, D. Fernández-Barrera and J. Prada-Delgado
Conference · Design, Automation and Test in Europe DATE 2016
resumen
Nowadays, several smart lock systems use Bluetooth Low Energy (BLE) to recognize when a smartphone, conveniently authenticated by a digital key, is near. The keys can be shared and are managed by web apps, so that system security depends on how the software prevents an attacker from discovering the keys. In order to increase security by a two-factor method (‘something you have’ in addition to ‘something you know’), the BLE smart lock system prototype shown in this demonstrator recognizes when a user wearing an authenticated BLE chip (in a key fob, wristband, etc.) is near. The digital keys are not stored but they are regenerated on the fly by only the trusted chip. This is possible by using the start-up values of the SRAM in the BLE chip, which act as a physical unclonable function (PUF), so that the chip cannot be cloned. The SRAM start-up values of the BLE chip are also exploited as true random numbers to derive fresh keys for each transaction with the lock.
Dedicated Hardware IP Module for Fingerprint Recognition
M.C. Martínez-Rodríguez, R. Arjona, P. Brox and I. Baturone
Conference · International Symposium on Consumer Electronics ISCE 2015
resumen
This work presents a dedicated hardware IP module for fingerprints recognition based on a feature, named QFingerMap, which is very suitable for VLSI design. FPGA implementation results of the IP module are given. A demonstrator has been developed to evaluate the IP module behavior in a real scenario.
A VLSI Module To Authenticate Unclonable Things
I. Baturone, M.A. Prada-Delgado and S. Eiroa
Conference · International Symposium on Consumer Electronics ISCE 2015
resumen
This paper presents a VLSI module that implements a lightweight symmetric authentication protocol based on Keyed-Hash Message Authentication Code (HMAC). The cryptographic key and the random numbers needed by the protocol are generated by a SRAM acting as a Physical Unclonable Function (PUF).
Programmable ASICs for Model Predictive Control
M.C. Martínez-Rodríguez, P. Brox, E. Tena, A.J. Acosta and I. Baturone
Conference · IEEE International Conference on Industrial Technology ICIT 2015
resumen
Two configurable and programmable ASICs that implement piecewise-affine (PWA) functions have been designed in TSMC 90-nm technology in response to industry demands for embedded, fast response time, and low power solutions for Model Predictive Control (MPC). An automated model-based design flow can extract the parameters necessary for the configuration and the programming of both ASICs. Two application examples in the automotive field illustrate the design flow and the behavior of the ASICs.
A Fingerprint Biometric Cryptosystem in FPGA
R. Arjona and I. Baturone
Conference · IEEE International Conference on Industrial Technology ICIT 2015
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This paper presents the implementation of a complete fingerprint biometric cryptosystem in a Field Programmable Gate Array (FPGA). This is possible thanks to the use of a novel fingerprint feature, named QFingerMap, which is binary, length-fixed, and ordered. Security of Authentication on FPGA is further improved because information stored is not sensitive but public due to the design of a cryptosystem based on Fuzzy Commitment. Several samples of fingers as well as passwords can be fused at feature level with codewords of an error correcting code to generate non-sensitive data. System performance is illustrated with experimental results corresponding to 560 fingerprints acquired in live by an optical sensor and processed by the system in a Xilinx Virtex 6 FPGA. Depending on the realization, more or less accuracy is obtained, being possible a perfect authentication (zero Equal Error Rate), with the advantages of real-time operation, low power consumption, and a very small device.
An unclonable token for a secure document management system
I. Baturone, M.A. Prada-Delgado, S. Eiroa and J.A. Prieto
Conference · Intel Workshop on Cyberphysical and Mobile Security: Intelligent Things, Vehicles and Factories, 2014
resumen
Abstract not avaliable
Robust Unclonable Identifiers and True Random Numbers from off-the-Shelf SRAMs
M.A. Prada, S. Eiroa and I. Baturone
Conference · Conference on Design and Architectures for Signal and Image Processing DASIP 2014
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A demonstrator has been developed that shows how off-the-shelf SRAMs can be identified by their start-up values and how true random numbers can be extracted from them. It contains an FPGA that communicates with off-the-shelf SRAMs and with a USB 2.0 microcontroller which in turn communicates with a computer to show the results to users.
Robust unclonable identifiers and true random numbers from off-the-shelf SRAMs
M.A. Prada-Delgado, S. Eiroa and I. Baturone
Conference · Conference on Design and Architectures for Signal and Image Processing DASIP 2014
resumen
A demonstrator has been developed that shows how off-the-shelf SRAMs can be identified by their start-up values and how true random numbers can be extracted from them. It contains an FPGA that communicates with off-the-shelf SRAMs and with a USB 2.0 microcontroller which in turn communicates with a computer to show the results to users.
Hardware Implementation of a Biometric Recognition Algorithm based on In-Air Signature
R. Arjona, R. Romero-Moreno and I. Baturone
Conference · Conference on Design and Architectures for Signal and Image Processing DASIP 2014
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Wearable technology requires low-cost, small and lightweight devices, which impose high constraints in terms of resources, real-time responses and power consumption. The selection of a biometric trait suitable for a wearable device should consider small-size sensors to acquire the signals as well as algorithms of low complexity that maintain discrimination capability. The in-air signature satisfies these constraints. This paper presents the design of a wearable device that implements a recognition system based on in-air signature into a FPGA that receives data from a 3-axis accelerometer. The hardware architecture is developed once the specifications of the algorithm to implement are analyzed. Results are shown in terms of resource consumption and processing speed of the implementation into a Spartan-6 FPGA LX9 microboard from Xilinx.
Dedicated Hardware IP Module for Extracting Singular Points from Fingerprints
M.C. Martínez-Rodríguez, R. Arjona, P. Brox and I. Baturone
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2014
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In this paper a new digital dedicated hardware IP module for extracting singular points from fingerprints is presented (in particular convex cores). This module comprises four main blocks that implement an image directional extraction, a smoothing process, singular point detection and finally, a post processing to obtain the exact location of the singular point. A Verilog HDL description has been developed for this solution. The description has been synthesized and implemented in FPGAs from Xilinx.
FPGA Implementation and DPA Resistance Analysis of a Lightweight HMAC Construction based on Photon Hash Family
S. Eiroa and I. Baturone
Conference · International Conference on Field Programmable Logic and Applications FPL 2013
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Lightweight security is currently a challenge in the field of cryptography. Most of applications designed for embedded scenarios often focus on authentication or on providing some form of anonymity and/or privacy. A well-known cryptographic element employed to provide such security is the HMAC construction. However, reported solutions are not suitable for constrained-resource scenarios due to their heavy approaches optimized for high-speed operations. In order to cover this lack, a lightweight implementation of HMAC based on the Photon family of hash functions is given in this work. Security of the construction against differential power attacks (DPA) is analyzed using a SASEBO-II development board. Implementation and performance results for Xilinx Virtex-5 FPGAs of the HMAC structure is provided.
Reducing bit flipping problems in SRAM physical unclonable functions for chip identification
S. Eiroa, J. Castro, M.C. Martínez-Rodríguez, E. Tena, P. Brox and I. Baturone
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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Physical Unclonable functions (PUFs) have appeared as a promising solution to provide security in hardware. SRAM PUFs offer the advantage, over other PUF constructions, of reusing resources (memories) that already exist in many designs. However, their intrinsic noisy nature produces the so called bit flipping effect, which is a problem in circuit identification and secret key generation. The approaches reported to reduce this effect usually resort to the use of pre- and post-processing steps (such as Fuzzy Extractor structures combined with Error Correcting Codes), which increase the complexity of the system. This paper proposes a pre-processing step that reduces bit flipping problems without increasing the hardware complexity. The proposal has been verified experimentally with 90-nm SRAMs included in digital application specific integrated circuits (ASICs).
Model-Based Design for Selecting Fingerprint Recognition Algorithms for Embedded Systems
R. Arjona and I. Baturone
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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Most of contributions for biometric recognition solutions (and specifically for fingerprint recognition) are implemented in software on PC or similar platforms. However, the wide spread of embedded systems means that fingerprint embedded systems will be progressively demanded and, hence, hardware dedicated solutions are needed to satisfy their constraints. CAD tools from Matlab-Simulink ease hardware design for embedded systems because automatize the design process from high-level descriptions to device implementation. Verification of results is set at different abstraction levels (high- level description, hardware code simulation, and device implementation). This paper shows how a design flow based on models facilitates the selection of algorithms for fingerprint embedded systems. In particular, the search of a solution for directional image extraction suitable for its application to singular point extraction is detailed. Implementation results in terms of area occupation and timing are presented for different Xilinx FPGAs.
ASIC-in-the-loop methodology for verification of piecewise affine controllers
M. Martínez-Rodríguez, P. Brox, J. Castro, E. Tena, A. Acosta and I. Baturone
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations.
XFSML: An XML-based modeling language for fuzzy systems
F.J. Moreno-Velo, A. Barriga, S. Sánchez-Solano and I. Baturone
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2012
resumen
This paper presents a new modeling language for fuzzy systems called XFSML. It is an XML-based language and it is proposed as a starting point for the definition of a standard modeling language in the fuzzy community. The main features of the language are its high expressiveness and its independence from specific platforms, tools or programming languages.
Towards Low-Cost Hardware Solutions for Fingerprint Authentication Embedded Systems
R. Arjona and I. Baturone
Conference · Summer School for Advanced Studies on Biometrics for Secure Authentication: New Technologies for Forensics and Security, 2011
resumen
Abstract not avaliable
Design methodology for FPGA implementation of lattice piecewise-affine functions
M.C. Martínez-Rodríguez, I. Baturone and P. Brox
Conference · International Conference on Field-Programmable Technology FPT 2011
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This paper describes a design methodology to implement on FPGAs piecewise-affine (PWA) functions based on representation methods from the lattice theory. An off-line automatic processing starts at the algorithmic formulation of the problem, obtains the parameters required by a parameterized digital architecture, and ends with the bitstream to program an FPGA. The methodology has been proven to implement PWA functions on Xilinx FPGAs. The results are compared with other approaches for FPGA implementations of PWA functions. © 2011 IEEE.
Circuit authentication based on ring-oscillator PUFs
S. Eiroa and I. Baturone
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2011
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The use of Ring Oscillator PUFs to provide circuit authentication is analyzed in this paper. The limitations of the previously reported approach in terms of false rejection (due to high intra-die variations) and false acceptance (due to small inter-die variations) are discussed. These limitations are overcome by a new proposal that makes the authentication more robust against noise, temperature and power supply variations, without increasing considerably hardware complexity. All these issues are illustrated with experimental results obtained with FPGAs from Xilinx. © 2011 IEEE.
A digital circuit for extracting singular points from fingerprint images
R. Arjona and I. Baturone
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2011
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Since singular point extraction plays an important role in many fingerprint recognition systems, a digital circuit to implement such processing is presented herein. A novel algorithm that combines hardware efficiency with precision in the extraction of the points has been developed. The circuit architecture contains three main building blocks to carry out the three main stages of the algorithm: extraction of a partitioned directional image, smoothing, and searching for the patterns associated with singular points. The circuit processes the pixels in a serial way, following a pipeline scheme and executing in parallel several operations. The design flow employed has been supported by CAD tools. It starts with high-level descriptions and ends with the hardware prototyping into a FPGA from Xilinx. © 2011 IEEE.
An analysis of ring oscillator PUF behavior on FPGAs
S. Eiroa and I. Baturone
Conference · International Conference on Field-Programmable Technology FPT 2011
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Many studies have been directed to probe ring oscillator PUF's feasibility in the security field, but most of them suffer from the lack of global approach as they analyze the system isolated, giving an uncompleted theory about their behavior. This paper presents how adjacent hardware elements may affect PUF response, modifying their statistical characteristics and even masking the randomness of manufacturing process. This is a factor that should be taken into account when modeling the behavior of the ring oscillators in the PUF. Experimental results from Xilinx Spartan 3 FPGAs illustrate these issues. © 2011 IEEE.
Circuit implementation of piecewise-affine functions based on lattice representation
M.C. Martínez-Rodríguez, I. Baturone and P. Brox
Conference · European Conference on Circuit Theory and Design ECCTD 2011
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This paper introduces a digital architecture to implement piecewise-affine (PWA) functions based on representation methods from the lattice theory. Given an explicit and continuous PWA function, the parameters required to implement the lattice approach can be obtained by an off-line preprocessing that can be automated. Other advantages of the proposal are that it implements a continuous PWA function with potentially no errors and the minimum number of parameters to store. This has been proven experimentally by implementing the proposal in a Xilinx FPGA and comparing its performance with other implementations, all of them addressing a typical non linear control problem. © 2011 IEEE.
Digital implementation of hierarchical piecewise-affine controllers
I. Baturone, M.C. Martínez-Rodríguez, P. Brox, A. Gersnoviez and S. Sánchez-Solano
Conference · IEEE International Symposium on Industrial Electronics ISIE 2011
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This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the hierarchical solution have fewer inputs and/or coarser partitions, so that they can reduce considerably the hardware resources required and/or the time response of the controller. A design methodology aided by CAD tools is employed to design the parameters of the controller, implement its architecture in an FPGA, and verify the static and dynamic behavior of the digital implementation by applying hardware-in-the-loop testing. © 2011 IEEE.
Aplicación de XFuzzy 3 al procesado de imágenes basado en reglas
I. Baturone, P. Brox and R. Arjona
Conference · XIV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2010
resumen
Los entornos de desarrollo de sistemas fuzzy se han empleado normalmente para diseñar sistemas de control y de toma de decisiones pero apenas para diseñar sistemas de procesado de imágenes, a pesar de que este campo cuenta ya con numerosas soluciones basadas en Lógica Fuzzy. En este artículo se muestra cómo el entorno Xfuzzy 3 desarrollado en el Instituto de Microelectrónica de Sevilla posee la versatilidad necesaria para abordar el diseño de estos sistemas, facilitando su descripción, verificación, ajuste y síntesis.
Tuning of a hierarchical fuzzy system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2010
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The tuning of hierarchical fuzzy systems are not supported by the majority of CAD tools available at the market currently. The XFSL tool integrated into Xfuzzy 3 allows the tuning of complex fuzzy systems, for instance, hierarchical systems with modules in cascade. The authors propose the use of this tool for tuning a complex fuzzy system for video de-interlacing in this paper. The parameters obtained after tuning are proven by de-interlacing a wide battery of sequences. The use of tuning techniques improves the quality of de-interlacing and provides an algorithm simplification that facilitates its hardware implementation.
Using physical unclonable functions for hardware authentication: a survey
S. Eiroa, I. Baturone, A.J. Acosta and J. Dávila
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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Physical unclonable functions (PUFs) are drawing a crescent interest in hardware oriented security due to their special characteristics of simplicity and safety. However, their nature as well as early stage of study makes them constitute currently a diverse and non-standardized set for designers. This work tries to establish one organization of existing PUF structures, giving guidelines for their choice, conditioning, and adaptation depending on the target application. In particular, it is described how using PUFs adequately could enlighten significantly most of the security primitives, making them very suitable for authenticating constrained resource platforms.
Diseño de sistemas difusos para procesado de imágenes con xfuzzy 3
I. Baturone, P. Brox and R. Arjona
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2010
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La presente comunicación describe la utilización de un software de libre
distribución, Xfuzzy 3, para ilustrar la aplicación de sistemas difusos al
procesamiento de imágenes, en concreto, al problema del aumento de resolución.
El proceso de diseño de sistemas difusos quedará cubierto por el uso de las
herramientas CAD de descripción, verificación, identificación, aprendizaje y
simplificación del entorno XFuzzy en su versión 3.3, que facilitan al alumno la
comprensión de todos los pasos del proceso.
Circuital and Architectural Challenges for the Design of PET Medical Imaging Systems using CMOS
A. Rodríguez-Vázquez, R. Carmona-Galán, G. Liñán, R. del Río and B. Pérez-Verdú
Conference · International Workshop on Biomedical Applications of Micro-PET, 2010
resumen
Abstract not available
Aplicación de Xfuzzy3 al procesado de imágenes basado en reglas
I. Baturone, P. Brox and R. Arjona
Conference · XV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2010
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Los entornos de desarrollo de sistemas fuzzy se han empleado normalmente para diseñar sistemas de control y de toma de decisiones pero apenas para diseñar sistemas de procesado de imágenes, a pesar de que este campo cuenta ya con numerosas soluciones basadas en Lógica Fuzzy. En este artículo se muestra cómo el entorno Xfuzzy 3 desarrollado en el Instituto de Microelectrónica de Sevilla posee la versatilidad necesaria para abordar el diseño de estos sistemas, facilitando su descripción, verificación, ajuste y síntesis.
Hardware authentication based on PUFs and SHA-3 2(nd) round candidates
S. Eiroa and I. Baturone
Conference · International Conference on Microelectronics ICM 2010
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Security features are getting a growing interest in microelectronics. Not only entities have to authenticate in the context of a high secure communication but also the hardware employed has to be trusted. Silicon Physical Unclonable Functions (PUFs) or Physical Random Functions, which exploits manufacturing process variations in integrated circuits, have been used to authenticate the hardware in which they are included and, based on them, several cryptographic protocols have been reported. This paper describes the hardware implementation of a symmetric-key authentication protocol in which a PUF is one of the relevant blocks. The second relevant block is a SHA-3 2(nd) round candidate, a Secure Hash Algorithm (in particular Keccak), which has been proposed to replace the SHA-2 functions that have been broken no long time ago. Implementation details are discussed in the case of Xilinx FPGAs.
Microelectronics implementation of directional image-based fuzzy templates for fingerprints
R. Arjona, I. Baturone and S. Sánchez-Solano
Conference · International Conference on Microelectronics ICM 2010
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Fingerprint orientation image, also called directional image, is a widely used method in fingerprint recognition. It helps in classification (accelerating fingerprint identification process) as well as in preprocessing or processing steps (such as fingerprint enhancement or minutiae extraction). Hence, efficient storage of directional image-based information is relevant to achieve low-cost templates not only for "match on card" but also for "authentication on card" solutions. This paper describes how to obtain a fuzzy model to describe the directional image of a fingerprint and how this model can be implemented in hardware efficiently. The CAD tools of the Xfuzzy 3 environment have been employed to accelerate the fuzzy modeling process as well as to implement the directional image-based template into both an FPGA from Xilinx and an ASIC.
Automatic extraction of linguistic models for image description
I. Baturone and A. Gersnoviez
Conference · IEEE World Congress on Computational Intelligence WCCI 2010
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This paper describes a methodology to extract fuzzy models that describe linguistically the low-level features of an image (such as color, texture, etc.). The methodology combines grid-based algorithms with clustering and tabular simplification methods to compress image information into a small number of fuzzy rules with high linguistic meaning. All the steps of the methodology are carried out with the help offered by the tools of Xfuzzy 3 environment, so we can define, simplify, tune and verify the fuzzy models automatically. Several examples are included to illustrate the advantages of the methodology.
Tuning of a hierarchical fuzzy system for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE World Congress on Computational Intelligence WCCI 2010
resumen
The tuning of hierarchical fuzzy systems are not supported by the majority of CAD tools available at the market currently. The XFSL tool integrated into Xfuzzy 3 allows the tuning of complex fuzzy systems, for instance, hierarchical systems with modules in cascade. The authors propose the use of this tool for tuning a complex fuzzy system for video de-interlacing in this paper. The parameters obtained after tuning are proven by de-interlacing a wide battery of sequences. The use of tuning techniques improves the quality of de-interlacing and provides an algorithm simplification that facilitates its hardware implementation.
A design environment for synthesis of embedded fuzzy controllers on FPGAs
S. Sánchez-Solano, E. del Toro, M. Brox, I. Baturone and A. Barriga
Conference · IEEE World Congress on Computational Intelligence WCCI 2010
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This paper presents a design environment for the synthesis of embedded fuzzy controllers on FPGAs. It provides a novel implementation technique that allows accelerating the exploration of the design space of fuzzy control modules, as well as a codesign flow that eases their integration into complex control systems and the joint development of hardware and software components. The set of CAD tools supporting this environment includes specific fuzzy logic design tools provided by Xfuzzy, FPGA synthesis and implementation tools from Xilinx, and modeling and simulation facilities from Matlab. As demonstrated by the analyzed design examples, the described development strategy takes advantage of flexibility and ease of configuration offered by the different tools to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy control systems.
An automated design flow from linguistic models to piecewise polynomial digital circuits
I. Baturone, S. Sánchez-Solano, A.A. Gersnoviez and M. Brox
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
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This paper describes how the different CAD tools of the environment Xfuzzy 3, developed in Microelectronics Institute of Seville and University of Seville, allow to translate expressive linguistic models into mathematical ones, in particular, into a combination of piecewise polynomial systems that can be implemented efficiently in hardware. The new synthesis tool of Xfuzzy 3 automates communication with Xilinx System Generator in Matlab, thus facilitating implementation of the linguistic model into an FPGA from Xilinx. This is illustrated with the design of a navigation controller for an autonomous robot.
Un algoritmo de desentrelazado adaptativo con la repetición de imágenes basado en lógica difusa
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Iberchip XV Workshop IWS 2009
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Esta comunicación presenta un interpolator temporal basado en lógica difusa que es utilizado para el desentrelazado de la señal de vídeo. El objetivo es que dicho interpolador sea capaz de aprovechar una caracterísctica que cada vez es más frecuente en las secuencias, debido a los estándares de conversión entre distintos formatos de transmisión, como es la repetición de imágenes. Este nuevo interpolador es incluido en un algoritmo adaptativo en función del movimiento, obteniendo una técnica de desentrelazado muy competitiva frente a otros algoritmos que son actualmente utilizados en ASICs de dispositivos comerciales de altas prestaciones. Los resultados de simulación obtenidos al desentrelazar secuencias de distintos materiales (film, vídeo e híbrido) muestran la superioridad del algoritmo propuesto.
XfuzzyLib: una librería de módulos para la síntesis hardware de sistemas de inferencia difusos
S. Sánchez-Solano, M. Brox, I. Baturone and A. Barriga
Conference · XIV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2008
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Esta comunicación presenta una nueva técnica de implementación de sistemas difusos que está basada en el uso de una librería de módulos específicos, denominada XfuzzyLib, y cuyo flujo de diseño combina las herramientas de modelado y simulación del entorno Matlab con las de síntesis e implementación de FPGAs de Xilinx. La estrategia propuesta, que constituye la base de una nueva herramienta de síntesis hardware del entorno Xfuzzy, aprovecha las ventajas de flexibilidad y facilidad de configuración que brindan las diferentes herramientas de Matlab y Xilinx, permitiendo acelerar considerablemente las etapas de descripción, síntesis y verificación funcional de los sistemas bajo desarrollo.
Síntesis hardware de módulos de inferencia difusos mediante herramientas de diseño de DSP
M. Brox, S. Sánchez-Solano, P. Brox, I. Baturone, A. Barriga and A. Gersnoviez
Conference · VIII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2008
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En esta comunicación se describe una nueva estrategia de desarrollo de sistemas de control basados en lógica difusa mediante un flujo de diseño que combina las herramientas de modelado y simulación del entorno Matlab y las herramientas de síntesis e implementación de FPGAs de Xilinx. Apoyada en el uso de una librería de módulos específicos para sistemas difusos, esta estrategia acelera las etapas de descripción, síntesis y verificación funcional de los sistemas bajo desarrollo.
Nuevos algoritmos de clasificación integrados en Xfuzzy 3
F.J. Moreno-Velo, I. Baturone and S. Sánchez-Solano
Conference · XIV Congreso Español sobre Tecnologías y Lógica Fuzzy ESTYLF 2008
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El entorno Xfuzzy 3 está formado por un amplio conjunto de herramientas dedicadas a dar soporte a las diferentes etapas del desarrollo de sistemas difusos. Entre estas herramientas se encuentra Xfdm, dedicada a la extracción de conocimiento difuso a partir de conjuntos de datos. Este trabajo presenta las últimas modificaciones realizadas en esta herramienta, que consisten en la integración de los algoritmos de clasificación difusos FuzzyID3 y FuzzConRI.
A motion and edge adaptive interlaced-to-progressive conversion using fuzzy logic-based systems
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Information Processing and Management of Uncertainty in Knowledge-based Systems IPMU 2008
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This paper presents an algorithm for video de-interlacing. The approach uses three fuzzy logic-based systems to adapt the interpolation strategy to the presence of motion and edges. Furthermore, the algorithm is able to deal with any kind of TV material independently of the source used to acquire the scene. Extensive simulations of standard and real sequences prove the efficiency of the proposed algorithm.
FPGA-based implementation of a fuzzy motion adaptive de-interlacing algorithm
P. Brox, S. Sánchez-Solano and I. Baturone
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2007
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This paper surveys the hardware implementation of a de-interlacing algorithm on Field-Programmable Technology for real-time processing. The algorithm presented evaluates the level of motion at each pixel, and determines the interpolation between a spatial and a temporal method according to the presence of motion. To achieve it the algorithm employs an hierarchical structure with three simple fuzzy systems. The first one performs a set of fuzzy rules to apply reasoning in order to detect motion; the second one selects the most convenient direction to implement an edge-dependent line average method; and the third one is used to choose the most adequate temporal method.
The hardware implementation of this algorithm combines pipeline architecture with a parallel processing of fuzzy rules to accelerate the computation. As result an efficient implementation is developed in terms of computational time and hardware cost.
Aplicación de técnicas de interpolación basadas en lógica difusa al procesado de imágenes de video
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Iberchip XIII Workshop IWS 2007
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Muchas tareas básicas de procesado de imágenes requieren la manipulación de grandes volúmenes de información que, en ocasiones, puede resultar ambigua y/o imprecisa como consecuencia de las características propias de las imágenes (gran cantidad de detalles con grandes contrastes de valores de luminancia y secuencias con un elevado grado de movimiento) o de los defectos de las mismas (presencia de ruido, falta de nitidez, etc.). En esta comunicación se analizan nuevas técnicas de interpolación basadas en lógica difusa que proporcionan soluciones eficaces para dos aplicaciones típicas de procesado de imágenes: el desentrelazado de señales de vídeo y el incremento de resolución de imágenes.
A fuzzy motion adaptive de-interlacing algorithm capable of detecting field repetition patterns
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · IEEE International Symposium on Intelligent Signal Processing WISP 2007
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A new motion adaptive algorithm for de-interlacing video is proposed in this paper. It employs two fuzzy systems to interpolate the missing lines of the transmission. One fuzzy system is used to evaluate the motion level at the current pixel, and a second one selects the most adequate temporal interpolation method. The combination of both systems provides an effective result with a low cost in term of hardware resources.
Using xfuzzy environment for the whole design of fuzzy systems
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano, A. Barriga, P. Brox, A.A. Gersnoviez and M. Brox
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2007
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Since 1992, Xfuzzy environment has been improving to ease the design of fuzzy systems. The current version, Xfuzzy 3, which is entirely programmed in Java, includes a wide set of new featured tools that allow automating the whole design process of a fuzzy logic based system: from its description (in the XFL3 language) to its synthesis in C, C++ or Java (to be included in software projects) or in VHDL (for hardware projects). The new features of the current version have been exploited in different application areas such as autonomous robot navigation and image processing.
A simple neuro-fuzzy controller for car-like robot navigation avoiding obstacles
I. Baturone and A.A. Gersnoviez
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2007
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This paper describes how the combination of neuro-fuzzy techniques with geometric analysis offers a good trade-off between purely heuristics and purely physical approaches when solving the problem of car-like robot navigation. The controller described, which follows a reactive technique, generates trajectories of near-minimal lengths when no obstacles are detected and, in presence of obstacles, generates minimum deviations from them. All these reference paths meet the kinematic constraints of car-like robots and take into account dynamic issues. Besides its efficiency, the proposed controller is very simple and linguistically interpretable. The whole controller has been designed and verified by using the CAD tools of the Xfuzzy environment.
New features of the fuzzy logic development environment Xfuzzy
A. Barriga, S. Sánchez-Solano, I. Baturone, D.R. López, F.J. Moreno-Velo, F. Montesino, P. Brox and N.M. Hussein
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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The characteristics of the new version of the fuzzy systems development environment Xfuzzy is presented. The environment covers the aspects related to the specification, verification, adjustment and implementation of fuzzy systems. It is an open environment (in the sense that the user can define many functional and structural aspects) and a free distribution tool that allows proving new formalisms and helps the definition and implementation of complex systems.
Image Enlargement using the Fuzzy-ELA Algorithm
P. Brox, I. Baturone, S. Sánchez-Solano and A. Barriga
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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The increase of resolution is one of the most important tasks in image processing. Traditional interpolation algorithms perform a linear interpolation between the closest pixels in the image. This strategy may introduce mistakes specially in the reconstruction of edges and zones with high contrast luminance values. The use of a novel interpolation algorithm for image enlargement is presented in this paper. It employs a fuzzy logic-system to adapt the interpolation to the presence of edges in the image, achieving good results at expense of a low increment in the computational cost.
Fuzzy Motion Adaptive Algorithm for Video De-interlacing
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutiérrez-Ríos and F. Fernández-Hernández
Conference · International Conference on Knowledge-Based and Intelligent Information and Engineering Systems KES 2006
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A motion adaptive algorithm for video de-interlacing is presented in this paper. It is based on a fuzzy inference system, which performs an interpolation between two linear techniques as a function of the motion level. Fuzzy systems with different number of 'if-then' rules have been analyzed and compared in terms of complexity as well as efficiency in de-interlacing benchmark video sequences.
Extracción de bases de reglas simples y lingüísticamente interpretables
A. Gersnoviez, I. Baturone and F.J. Moreno-Velo
Conference · XIII Congreso Español de Tecnologías y Lógica Fuzzy ESTYLF 2006
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Este artículo presenta una técnica basada en la lógica difusa para extraer bases de reglas a partir de datos numéricos. Permite obtener bases de reglas interpretables lingüísticamente a la vez que simples en cuanto a número de reglas, sencillez en las partes antecedentes y consecuentes y facilidad de implementación hardware/software. Los pasos más significativos de esta técnica son los siguientes: (1) extracción de la base de reglas empleando particiones granulares de las variables del problema, (2) ajuste de las funciones de pertenencia para las variables de salida y posterior simplificación, (3) simplificación tabular de la base de reglas y (4) simplificación de las funciones de pertenencia para las variables de entrada. La técnica puede aplicarse de forma automática mediante las herramientas de CAD integradas en el entorno Xfuzzy 3. Se incluye un ejemplo de aplicación en robótica móvil para ilustrar las ventajas de la técnica propuesta.
Desarrollo de Módulos-IP de Controladores Difusos para el Diseño de Sistemas Empotrados sobre FPGAs
M. Brox, A. Gersnoviez, S. Sánchez-Solano, A.J. Cabrera and I. Baturone
Conference · VII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2006
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En esta comunicación se describe el diseño de controladores basados en lógica difusa como módulos de Propiedad Intelectual (IP) compatibles con los sistemas de procesado disponibles en las familias de FPGAs de Xilinx. El trabajo fue propuesto como caso práctico de un curso de postgrado de diseño de sistemas empotrados sobre FPGAs. Su realización permitió reforzar los conocimientos de los alumnos en disciplinas relacionadas con: diseño de sistemas digitales, arquitectura de computadores, codiseño hardware-software y aplicaciones de control.
Controlador difuso para problemas de navegación en presencia de obstáculos fijos
M. Brox, A. Gersnoviez, S. Sánchez-Solano and I. Baturone
Conference · XIII Congreso Español de Tecnologías y Lógica Fuzzy ESTYLF 2006
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En esta comunicación se describe un sistema de control difuso para aplicaciones de navegación de robots móviles autónomos en presencia de obstáculos fijos. Las herramientas de CAD del entorno Xfuzzy 3, desarrollado en el IMSE, han facilitado el diseño del controlador. En la comunicación se procede a la verificación del controlador diseñado operando en un lazo cerrado con el modelo del robot móvil autónomo eléctrico Romeo 4R, diseñado y construido en la Escuela Superior de Ingenieros de la Universidad de Sevilla. Las simulaciones realizadas demuestran la eficiencia del controlador desarrollado.
Algoritmo adaptativo con el grado de movimiento para el desentrelazado de vídeo
P. Brox, I. Baturone, S. Sánchez-Solano, J. Gutiérrez-Ríos and F. Fernández-Hernández
Conference · XIII Congreso Español de Tecnologías y Lógica Fuzzy ESTYLF 2006
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En esta comunicación se presenta un algoritmo adaptativo con el movimiento para el desentrelazado de vídeo. Se basa en un sistema de inferencia difuso, que realiza una interpolación entre dos técnicas lineales en función del grado de movimiento. Se ha realizado un estudio de diferentes sistemas difusos con distinto número de funciones de pertenencia, analizándose el grado de complejidad de los mismos frente a su eficacia desentrelazando varias secuencias de vídeo.
A Fuzzy Motion Adaptive Algorithm for Interlaced-to-Progressive Conversion
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Information Processing and Management of Uncertainty in Knowledge-Based Systems IPMU 2006
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Interlaced-to-progressive algorithms are currently required by video format conversion systems in order to display a progressive scanning used in modern visualization equipments. Deinterlacing algorithms use interpolation techniques to calculate missing pixels in transmitted fields. A motion adaptive algorithm which employs fuzzy logic to adapt the interpolation strategy to the presence of motion in the images is proposed in this paper. The performance of this new approach is evaluated by extensive simulation of different video sequences.
A CAD approach to simplify fuzzy system descriptions
I. Baturone, F.J. Moreno-Velo and A. Gersnoviez
Conference · IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2007
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Simplification is an important step in the design of a fuzzy system since the membership functions that represent the fuzzy sets as well as the 'if-then' rules that relate them usually contain redundant information. This paper presents a CAD tool which provides the user with a wide set of algorithms to automate simplification process. It allows reducing the number of membership functions and rules described initially as well as increasing its expressiveness and linguistic interpretability. Since the tool is included within the design environment Xfuzzy 3, the simplified system can be also verified, tuned and synthesized automatically. Several examples are included to illustrate the efficiency of the simplification facilities provided.
Directional motion adaptive fuzzy method for video de-interlacing
J. Gutiérrez-Ríos, F. Fernández-Hernández, P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Conference · Artificial Neural Networks in Engineering ANNIE 2005
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The procedure employed to make de-interlacing of video sequences has great influence in the quality of the obtained image. Reaching good results is not possible if dynamical characteristics of the processed image are not considered. On the other hand, the gradual adjust of the de-interlacing procedure as a function of the motion detected in each pixel of the image is a powerful method that is able to be realised by means of fuzzy inference. Detection of motion direction in each pixel of a frame becomes important in order to choose inclination in the spatial interpolation operations. In this paper we start from a fuzzy algorithm proposed by Van de Ville et al. to succeed in a family of more efficient algorithms under the point of view of execution speed and quality. These algorithms are based on convolution techniques (in substitution of the sum-prod norms) that are able to create a good emphasising distribution on the input variables.
Progressive scan conversion based on edge-dependent interpolation using fuzzy logic
P. Brox, I. Baturone and S. Sánchez-Solano
Conference · Conf. of the European Society for Fuzzy Logic and Technology & 11th French Days on Fuzzy Logic and Applications EUSFLAT-LFA 2005
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De-interlacing algorithms realize the interlaced to progressive conversion required in many applications. The most cost efficient are intra-field techniques which interpolate pixels of the same field. Some of these methods use the upper and lower line pixels. Among them, the ELA algorithm is widely employed since it reconstructs the edges of the de-interlaced image with more accuracy eliminating nondesired problems such as blurring and staircase effects. However, the ELA algorithm does not perform well when there are non clear edges or in presence of noise. In order to reduce these drawbacks, a new algorithm is presented in this paper. It is based on a simple fuzzy system which models heuristic rules to improve the ELA algorithm. Two enhancements of this new algorithm are also presented in this paper. Simulation results of video sequences prove the advantageous of the new algorithms.
Embedded fuzzy controllers on standard DSPs
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano, V. Blanco and J. Ferruz
Conference · IEEE International Symposium on Industrial Electronics ISIE 2005
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Fuzzy controllers are used in many applications because of their rapid design by translating heuristic knowledge, robustness against perturbations, and smoothness in the control action. However, they require parallel processing and special operators (such as fuzzification or defuzzification) which are not available at standard DSPs, thus making inefficient its direct implementation. This paper describes a design methodology which allows starting with any kind of fuzzy controller and subsequently transforming it until obtaining a system suitable for DSP implementation. Such methodology is aided by Xfuzzy 3, a design environment developed by some of the authors. The parking problem of an autonomous robot is described to illustrate the steps of this methodology. Experimental results show the efficiency of the designed fuzzy controller embedded into a stand-alone card based on a fixed-point DSP from Texas Instruments.
Fuzzy logic activities at the Microelectronics Institute of Seville
A. Barriga, S. Sánchez-Solano, I. Baturone, F. Moreno-Velo, P. Brox, F. Montesino, N.M. Hussein, M. Brox and A. Gersnoviez
Conference · XVI Italian Workshop on Neural Nets WIRN 2005
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In this communication we present the activities related to the development of fuzzy logic based systems at the Microelectronics Institute of Seville (Spain). These activities regard with the design of circuits and systems that operate in fuzzy logic, the development of CAD tools for fuzzy logic and the accomplishment of applications that use fuzzy logic in the resolution of certain problems.
FPGA implementation of a fuzzy based video de-interlacing algorithm
P. Brox, S. Sánchez-Solano, I. Baturone and A. Barriga
Conference · Conference on VLSI Circuits and Systems II, 2005
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De-interlacing algorithms are used to convert interlaced video into progressive scan format. Among the different techniques reported in the literature, motion adaptive de-interlacing techniques that combine spatial and temporal interpolation according to the presence of motion achieve good results with a low computational cost. This paper presents the FPGA implementation of a motion adaptive algorithm which employs fuzzy logic in detecting motion and edges. Motion, which is evaluated at each pixel of the deinterlaced frame, determines the interpolation between an enhanced edge-dependent line average method and field insertion. Extensive simulations with video sequences show the advantages performance of the proposed method over other well-known de-interlacing techniques. The hardware implementation of the algorithm has been carried out on a FPGA obtaining a low-cost solution for real-time processing.
Codiseño Hardware/Software de controladores difusos mediante módulos de propiedad intelectual
A. Barriga, I. Barturone, P. Brox, A. Cabrera, F.J. Moreno and S. Sánchez-Solano
Conference · VI Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2004
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El uso de técnicas de diseño basadas en módulos de propiedad intelectual (IP) constituye una alternativa válida para salvar la creciente distancia entre los recursos proporcionados por las actuales tecnologías de fabricación de circuitos integrados y la productividad alcanzada por los diseñadores de sistemas. Esta comunicación describe el desarrollo de un sistema de control basado en lógica difusa mediante una técnica de codiseño hardware/software que combina un procesador de propósito general disponible como módulo-IP y hardware específico para la síntesis del módulo de inferencia. La implementación física se ha llevado a cabo mediante una plataforma de desarrollo basada en FPGAs, lo que permite la realización de todo el sistema como un SoPC (System on Programmable Chip).
Development of fuzzy control systems on programmable chips: Application to motion planning of mobile robots
A. Cabrera, S. Sánchez-Solano, I. Baturone, F. Moreno-Velo, P. Brox and A. Barriga
Conference · International Symposium on Robotics and Applications ISORA 2004
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This paper describes the realization of embedded fuzzy control systems for planning the motion of autonomous mobile robots. The development of the controllers is carried out by means of a reconfigurable platform based on FPGAs. This platform combines a general-purpose processor with specific hardware to implement fuzzy inference modules, thus allowing the comparison between a fully software solution and others based on hybrid hardware/software techniques. Both the processing system and the inference modules are configurable using available CAD tools, which make the development of the controllers easier.
The parametric definition of membership functions in XFL3
F.J. Moreno-Velo, I. Baturone, S. Sánchez-Solano and A. Barriga
Conference · Annual IEEE International Conference on Fuzzy Systems FUZZ-IEEE 2004
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This paper presents a study of the different kinds of membership function (MF) definitions, regarding free MFs and families of MFs, and describes the capabilities of XFL3 (the formal specification language defined by Xfuzzy 3) to manage them. This includes not only the possibility of using them in a system design, but also the capability for extending the available functions with new user-defined membership functions and families. An application example has been included in order to discuss on the suitable parametric definition of the functions.
Implementación sobre FPGAs de sistemas difusos programables
S. Sánchez-Solano, A. Cabrera, C.J. Jiménez, P. Brox, I. Baturone and A. Barriga
Conference · Workshop IBERCHIP 2003
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El número de aplicaciones electrónicas que utilizan soluciones basadas en lógica difusa se ha incrementado considerablemente en los últimos años y, de forma paralela, se han desarrollado nuevas herramientas de CAD que contemplan diferentes técnicas de implementación para este tipo de sistemas. De entre ellas, el uso de arquitecturas específicas de procesado implementadas sobre FPGAs presenta como principales ventajas una buena relación 'coste-rendimiento' y un ciclo de desarrollo aceptablemente corto. En esta comunicación se analizan las distintas facilidades de síntesis que proporciona el entorno de diseño Xfuzzy para la implementación de sistemas difusos programables que aprovechen los recursos disponibles en las actuales familias de FPGAs.
VHDL high level modelling and implementation of fuzzy systems
A. Barriga, S. Sánchez-Solano, P. Brox, A. Cabrera and I. Baturone
Conference · International Workshop on Fuzzy Logic and Applications WILF 2003
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In this paper we illustrate a fuzzy logic system design strategy based on a high level description. Employing this high level description, the knowledge base is described in a language in appearance close to the natural language with the particularity that it uses a hardware description language (VHDL) directly synthesizable on an FPGA circuit. In addition, we analyze FPCA implementations of different fuzzy inference hardware architectures in order to characterize them in terms of area and speed.
Optimizing the design of a fuzzy path planner for car-like autonomous robots
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano and A. Ollero
Conference · International Conference on Advanced Robotics ICAR 2003
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This paper presents methods and tools to design a fuzzy path planner for autonomous non-holonomic vehicles by means of supervised learning. The method combines heuristic knowledge and geometric considerations to obtain a continuous-curvature short path that can be executed efficiently by the path tracking controller of the mobile robot. Furthermore, the method minimizes the computer requirements to implement the fuzzy planner. The proposed design method can be easily carried out by means of the Xfuzzy 3.0 environment developed by some of the authors. The resulting planning strategies have been proven successfully in the Romeo 4R autonomous vehicle fully designed and built at the Escuela Superíor de Ingenieros, University of Seville.
Tuning complex fuzzy systems by supervised learning algorithms
F.J. Moreno-Velo, I. Baturone, R. Senhadji and S. Sánchez-Solano
Conference · IEEE International Conference on Fuzzy Systems FUZZ 2003
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Tuning a fuzzy system to meet a given set of input/output patterns is usually a difficult task that involves many parameters. This paper presents an study of different approaches that can be applied to perform this tuning process automatically, and describes a CAD tool, named xfs1, which allows applying a wide set of these approaches: (a) a large number of supervised learning algorithms; (b) different processes to simplify the learned system; (c) tuning only specific parameters of the system; (d) the ability to tune hierarchical fuzzy systems, systems with continuous output (like fuzzy controller) as well as with categorical output (like fuzzy classifiers), and even systems that employ user-defined fuzzy functions; and, finally, (e) the ability to employ this tuning within the design flow of a fuzzy system, because xfs1 is integrated into the fuzzy system development environment Xfuzzy 3.0.
Rapid design of fuzzy systems with XFUZZY
F.J.M. Velo, I. Baturone, S. Sánchez-Solano and A. Barriga
Conference · IEEE International Conference on Fuzzy Systems FUZZ 2003
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The crecient use of fuzzy systems in complex applications has motivated us to develop a new version of Xfuzzy, the design environment for fuzzy system created at the IMSE (Instituto de Microelectronica de Sevilla). This new version, Xfuzzy 3.0, offers the advantages of being enterely programmed in Java, and allows designing hierarchical rule bases that can interchange fuzzy or non fuzzy values as well as employ user-defined fuzzy connectives, linguistic hedges, membership functions, and defuzzification methods. Xfuzzy 3.0 integrates tools that facilitate the description, tuning, verification, and synthesis of complex fuzzy systems. This is illustrated in this paper with the design of a fuzzy controller to solve a parking problem.
Automatic design of fuzzy control systems for autonomous mobile robots
I. Baturone, F.J. Moreno-Velo, S. Sánchez-Solano and R.M. de Agar
Conference · IEEE Industrial Electronics Conference IECON 2002
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This paper describes the design and implementation of a fuzzy controller for autonomous mobile robots. The tool Xfuzzy 3.0, developed at the IMSE (Instituto de Microelectronica de Sevilla) has been used to design a controller for the Romeo 4R autonomous vehicle designed and built at the "Escuela SupeRíor de Ingenieros", University of Seville. The paper presents the design of the controller and real experiments with Romeo 4R demonstrating the efficiency of the controller.
Prototyping of fuzzy logic-based controllers using standard FPGA development boards
S. Sánchez-Solano, R. Senhadji, A. Cabrera, I. Baturone, C.J. Jiménez and A. Barriga
Conference · IEEE International Workshop on Rapid System Prototyping RSP 2002
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This paper describes a design methodology for fuzzy logic-based control systems. The methodology employs hardware/software codesign techniques according to an 'a priori' partition of the tasks assigned to the selected components. This feature makes it possible to tackle the control system prototyping as one of the design stages. In our case, the platform considered for prototyping has been a development board containing a standard microcontroller and an FPGA. Experimental results from an actual control application validate the efficiency of this methodology.
Libros
Fuzzy logic-based algorithms for video de-interlacing
P. Brox, I. Baturone and S. Sánchez-Solano
Book · STUDFUZZ, vol. 246, 184 p, 2010
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The Fuzzy Logic research group of the Microelectronics Institute of Seville is composed of researchers who have been doing research on fuzzy logic since the beginning of the 1990s. Mainly, this research has been focused on the microelectronic design of fuzzy logic-based systems using implementation techniques which range from ASICs to FPGAs and DSPs. Another active line was the development of a CAD environment, named Xfuzzy, to ease such design. Several versions of Xfuzzy have been and are being currently developed by the group. The addressed applications had basically belonged to the control field domain. In this sense, several problems without a linear control solution had been studied thoroughly. Some examples are the navigation control of an autonomous mobile robot and the level control of a dosage system.
This book is organized in five chapters. In Chapter 1, some basic concepts are explained to completely understand the contribution of the algorithms developed in this research work. The evaluation of how motion is present and how it influences on de-interlacing is studied in Chapter 2. The design options of the proposed fuzzy motion-adaptive de-interlacing algorithm is studied in Chapter 3. A spatial interpolator that adapts the interpolation to the presence of edges in a fuzzy way is developed in Chapter 4. A temporal interpolator that adapts the strategy of the interpolation to possible repetition of areas of fields is presented in Chapter 5. Using both interpolators in the fuzzy motion-adaptive algorithm described in Chapter 3 clearly improves the de-interlaced results.
Capítulos de libros
A fuzzy edge-dependent interpolation algorithm
P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Book Chapter · Soft Computing in Image Processing: Recent Advances, STUDFUZZ, vol. 210, pp 157-183, 2007
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Images have always been very important in human life. Their applications range from primitive communication between humans of all ages to advanced technologies in the industrial, medical and military field. The increased possibilities to capture and analyze images have contributed to the largeness that the scientific field of "image processing" has become today. Many techniques are being applied, including soft computing.
Directional motion adaptive fuzzy method for video de-interlacing
J. Gutiérrez-Ríos, F. Fernández-Hernández, P. Brox-Jiménez, I. Baturone-Castillo and S. Sánchez-Solano
Book Chapter · Intelligent Engineering Systems Through Artificial Neural Networks, pp 567-577, 2005
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The procedure employed to make de-interlacing of video sequences has great influence in the quality of the obtained image. Reaching good results is not possible if dynamical characteristics of the processed image are not considered. On the other hand, the gradual adjust of the de-interlacing procedure as a function of the motion detected in each pixel of the image is a powerful method that is able to be realised by means of fuzzy inference. Detection of motion direction in each pixel of a frame becomes important in order to choose inclination in the spatial interpolation operations. In this paper we start from a fuzzy algorithm proposed by Van de Ville et al. to succeed in a family of more efficient algorithms under the point of view of execution speed and quality. These algorithms are based on convolution techniques (in substitution of the sum-prod norms) that are able to create a good emphasising distribution on the input variables.
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