Encontrados resultados para:
Autor: Antonio J. Acosta Jiménez
Año: Desde 2002
Artículos de revistas
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher
F.E. Potestad-Ordóñez, E. Tena-Sánchez, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and R. Chaves
Journal Paper · IEEE Access, vol. 10, pp 65548-65561, 2022
resumen
doi
Differential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the vulnerabilities of physical implementations of block ciphers, currently used in a multitude of applications, such as the Advanced Encryption Standard (AES). In order to minimize these types of vulnerabilities, several mechanisms have been proposed to detect fault attacks. However, these mechanisms can have a significant cost, not fully covering the implementations against fault attacks or not taking into account the leakage of the information exploitable by the power analysis attacks. In this paper, four different approaches are proposed with the aim of protecting the AES block cipher against DFA. The proposed solutions are based on Hamming code and parity bits as signature generators for the internal state of the AES cipher. These allow to detect DFA exploitable faults, from bit to byte level. The proposed solutions have been applied to a T-box based AES block cipher implemented on Field Programmable Gate Array (FPGA). Experimental results suggest a fault coverage of 98.5% and 99.99% with an area penalty of 9% and 36% respectively, for the parity bit signature generators and a fault coverage of 100% with an area penalty of 18% and 42% respectively when Hamming code signature generator is used. In addition, none of the proposed countermeasures impose a frequency degradation, in respect to the unprotected cipher. The proposed work goes further in the evaluation of the proposed DFA countermeasures by evaluating the impact of these structures in terms of power side-channel. The obtained results suggest that no extra information leakage is produced that can be exploited by PA. Overall, the proposed DFA countermeasures provide a high fault coverage protection with a low cost in terms of area and power consumption and no PA security degradation.
Hardware Countermeasures Benchmarking against Fault Attacks
F.E. Potestad-Ordóñez, E. Tena-Sánchez, A.J. Acosta, C.J. Jiménez-Fernández and R. Chaves
Journal Paper · Applied Sciences, vol. 12, no. 5, article 2443, 2022
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The development of differential fault analysis (DFA) techniques and mechanisms to inject faults into cryptographic circuits brings with it the need to use protection mechanisms that guarantee the expected level of security. The AES cipher, as a standard, has been the target of numerous DFA techniques, where its security has been compromised through different formulations and types of fault injections. These attacks have shown vulnerabilities of different AES implementations and building blocks. Consequently, several solutions have been proposed that provide additional protection to cover the identified vulnerabilities. In this paper, an extensive analysis has been carried out covering the existing fault injection techniques, the types of faults, and the requirements needed to apply DFA. Additionally, an analysis of the countermeasures reported in the literature is also presented, considering the protection provided, the type of faults considered, and the coverage against fault attacks. The eight different types of fault that allow us to perform DFAs on the AES cipher have been differentiated, as well as the vulnerabilities of the cipher. On the other hand, two comparisons have been made considering frequency penalty vs. area and fault coverage vs. area and frequency overhead. A metric has been proposed to compare the fault coverage of all the proposed solutions. To conclude, a final analysis is presented discussing the key aspects when choosing a particular solution and the possible development of new countermeasures to provide further protection against DFA.
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
E. Tena-Sánchez, F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, A.J. Acosta and R. Chaves
Journal Paper · Applied Sciences, vol. 12, no. 5, article 2390, 2022
resumen
doi
The fast settlement of privacy and secure operations in the Internet of Things (IoT) is appealing in the selection of mechanisms to achieve a higher level of security at minimum cost and with reasonable performances. All these aspects have been widely considered by the scientific community, but more effort is needed to allow the crypto-designer the selection of the best style for a specific application. In recent years, dozens of proposals have been presented to design circuits resistant to power analysis attacks. In this paper, a deep review of the state of the art of gate-level countermeasures against power analysis attacks has been carried out, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison. Advantages and drawbacks of the proposals are analyzed, showing quantified data for cost, performance (delay and power), and security when available. One of the main conclusions is that the RSL proposal is the best in masking, while TSPL, HDRL, SDMLp, 3sDDL, TDPL, and SABL are those with the best security performance figures. Nevertheless, a wise combination of hiding and masking as masked_SABL presents promising results.
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles using TFETs
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A.J. Acosta
Journal Paper · IEEE Embedded Systems Letters, vol. 14, no. 2, pp 99-102, 2021
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doi
The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. The paper deals with the optimized design of DPA-resilient hiding-based techniques, using Tunnel Field-Effect Transistors (TFETs). Specifically, proposed TFET implementations of Dual-Precharge-Logic primitives optimizing their computation tree in three different ways, are applied to the design of PRIDE Sbox-4, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals have shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction (x25), compared to their CMOS-based counterparts in 65nm, which is a significant advance in the development of secure circuits with TFETs.
Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A. Acosta
Journal Paper · ACM Journal on Emerging Technologies in Computing Systems, vol. 16, no. 3, article 30, 2020
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The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4-bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude.
Design and analysis of secure emerging crypto-hardware using HyperFET devices
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A.J. Acosta
Journal Paper · IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp 787-796, 2020
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doi
The emergence of new devices to be used in low-power applications are expected to reach impressive performance compared to those obtained by equivalent CMOS counterparts. However, when used in lightweight security applications, these emerging paradigms are required to be reliable and safe enough during the task of protecting important and valuable data. In this work, the usage of HyperFET devices for security applications has been analyzed and new paradigms for enhancing security against Power Analysis attacks have been developed for the first time. To perform this analysis, classical dual-precharge logic primitives implemented with 14nm FinFET have been upgraded to incorporate HyperFET devices. The proposed primitives incorporating HyperFETs, as well as a 4-bit Substitution box of PRIDE algorithm as demonstrative example, have been designed and simulated using predictive models. Simulation-based Differential Power Analysis attacks demonstrate high improvements in security levels in a x25 factor at least, with negligible degradation in performance. This first approach could be easily extensible to other ciphers or crypto-circuits, where the incorporation of HyperFET devices will enhance security for most future applications.
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks
E. Tena-Sánchez and A.J. Acosta
Journal Paper · International Journal of Circuit Theory and Applications, vol. 47, no. 2, pp 238-253, 2019
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This paper discusses the use of logic minimization techniques and wide fan-in primitives and how the design and evaluation of combinational blocks for full-custom dual-precharge-logic-based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed and applied to the gate-level design of substitution boxes, widely used in block ciphers, using sense-amplifier-based logic in a 90-nm technology. The security of several proposals was evaluated with simulation-based correlation power analysis attacks, using the secret key measurements to disclosure metric. The simulation results showed increased security-power-delay figures for our proposals and, surprisingly, indicated that those solutions which minimized area occupation were both the most secure and the most power-efficient.
Power and energy issues on lightweight cryptography
A.J. Acosta, E. Tena-Sánchez, C.J. Jiménez and J.M. Mora
Journal Paper · Journal of Low Power Electronics, vol. 13, no. 3, pp 326-337, 2017
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Portable devices such as smartphones, smart cards and other embedded devices require encryption technology to guarantee security. Users store private data in electronic devices on a daily basis. Cryptography exploits reliable authentication mechanisms in order to ensure data confidentiality. Typical encryption security is based on algorithms that are mathematically secure. However, these algorithms are also costly in terms of computational and energy resources. The implementation of security mechanisms on dedicated hardware has been shown as a first-order solution to meet prescribed security standards at low power consumption with limited resources. These are the guidelines of the so-called lightweight cryptography. Upcoming Internet of Thing (IoT) is extensively demanding solutions in this framework. Interestingly, physical realizations of encryption algorithms can leak side-channel information that can be used by an attacker to reveal secret keys or private data. Such physical realizations must therefore be holistically addressed. Algorithm, circuit and layout aspects are to be considered in order to achieve secure hardware against active and passive attacks. In order to address the challenges raised by the IoT, both academia and industry are these days devoting significant efforts to the implementation of secure lightweight cryptography. This paper is a survey of (i) lightweight cryptography algorithms; (ii) techniques to reduce power applied to cryptohardware implementations; (iii) vulnerability analysis of low-power techniques against sidechannel attacks; and (iv) possibilities opened to emerging technologies and devices in the "More than Moore" scenario.
Guest Editorial. Secure lightweight crypto-hardware
A.J. Acosta and T. Addabbo
Journal Paper · International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 143-144, 2017
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Abstract not avaliable
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
A.J. Acosta, T. Addabbo and E. Tena-Sánchez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 145-169, 2017
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doi
We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators. In detail, we discuss the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography, and hash functions, discussing some important security issues in electronic crypto-devices, related to side-channel attacks (SCAs), fault injection attacks, and the corresponding design countermeasures that can be taken. Finally, we present an overview about the hardware implementation of true random number generators, discussing the chief electronic sources of randomness and the types of post-processing techniques used to improve the statistical characteristics of the generated random sequences.
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions
P. Brox, M.C. Martínez-Rodríguez, E. Tena-Sánchez, I. Baturone and A.J. Acosta
Journal Paper · International Journal of Circuit Theory and Applications, vol. 44, no. 1, pp. 4-20, 2015
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This paper presents a fully digital architecture and its application specific integrated circuit implementation for computing multi-input multi-output (MIMO) piecewise-affine (PWA) functions. The work considers both PWA functions defined over regular hyperrectangular and simplicial partitions of the input domains and also lattice PWA representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with application specific integrated circuit (ASIC) integrated in a 90-nm complementary metal-oxide semiconductor standard technology are provided. The proposed architecture is compared with other digital architectures in the state of the art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high-performance and minimum unitary cost are required.
Special issue on 'Secure lightweight crypto-hardware'
A.J. Acosta and T. Addabbo
Journal Paper · International Journal of Circuit Theory and Applications, vol. 43, no. 12, pp. 2089-2090, 2015
resumen
doi
Abstract not avaliable
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits
E. Tena-Sánchez, J. Castro and A.J. Acosta
Journal Paper · IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, no. 2, pp 203-215, 2014
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doi
Cryptocircuits can be attacked by third parties using differential power analysis (DPA), which uses power consumption dependence on data being processed to reveal critical information. To protect security devices against this issue, differential logic styles with (almost) constant power dissipation are widely used. However, to use such circuits effectively for secure applications it is necessary to eliminate any energy-secure flaw in security in the shape of memory effects that could leak information. This paper proposes a design methodology to improve pull-down logic configuration for secure differential gates by redistributing the charge stored in internal nodes and thus, removing memory effects that represent a significant threat to security. To evaluate the methodology, it was applied to the design of AND/NAND and XOR/XNOR gates in a 90 nm technology, adopting the sense amplifier based logic (SABL) style for the pull-up network. The proposed solutions leak less information than typical SABL gates, increasing security by at least two orders of magnitude and with negligible performance degradation. A simulation-based DPA attack on the Sbox9 cryptographic module used in the Kasumi algorithm, implemented with complementary metal-oxide-semiconductor, SABL and proposed gates, was performed. The results obtained illustrate that the number of measurements needed to disclose the key increased by much more than one order of magnitude when using our proposal. This paper also discusses how the effectivenness of DPA attacks is influenced by operating temperature and details how to insure energy-secure operations in the new proposals.
A programmable and configurable ASIC to generate piecewise-affine functions defined over general partitions
P. Brox, R. Castro-Ramirez, M.C. Martinez-Rodriguez, E. Tena, C.J. Jimenez, I. Baturone and A.J. Acosta
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 12, pp 3182-3194, 2013
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This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated Circuit (ASIC) to generate Piecewise-Affine (PWA) functions. A Generic PWA form (PWAG) has been selected for integration, because of its suitability to implement any PWA function without resorting to approximation. The design of the ASIC in a 90 nm TSMC technology, its integration, test and characterization through different examples are detailed in the paper. Furthermore, the ASIC verification using an ASIC-in-the-loop methodology for embedded control applications is presented. To assess the characteristics of this verification, the double-integrator, a usual control application example has been considered. Experimental results validate the proposed architecture and the ASIC implementation.
An event-driven multi-kernel convolution processor module for event-driven vision sensors
L. Camuñas-Mesa, C. Zamarreño-Ramos, A. Linares-Barranco, A.J. Acosta-Jiménez, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 47, no. 2, pp 504-517, 2012
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Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) is not capturing a sequence of still frames, as in conventional video and computer vision systems. In Event-Driven sensors each pixel autonomously and asynchronously decides when to send its address out. This way, the sensor output is a continuous stream of address events representing reality dynamically continuously and without constraining to frames. In this paper we present an Event-Driven Convolution Module for computing 2D convolutions on such event streams. The Convolution Module has been designed to assemble many of them for building modular and hierarchical Convolutional Neural Networks for robust shape and pose invariant object recognition. The Convolution Module has multi-kernel capability. This is, it will select the convolution kernel depending on the origin of the event. A proof-of-concept test prototype has been fabricated in a 0.35 mu m CMOS process and extensive experimental results are provided. The Convolution Processor has also been combined with an Event-Driven Dynamic Vision Sensor (DVS) for high-speed recognition examples. The chip can discriminate propellers rotating at 2 k revolutions per second, detect symbols on a 52 card deck when browsing all cards in 410 ms, or detect and follow the center of a phosphor oscilloscope trace rotating at 5 KHz.
A 32x32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 Meps throughput
L. Camuñas-Mesa, A. Acosta-Jiménez, C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 58, no. 4, pp 777-790, 2011
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This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free event-based vision, information is represented by a continuous flow of self-timed asynchronous events. Such events can be processed on the fly by event-based convolution chips, providing at their output a continuous event flow representing the 2-D filtered version of the input flow. In this paper we present a 32 x 32 pixel 2-D convolution event processor whose kernel can have arbitrary shape and size up to 32 x 32. Arrays of such chips can be assembled to process larger pixel arrays. Event latency between input and output event flows can be as low as 155 ns. Input event throughput can reach 20 Meps (mega events per second), and output peak event rate can reach 45 Meps. The chip can be configured to discriminate between two simulated propeller-like shapes rotating simultaneously in the field of view at a speed as high as 9400 rps (revolutions per second). Achieving this with a frame-constraint system would require a sensing and processing capability of about 100 K frames per second. The prototype chip has been built in 0.35 mu m CMOS technology, occupies 4.3 x 5.4 mm(2) and consumes a peak power of 200 mW at maximum kernel size at maximum input event rate.
CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking
R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, L. Camuñas-Mesa, R. Berner, M. Rivas-Pérez, T. Delbrueck, S.C. Liu, R. Douglas, P. Hafliger, G. Jiménez-Moreno, A. Civit-Ballcels, T. Serrano-Gotarredona, A.J. Acosta-Jiménez and B. Linares-Barranco
Journal Paper · IEEE Transactions on Neural Networks, vol. 20, no. 9, pp 1417-1438, 2009
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This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies.
On real-time AER 2-D convolutions hardware for neuromorphic spike-based cortical processing
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez, C. Serrano-Gotarredona, J.A. Pérez-Carrasco, B. Linares-Barranco, A. Linares-Barranco, G. Jiménez-Moreno and A. Civit-Ballcels
Journal Paper · IEEE Transactions on Neural Networks, vol. 19, no. 7, pp 1196-1219, 2008
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In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address-event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16 x 16 has been implemented with programmable kernel size of up to 16 x 16. The chip has been fabricated in a standard 0.35-mu m complimentary metal-oxide-semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog-digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.
A neuromorphic cortical-layer microchip for spike-based event processing vision systems
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez and B. Linares Barranco
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 53, no. 12, pp 2548-2566, 2006
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We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 x 32 pixels. The convolution processor operates on a pixel array of size 32 x 32, but can process an input space of up to 128 x 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second.
Selective Clock-Gating for Low-Power Synchronous Counters
P. Parra, A.J. Acosta, R. Jiménez and M. Valencia
Journal Paper · Journal of Low Power Electronics, vol. 1, no. 1, pp 11-19, 2005
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With current technologies and applications, dynamic power reduction is of great technological interest. The objective of this paper is to explore the applicability of clock gating techniques to counters in order to reduce the power consumption as well as to compare different power figures in counting structures. Counters are widely used in current VLSI digital circuits, and optimized low-power versions of them are of important concern. Different ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits with different synchronization schemes. The correct selection of bits where clock gating is applied and the suitable composition of groups of bits are essential but are not straightforward when applying this technique. We have found that some specific groupings of bits are the best options when applying clock gating to reduce power consumption.
High-performance edge-triggered flip-flops using weak-branch differential latch
R. Jiménez, P. Parra, P. Sanmartín and A.J. Acosta
Journal Paper · Electronics Letters, vol. 38, no. 21, pp 1243-1244, 2002
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doi
A new technique to build edge-triggered flip-flops based on the use of 'weak' transistors is presented. This technique can be applied to most CMOS differential latches with only some further design considerations. Despite of hardware costs, resulting flip-flops are very suited for high-performance and low-noise applications.
Analysis of high-performance flip-flops for submicron mixed-signal applications
R. Jiménez, P. Parra, P. Sanmartín and A.J. Acosta
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 145-156, 2002
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This paper presents a detailed analysis of high-performance edge-triggered memory elements for deep submicron mixed-signal applications. The variations of the main parameters (power, delay, peak of supply current) with supply voltage, as well as timing restrictions have been studied. Especial emphasis has been given to switching-noise generation, an aspect of important concern in mixed-signal applications. We have analyzed the sources of switching noise, noticing that, the less noisy flip-flops are those based on differential structures.
VHDL behavioural modelling of pipeline analog to digital converters
A.J. Acosta, E. Peralias, A. Rueda and J.L. Huertas
Journal Paper · Measurement, vol. 31, no. 1, pp 47-60, 2002
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This paper describes a VHDL implementation of a behavioural model for pipeline analog to digital converters (ADCs). The goal is using this VHDL description to facilitate the synthesis of the digital part, which in our example includes digital correction, digital calibration, and control of the ADC testing modes. Among other aspects of general interest, we will show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. As an application example, an ADC of 10-bits and 10 MSamples/s has been modelled and simulated. Results front these high level simulations carried out using QuickHDL in Mentor Graphics are compared with those obtained experimentally from a silicon prototype, validating the suitability of the model. (C) 2002 Elsevier Science Ltd. All rights reserved.
Congresos
Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
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doi
This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.
Review of Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA
F.E. Potestad-Ordoñez, E. Tena-Sánchez, C. Fernández-García, V. Zúñiga-González, J.M. Mora Gutiérrez, C. Baena-Oliva, P. Parra-Fernández, A.J. Acosta-Jiménez and C.J. Jiménez-Fernández
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen
In this paper, we present a review of the work [1]. In this work a complete setup to break ASIC implementations of standard Trivium stream cipher was presented. The setup allows to recover the secret keys combining the use of the active noninvasive technique attack of clock manipulation and Differential Fault Analysis (DFA) cryptanalysis. The attack system is able to inject transient faults into the Trivium in a clock cycle and sample the faulty output. Then, the internal state of the Trivium is recovered using the DFA cryptanalysis through the comparison between the correct and the faulty outputs. The secret key of the Trivium were recovered experimentally in 100% of the attempts, considering a real scenario and minimum assumptions.
[1] F.E. Potestad-Ordoñez, M. Valencia-Barrero, C. Baena-Oliva, P. Parra-Fernández, C.J. Jiménez-Fernández, "Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA". In Sensors, vol. 20, num. 6909, pp. 1-19, 2020.
Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
E. Tena-Sánchez, F.E. Potestad-Ordoñez, V. Zúñiga-González, C. Fernández-García, J.M. Mora Gutiérrez, C.J. Jiménez-Fernández and A.J. Acosta-Jiménez
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen
In this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of proposals have been presented to design circuits resistant to Power Analysis attacks. In this paper a deep review of the state of the art of gate-level countermeasures against Power Analysis attacks has been done, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison.
[1] E. Tena-Sánchez, F.E. Potestad-Ordoñez, C.J. Jiménez-Fernández, A.J. Acosta and R. Chaves, "Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks," Applied Sciences, 12(5), 2390, 2022.
Adaptación de prácticas de laboratorios de Electrónica y Automatización a una modalidad semipresencial
E. Tena-Sánchez, F.E. Potestad-Ordóñez, M. Valencia-Barrero, A.J. Acosta and C.J. Jiménez-Fernández
Conference · Congreso Universitario de Innovación Educativa en las Enseñanzas Técnicas CUIEET 2021
resumen
En el curso 20/21, debido a la situación de pandemia mundial, tanto las clases teóricas como las prácticas sufrieron importantes cambios, además de los que se seguirán adoptando en próximos años. En este trabajo se exponen los problemas observados en las clases de laboratorio, más concretamente en la adecuación de los laboratorios de electrónica y automatización, donde el equipamiento y la capacidad ya eran limitados y se han agravado drásticamente por el problema de no poder juntar dos alumnos por puesto. Esto implica dividir el grupo en subgrupos, y plantear nuevos modelos didácticos adaptados a esta situación.
Hamming-Code Based Fault Detection Design Methodology for Block Ciphers
F E. Potestad-Ordóñez, E. Tena-Sánchez, R. Chaves, M. Valencia-Barrero, A.J. Acosta-Jiménez and C.J. Jiménez-Fernández
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
resumen
Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to minimize this type of vulnerabilities, several mechanisms have been proposed to detect this type of attacks. However, these mechanisms can have a significant cost or not adequately cover the implementations against fault attacks. In this paper a novel approach is proposed, consisting in generating the signatures of the internal state using a Hamming code. This allows to cover a larger amount of faults allowing to detect even or odd bit changes, as well as multi-bit and multi-byte changes, the ones that make ciphers more vulnerable to DFA attacks. As case of study, this approach has been applied to the Advanced Encryption Standard (AES) block cipher implemented on FPGA using T-boxes. The results suggest a higher fault coverage with an overhead of 16% of resource consumption and without any penalty in the frequency degradation.
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
E. Tena-Sánchez, I.M. Delgado-Lozano, J. Nuñez and A.J. Acosta
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2018
resumen
The design of cryptographic circuits is requiring greater performance restrictions due to the constrained environments for IoT applications in which they are included. Focusing on the countermeasures based on dual-precharge logic styles, power, area and delay penalties are some of their major drawbacks when compared to their static CMOS single-ended counterparts. In this paper, we propose a initial study where scaled CMOS technnology and FinFET emerging technology are considered to foresee the relationship between ultra low power consumption, reduced delay, and security. As demonstration vehicle, we measure the performance and the security level achieved by different Substitution Boxes, implemented in different technologies. As main results, nanometer CMOS technologies maintains considerable security levels at reasonable power and delay figures, while FinFETs outperform CMOS in power and delay reduction, but with a non negligible degradation in security.
Effect of temperature variation in experimental DPA and DEMA attacks
E. Tena-Sánchez and A.J. Acosta
Conference · Int. Symposium on Power and Timing Modeling, Optimization and Simulation PATMOS 2018
resumen
Side-Channels attacks are usually performed to measure the vulnerability of cryptocircuits against malicious attacks. The conditions in which the attacks are carried out have influence in their effectivity. In this sense, temperature variations should be considered to assess the complete vulnerability of a system, but they have not been deeply considered in the literature. For this purpose, experimental DPA and DEMA attacks are carried out over one of the widest used and studied block cipher, namely AES algorithm, implemented in a Spartan-6 FPGA. The effectivity of DPA and DEMA attacks under different temperatures: 10, 25, 50 and 70°C have been studied experimentally. The attacks have been made over the 128 bits of two randomly chosen keys. The security achieved for each attack is measured using the Measurements to Disclose (MTD) the key, which determines the minimum number of patterns needed to retrieve the secret key. From the results we can obtain interesting conclusions: DPA attack is more effective than the DEMA attack over the AES implementation on FPGA. On the other hand, we conclude that the key has influence on the MTD value, but the variability between keys is of the same magnitude as the variability between temperatures, meaning that temperature variation is not a decisive factor in the effectiveness of an attack.
Emerging Design Challenges for Complex SoCs
A. Acosta
Conference · International Verification and Security Workshop IVSW 2017
resumen
The increasing demand for electronic systems with increasing bandwidth and decreasing size puts more high-speed circuitry and high bandwidth channels in ever-closer proximity. System-on-a-chip (SoC) integration places complex high speed digital circuitry, analog and RF blocks very closely together. Note that most EDA tools are geared for a specific design type (digital, analog, RF, etc.) However, there are many challenges caused by the interaction across various blocks. These challenges are not limited by the boundaries or types of the various design components, or by the types of analyses that designers are used to regularly run on less complex homogenous designs. Most notable among these interdisciplinary mixed signal SOC challenges include:
- Verification of behavioral and electrical correctness.
- Security verification.
- Electromagnetic Crosstalk interference analysis and signoff.
Mesa Redonda 'Medicina del Futuro'
A.J. Acosta-Jiménez
Conference · I Congreso de Medicina y Ciencias Biomédicas, 2017
resumen
Abstract not avaliable
Experiencia de puesta en marcha y desarrollo de un Máster on-line en Microelectrónica
A.J. Acosta, A. Barriga, B. Pérez and J.L. Huertas
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
resumen
Desde octubre de 2008 la Universidad de Sevilla oferta el título oficial de ‘Máster Universitario en Microelectrónica, Diseño y Aplicaciones de Sistemas Micro/nanométricos’. Dicho máster tiene, como característica diferenciadora respecto a la práctica totalidad de cursos similares existentes, la peculiaridad de ser impartido on-line. En su momento de aparición fue una auténtica novedad, que supuso un extraordinario reto, tanto en su puesta en marcha como en su desarrollo día a día, ya que aúna las características y problemática de realizar a la vez docencia a distancia y de contenido técnico muy especializado. Esta comunicación describe las características y la experiencia de puesta en marcha y desarrollo de un título exitoso en esta área.
Vulnerability Evaluation and Secure Design Methodology of Cryptohardware for ASIC-embedded Secure Applications to Prevent Side-Channel Attacks
E. Tena-Sánchez, I. Durán, S. Canas and A. J. Acosta
Conference · Workshop on Trustworthy Manufacturing and Utilization of Secure Devices TRUDEVICE 2016
resumen
This poster presents the state of the art in the research performed by our group in designing and testing cryptohardware for ASIC-embedded secure applications. Implementations of both block-ciphers (Kasumi-Sbox9, AES-128) and stream-ciphers (Trivium) are explored at a circuit and transistor level, to increase their security figures. Analysis of vulnerability is made via Correlation Power Analysis (CPA) attacks, by implementing Correlation Electromagnetic Analysis attacks (CEMA), and using t-test leakage detection analysis, which are made at simulation and experimental level
A low-cost FPGA-based platform to perform fast Power/Electromagnetic Attacks on cryptographic circuits
S. Canas, E. Tena-Sánchez and A.J. Acosta
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
resumen
In this paper, we propose a general purpose low-cost FPGA-based platform to acquire traces faster than a high performance logic analyzer from any kind of cryptographic device in order to use them to perform Power Analysis (PA) and Electromagnetic Analysis (EMA) attacks. The proposed platform can be easily customized to capture traces from any cryptocircuit to attack it, removing pattern generators (like expensive logic analyzers) to produce test patterns. We have tested and verified the functionality, speed and improvement over a logic analyzer-based setup measuring the power and electromagnetic traces to be used in a PA or EMA attack over an ASIC with an implementation of Trivium stream cipher and over a SBOX-9 (Kasumi) FPGA implementation. In the case of Trivium(ASIC implementation), the time needed to generate input patterns is reduced to 5% of the total time of measurement, being 4% for the SBOX-9 (FPGA implementation). The measurement time is compared to existing instrument-based alternatives.
Secure Cryptographic Hardware Implementation Issues for High-Performance Applications
E. Tena-Sánchez, A.J. Acosta and J. Nuñez
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2016
resumen
In this paper the effect of high-performance techniques for high speed applications in secure cryptographic implementations is studied. The use of dual precharge logic styles with fine-grained pipelining with an overlapping three-phase clock scheme is studied, also including a correct distribution of the clock signal in the cryptographic implementation. To make this study, four different implementations of the Sbox-9 of the Kasumi algorithm have been implemented using an 90nm TSMC technology. Simulation-based DPA attacks have been carried out, showing how the proper synchronization of data signals gives better results in terms of power consumption and operating frequency, but affects negatively the security against side channel attacks, decreasing the number of input patterns needed to disclosure the secret key.
Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers
E. Tena and A. Acosta
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
resumen
Trivium is a hardware oriented stream cipher finalist of the eSTREAM project. In this work, an optimized Differential Power Analysis (DPA) attack on Trivium using correlation shape distinguishers is presented. Unlike in the previous reported attacks, we are able to retrieve the whole 80-bit key without making any hypothesis during the attack using the proposed method. The theoretical vulnerability analysis is presented and then checked developing a simulation-based DPA attack on a standard CMOS Trivium implementation in a 90nm TSMC technology. The results show that our simulation-based attack is successful for random keys, improving the previously-reported attacks at least in 91.25% in terms of number of patterns needed to recover the key.
Design and Characterization of Cryptohardware for ASIC-embedded Secure Applications to Prevent Power Analysis Attacks
E. Tena-Sánchez and A.J. Acosta
Conference · Workshop on Cryptographic Hardware and Embedded Systems CHES 2015
resumen
Information leakaged by cryptosystems can be used to reveal critical information using Side Channel Attacks. Differential Power Analysis (DPA) uses the power consumption dependence on the processed data to reveal the secret key. Countermeasures against DPA.
DPA Vulnerability Analysis on Trivium Stream Cipher using an Optimized Power Model
E. Tena-Sánchez and A.J. Acosta
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2015
resumen
In this paper, a Differential Power Analysis (DPA) vulnerability analysis on Trivium stream cipher is presented. Compared to the two previously presented DPA attacks on Trivium, we retrieve the whole key without making any hypothesis during the attack. An optimized power model is proposed allowing the power trace acquisition without making any algorithmic noise removement thus simplifying the attack strategy considerably. The theoretical vulnerability analysis is presented and then checked developing a simulation-based DPA attack on a standard CMOS Trivium implementation in a 90nm TSMC technology. The results show that our attack is successful for random keys, saving in computer resources and time respecting to previously reported attacks. The attack is independent on technology used for the implementation of Trivium and can be used to measure the security of novel Trivium implementations.
Programmable ASICs for Model Predictive Control
M.C. Martínez-Rodríguez, P. Brox, E. Tena, A.J. Acosta and I. Baturone
Conference · IEEE International Conference on Industrial Technology ICIT 2015
resumen
Two configurable and programmable ASICs that implement piecewise-affine (PWA) functions have been designed in TSMC 90-nm technology in response to industry demands for embedded, fast response time, and low power solutions for Model Predictive Control (MPC). An automated model-based design flow can extract the parameters necessary for the configuration and the programming of both ASICs. Two application examples in the automotive field illustrate the design flow and the behavior of the ASICs.
Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications
E. Tena-Sánchez, J. Castro and A. Acosta
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2014
resumen
In this paper, the design of a XOR/XNOR gate for low-power cryptographic applications is presented. The proposed gate optimizes the SABL (Sense Amplifier Based Logic) gate, widely used in cryptocircuit implementations, by removing residual charge in the pull-down circuit and simplifying the pull-up. The resulting gate improves SABL in terms of area, power consumption, propagation delay and resilience against Differential Power Analysis (DPA) attacks. To demonstrate the gain in performances, both gates have been designed, physically implemented and experimentally characterized, in a 90nm TSMC technology. Experimental results show a reduction of 15% in area, 12% in power consumption, and 40% in delay in the proposed gate. To demonstrate the gain in security of the proposal, simulation-based DPA attacks have been performed on respective Kasumi Sbox9 implementations, being our proposal suitable for inmediate application in high-performance secure cryptographic applications.
Low-Power Differential Logic Gates for DPA Resistant Circuits
E. Tena-Sanchez, J. Castro and A.J. Acosta
Conference · Euromicro Conference on Digital System Design DSD 2014
resumen
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Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is a SCA that uses the power consumption dependence on the processed data. Designers widely use differential logic styles with constant power consumption to protect devices against DPA. However, the right use of such circuits needs a fully symmetric structure and layout, and to remove any memory effect that could leak information. In this paper we propose improved low-power gates that provide excellent results against DPA attacks. Simulation based DPA attacks on Sbox9 are used to validate the effectiveness of the proposals.
Automatic and Systematic Test Toolset for Digital ASICs
E. Tena-Sánchez, J. Castro-Ramirez and A.J. Acosta-Jimenez
Conference · Conference on the Design of Circuits and Integrated Systems DCIS 2013
resumen
Abstract not available
Automatic and Systematic Control of Experimental Data Measurements on ASICs
E. Tena, J. Castro and A.J. Acosta
Conference · Symposium IMEKO TC 4 Symposium and IWADC Workshop 2013
resumen
This paper presents a methodology to perform automatic and systematic characterization test on application specific integrated circuits (ASICs). The proposed methodology is based on the automatic control of all laboratory equipment and the data processing with Matlab. The ASIC, or integrated system, is connected to controllable test equipment to generate patterns and collect the output data provided by the ASIC. The methodology that provides the Matlab script controlling the equipment, test process, making the analysis of the results and supervising the whole process, can be easily adapted to different experiments and ASIC features. The test of a piecewise affine (PWA) ASIC controller has been used to experimentally prove the automatic control in both open-loop as well as in closed-loop configurations, reducing the risk of manual measurement errors.
ASIC-in-the-loop methodology for verification of piecewise affine controllers
M. Martínez-Rodríguez, P. Brox, J. Castro, E. Tena, A. Acosta and I. Baturone
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
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This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations.
Using physical unclonable functions for hardware authentication: a survey
S. Eiroa, I. Baturone, A.J. Acosta and J. Dávila
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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Physical unclonable functions (PUFs) are drawing a crescent interest in hardware oriented security due to their special characteristics of simplicity and safety. However, their nature as well as early stage of study makes them constitute currently a diverse and non-standardized set for designers. This work tries to establish one organization of existing PUF structures, giving guidelines for their choice, conditioning, and adaptation depending on the target application. In particular, it is described how using PUFs adequately could enlighten significantly most of the security primitives, making them very suitable for authenticating constrained resource platforms.
Revisting clock-gating: the common place for power reduction
J. Castro, P. Parra and A.J. Acosta
Conference · Iberchip XVI Workshop IWS 2010
resumen
Abstract not avaliable
Master-slave flip-flop optimization for fine-grained clock-gating applications
J. Castro, P. Parra and A.J. Acosta
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2010
resumen
Abstract not avaliable
An improved differential pull-down network logic configuration for DPA resistant circuits
J. Castro, P. Parra and A.J. Acosta
Conference · International Conference on Microelectronics ICM 2010
resumen
Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with constant power dissipation have been widely used. However, the right use of such circuits for secure applications needs not only a fully symmetric structure, but also removing any memory effect that could leak information. We propose an improved memory-less fully symmetric Xor/Xnor pull-down logic configuration, to be used with any differential technique, for immediate application in cryptographic secure applications.
Optimization of clock-gating structures for low-leakage high-performance applications
J. Castro, P. Parra and A.J. Acosta
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2010
resumen
Clock Gating (CG) is a well known technique to reduce dynamic power consumption by stopping the clock to avoid unnecessary transitions in synchronous circuits. The abilities of different CG-styles to save power at a flip-flop level, depending on the input activity, are analysed in this paper. Also, since conventional CG techniques usually do not take into account leakage power, some optimization procedures and guidelines are presented for leakage reduction. Focusing on those structures that do not need a latch to remove undesired transitions in gated clock, a leakage value of a fourth of the original one is achieved without degradation in timing performances.
improved AER convolution chip for vision processing with higher resolution and new functionalities
L.A. Camuñas-Mesa, A. Linares-Barranco, A. Acosta, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2009
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We present a new neuromorphic fully digital convolution
microchip for Address Event Representation (AER)
spike-based processing system. This chip computes 2-D
convolutions with a programmable kernel in real time.
Previously, we designed and tested another convolution
chip with a size of 32 x 32 pixels [1] and, based on the
information obtained from this test, we have designed a
new chip with larger resolution (64 x 64 pixels),
improved behavior and new functionalities included.
This chip receives and generates data in AER format,
which is an asynchronous protocol, implementing the
convolution of the input images with a programmable
kernel. The most important new functionality included in
this chip is the multikernel capability, which allows us to
program several kernels (up to 32) so that each input
event will be processed with the corresponding kernel,
depending on the origin of the input event. The paper
describes the architecture of the chip, with special
emphasis to the new improvements.
Switching noise optimization in the wake-up phase of leakage-aware power gating structures
J. Castro, P. Parra and A.J. Acosta
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2009
resumen
Leakage power dissipation has become a critical issue in advanced process technologies. The use of techniques to reduce leakage power consumption with negligible degradation in performances is needed for current and next technologies. Power gating is an effective technique to reduce leakage, taking advantage of the transistor stacking effect. However, the restoration from standby mode in power-gated circuits usually introduces a large amount of switching noise on the power supply and ground networks, that may affect the normal operation of circuits connected to the same polarizations. This paper analyzes the switching noise generated in the wake-up phase by several power-gating techniques, and their influence on the wake-up time. The best results are for the techniques that redistribute the amount of current flowing through the Vdd and Gnd nodes during the wake-up transition. Simulation results obtained on basic digital cells in a 90 nm technology show a variation of two in switching noise, while maintaining the same wake-up time and leakage saving
A 2.5MHz bandpass active complex filter with 2.4MHz bandwidth for wireless communications
A. Villegas, R. Bianca, A. Ginés, R. Doldán, M.A. Jalón, A.J. Acosta, E. Peralías, D. Vázquez and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2008
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This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The filter compliants with the requirements of the IEEE802.15.4 standard. Simulation results including mismatching and process variations over the extracted view of the circuit are shown. The filter has a nominal gain of 12dB, good selectivity (20dB@2MHz offset), high image rejection (51dB nominal) and low power consumption (3.6mA @2.5V).
La simulación eléctrica en el trabajo académicamente dirigido como vehículo docente para la enseñanza de la electrónica
A.J. Acosta, R. del Río and A. Rodríguez-Vázquez
Conference · VIII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2008
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La Electrónica es una disciplina versátil en cuanto a las metodologías y técnicas docentes que pueden emplearse. Frente a las clases magistrales, experiencias de cátedra, tutorías y clases prácticas, el Trabajo Académicamente Dirigido (TAD) se muestra como altamente eficiente a la hora de trasvasar conocimiento al alumno. En esta comunicación se pone de manifiesto la experiencia de innovación docente puesta en funcionamiento en la Licenciatura en Física de la Universidad de Sevilla y que opera satisfactoriamente desde el curso 2002/03.
Geometry optimization in basic CMOS cells for improved power, leakage, and noise performances
J. Castro, A.J. Acosta and M. Vesterbacka
Conference · International Conference on Advances in Electronics and Micro-electronics ENICS 2008
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The rising demand for portable system is increasing the importance of low power as a design consideration. In this sense, leakage power is increasing much faster than dynamic power at smaller dimensions. Peak values of supply current are related to noise injected into the substrate and/or propagated through supply network, limiting the performances of the sensitive analog and RF portions of mixed-signal circuits. This paper analyses how these three aspects, dynamic power, leakage power and peak power, can be considered together, optimizing the sizing and design of basic cells, with a reduced degradation in performances. The suited sizing of basic cells, show the benefits of the proposed technique, validated through simulation results on 130 nm nand, nor and inverter cells. © 2008 IEEE.
Fully digital AER convolution chip for vision processing
L. Camuñas-Mesa, A. Acosta-Jiménez, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2008
resumen
We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It operates on a pixel array of size 32 x 32, and the kernel is programmable and can be of arbitrary shape and size up to 32 x 32 pixels. The chip receives and generates data in AER format, which is asynchronous and digital. The paper describes the architecture of the chip, the test setup, and experimental results obtained from a fabricated prototype. ©2008 IEEE.
A 1.2V 5.14 mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4 GHz ZigBee applications
A.J. Ginés, R. Doldán, A. Villegas, A.J. Acosta, M.A Jalón, D. Vázquez, A. Rueda and E. Peralías
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
resumen
A low-cost 1.2V 5.14mW phase-lock loop (PLL) quadrature frequency synthesizer compliant with the 2.4GHz ZigBee standard (IEEE 802.15.4) has been implemented in 90nm CNIOS technology. In-phase and quadrature (I/Q) components exhibit a phase noise of-105.9dBc/Hz at 1MHz offset from the carrier. The PLL die area including decoupling capacitors and testing buffers is 209x422 mu m(2).
Image Processing Architecture Based on a Fully Digital Aer Convolution Chip
L.A. Camuñas-Mesa, A.J. Acosta-Jimenez, T. Serrano-Gotarredona, B. Linares-Barranco and R. Serrano Gotarredona
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2007
resumen
Abstract not avaliable
Asynchronous staggered set/reset techniques for low-noise applications
R. Rimolo-Donadio, A.J. Acosta and W. Krautschneider
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2007
resumen
This work proposes the usage of staggered initialization schemes in digital sequential circuits as complementary technique to reduce the simultaneous switching activity, pursuing the minimization of switching noise levels. Simultaneous switching noise (SSN) generation has been evaluated in digital sequential circuits during initialization and a general synthesis methodology has been proposed in order to implement the staggered initialization schemes at system level. The evaluation of this methodology was made with counter arrays using 0.35um AMS library cells. In addition, timing considerations, clock suppression during initialization cycles, and the type of cell chosen to implement the staggered distribution are discussed. Main results include noise reduction levels, by suppression of power supply fluctuations, up to 66.7% in post-layout simulations when using staggered techniques enhanced with clock gating during initialization. © 2007 IEEE.
A switching noise vision of the optimization techniques for low-power synthesis
J. Castro, P. Parra, M. Valencia and A.J. Acosta
Conference · European Conference on Circuit Theory and Design ECCTD 2007
resumen
Different techniques used by a CAD tool that automatically optimize power consumption at gate-level circuit have been investigated in terms of switching noise generation. Such techniques, clock-gating, sleep-mode and others at a gate-level are usual saving power techniques, but are rarely applied to switching noise reduction. The reduction of peaks in supply current is of great interest due to their impact in sensitive parts of a circuit. An estimation of these peaks has been done at a gate level by two different tools (PrimePower and NanoSim, both from Synopsys) providing both the power supply current waveform along time, the average and the peak power for different synthesized circuits to check the effectiveness of such low-power techniques for switching noise reduction. As conclusions, although both tools provide an estimation of peak power, only NanoSim gives accurate values, and how these optimization techniques for low-power are, in general, useful for switching noise reduction.
Spike events processing for vision systems
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez, A. Linares-Barranco, G. Jiménez-Moreno, A. Civit-Balcells and B. Linares-Barranco
Conference · International Symposium on Circuits and Systems ISCAS 2007
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In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured cortical-like layers for sophisticated processing. The paper includes a few examples that have demonstrated the potential of this technology for highspeed vision processing, such as a multilayer event processing network of 5 sequential cortical-like layers, and a recognition system capable of discriminating propellers of different shape rotating at 5000 revolutions per second (300000 revolutions per minute).
Asymmetric clock driver for improved power and noise performances
J. Castro, P. Parra, M. Valencia and A.J. Acosta
Conference · International Symposium on Circuits and Systems ISCAS 2007
resumen
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an important solution to reduce the switching noise generated by the global clock, with a very reduced degradation in performances and reliability. The suited sizing of clock generators and the design of asymmetric clock tree cells, show the benefits of the proposed technique, validated through a design example where a 50% of noise reduction is achieved with 10% of loss in operation frequency and no penalty, even saving, in power consumption.
Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits
A.J. Acosta, J.M. Mora, J. Castro and P. Parra
Conference · Conference on VLSI Circuits and Systems III, 2007
resumen
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The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the signal on the wire, as propagation delay, signal integrity, transition time, among others. The power concerns related to buffering have also received much attention, because of the low power requirements of modem integrated systems. In the same way, the buffer insertion has strong impact on the reliability of synchronous systems, since the suited distribution of clock requires reduced or controlled clock-skew, being the buffer and wire sizing, a crucial aspect. In a different way, buffer insertion has been also used to reduce noise generation, especially in heavily loaded nets, since the inclusion of buffers help to desynchronize signal transitions. However, the inclusion of buffers of inverters to improve one or more of these characteristics have often negative effect on another parameters, as it happens in the average and peak of supply current. Mainly, the inclusion of a buffer to reduce noise (peak power), via desynchronizing transitions, could introduce more dynamic consumption, but reducing the short-circuit current because of the increment of signal slope. Thus, the average/peak current optimization can be considered a design trade-off. In this paper, the mechanism to obtain an average/peak power optimization procedure are presented. Selected examples show the feasibility of minimizing switching noise with negligible impact on average power consumption.
A methodology for switching noise estimation at gate level
J. Castro, P. Parra and A.J. Acosta
Conference · Conference on VLSI Circuits and Systems III, 2007
resumen
This paper provides a simple methodology, based on available CAD tools, able of extracting valuable information on supply current curves, otherwise limited by the layout disposal, making it impracticable for the present high density circuits. The approach starts at HDL level, which will be automatically synthesized to a gate level being the peak power (one peak per clock cycle) measured at this level, giving an idea of the switching noise generated. Although an indirect method, it provides a quantitative value of noise valid for comparison between different proposals. To assess the methodology two different tools are used: PrimePower and NanoSim, both from Synopsys, that generate an average power and a peak power value. We will see that NanoSim is good for noise estimation but this is not the case of PrimePower.
A bio-inspired event-based real-time image processor
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A.J. Acosta-Jiménez, B. Linares-Barranco and L.A. Camuñas-Mesa
Conference · IEEE RAS-EMBS International Conference on Biomedical Robotics and Biomechatronics BioRob 2006
resumen
AER (Address Event Representation) is an emergent bio-inspired protocol intended to communicate chips containing many processing units, called them neurons or pixels. It exploits the advantages of communicating the activation state of a neuron as pulses, as done in the human brain. The information is sent out sorted beginning with the most relevant. This feature together with the parallel processing of the information allows for performing very fast image processing. In this paper, we explain how AER is suitable for real-time image processing and, as an example, we present results from some AER-based convolution chips which is able to perform convolutions in real time.
High-speed image processing with AER-based components
R. Serrano-Gotarredona, B. Linares-Barranco, T. Serrano-Gotarredona, A.J. Acosta-Jiménez, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, G. Jiménez-Moreno and A. Civit-Ballcels
Conference · International Symposium on Circuits and Systems ISCAS 2006
resumen
A high speed sample image processing application using AER-based components is presented. The setup objective is to distinguish between two propellers of different shape rotating at high speed (around 1000 revolutions /see) to show event-based systems capabilities in high speed applications. Event-based schemes allow the most relevant information to propagate faster through the system layers. So image processing is sped up because a rough result may be available when only a little part of the input has arrived. This setup is much faster than the conventional frame-based image processing systems because they would need to proccess more than 10kFrames/s to do the same task proposed here, whereas only few events are required with the event based technique.
An arbitrary kernel convolution AER-transceiver chip for real-time image filtering
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A.J. Acosta-Jiménez and B. Linares-Barranco
Conference · International Symposium on Circuits and Systems ISCAS 2006
resumen
A new chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. This is a first prototype of reduced size (16x16 pixels) to validate system level techniques. It has been fabricated in AMS-0.35 mu n, 2-poly, 3-metal technology. Chip inputs and outputs are coded using Address Event Representation (AER). This is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of pixels located on different chips. Pixels generate 'events' according to their activity levels. More active pixels generate more events per unit time and access the interchip communication channel more frequently, whereas pixels with low activity consume less communication bandwidth. This allows to communicate more relevant information in a very short time. Specific PCI boards have been developed to feed images into the chip and to read images out of it.
Optimization of master-slave flip-flops for high-performance applications
R. Jiménez, P. Parra, J. Castro, M. Sánchez and A. Acosta
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2006
resumen
The design of high-performance master-slave flip-flops is of crucial importance in modem VLSI. The optimization of existing structures is necessary when the requirements of the flip-flop is for low-power, high-speed or low-noise applications. In this work, the optimization via transistor sizing of a well-known master-slave flip-flop is investigated. A detailed analysis of the flip-flop structure provides information useful for optimization, giving an optimum solution for an specific high-performance application.
A Programmable Convolution Chip Prototype for Real-Time Image Filtering
R. Serrano-Gotarredona, M.T. Serrano-Gotarredona, A.J. Acosta-Jimenez, B. Linares-Barranco, C. Serrano-Gotarredona, et. al
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
resumen
Abstract not available
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, H. Kolle-Riis, T. Delbrück, S.C. Liu, S. Zahnd, A.M. Whatley, R. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez and B. Linares-Barranco
Conference · Neural Information Processing Systems Conference NIPS 2005
resumen
A 5-layer neuromorphic vision processor whose components
communicate spike events asychronously using the address-eventrepresentation
(AER) is demonstrated. The system includes a retina
chip, two convolution chips, a 2D winner-take-all chip, a delay line
chip, a learning classifier chip, and a set of PCBs for computer
interfacing and address space remappings. The components use a
mixture of analog and digital computation and will learn to classify
trajectories of a moving object. A complete experimental setup and
measurements results are shown.
On Fully Digital Address-Event-Representation Convolution Processing
L. Camuñas-Mesa, A.J. Acosta-Jimenez, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
resumen
Abstract not avaliable
Performance analysis of full adders in CMOS technologies
J. Castro, P. Parra and A.J. Acosta
Conference · Conference on VLSI Circuits and Systems II, 2005
resumen
Full adders are one of the most important building blocks in VLSI digital arithmetic. The area, electrical, timing, power consumed and noise generated characteristics of this cell are strongly dependent on the design technique. An exhaustive work taking into account the above parameters is done, and that complete analysis will be of utility for the community of digital designers. Emphasis will be done in power/noise figures, of most important concern in current CMOS mixed-signal design. The full adders considered are those using complementary CMOS, pass-transistor logic, double pass-transistor logic, and two versions based on CMOS transmission gate. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 mu m CMOS technology. The main results obtained are on one hand, the selection of a logic family for a specific application and, on the other hand, the selection of a specific full adder structure for an optimized parameter option -power, noise or speed.
Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
P. Parra, J. Castro, M. Valencia and A.J. Acosta
Conference · VLSI Circuits and Systems II, 2005
resumen
One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry, meaning that memory elements are the main source of noise in digital circuits. This paper faces the application of clock-gating, a well known low-power technique, to the reduction of switching-noise generation. Sources of switching noise in master-slave flip-flops will be analyzed. It will be shown how different solutions for the clock-gated logic show very different results regarding switching-noise generation. Illustrative examples characterized through HSPICE simulations, as well as the application of clock-gating to 16-bit synchronous counter as demonstrator, will provide useful design guidelines for reduction of switching noise generation.
A digital pixel cell for address event representation image convolution processing
L. Camuñas-Mesa, A. Acosta-Jiménez, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · Conference on Bioengineered and Bioinspired Systems II, 2005
resumen
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of vaRíous type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.
Experimental Characterization of an Integrated Chaos-Based FM-DCSK Transmitter Chipset
M. Delgado-Restituto, A.J. Acosta-Jimenez and A. Rodriguez Vazquez
Conference · Experimental Chaos Conference 2004
resumen
Abstract not avaliable
A mixed-signal ASIC for FM-DCSK modulation
M. Delgado-Restituto, A.J. Acosta-Jimenez and A. Rodriguez-Vazquez
Conference · Design of Circuits and Integrated Systems Conference DCIS 2004
resumen
This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER =10(-3) for Eb/No lower than 28 dB.
A mixed-signal integrated circuit for FM-DCSK modulation
M. Delgado-Restituto, A.J. Acosta and A. Rodríguez-Vázquez
Conference · European Solid-State Circuits Conference ESSCIRC 2004
resumen
This paper presents a mixed-signal ASIC for a Frequency-Modulated Differential Chaos Shift Keying (FM-DCSK) communication system [1][2] which has been implemented in a 2P-3M 0.35mum CMOS technology. The prototype has been provided with several programming capabilities to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme. The operation of the integrated circuit is herein illustrated for a data rate of 500kb/s and a transmission bandwidth in the range of 17MHz. Based on experimental results, an estimation of the Bit Error Rate (BER) performance of the modulation scheme in a wireless environment at the 2.4GHz ISM band under different propagation conditions has been realized. Measured results confirm theoretical predictions.(dagger)
Optimum Current/Voltage Mode Circuit Partitioning for Low Noise Applications
R. Jiménez-Naharro, P. Parra-Fernández, P.M. Sanmartin-Rodriguez and A.J. Acosta-Jimenez
Conference · Design of Circuits and Integrated Systems Conference DCIS 2003
resumen
Abstract not avaliable
Analysis of current-mode flip-flops in CMOS technologies
R. Jiménez, P. Parra, P.M. Sanmartín and A.J. Acosta
Conference · Conference on VLSI Circuits and Systems 2003
resumen
In this paper, the analysis of different implementations of memory elements-edge-triggered flip-flops, in current-mode technologies is presented. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 mum CMOS technology. The reliability in operation has been also quantified by timing violation parameters measurement. The main results obtained are, on one hand, the selection of a logic family for an specific application and, on the other hand, the selection of an specific flip-flop structure for a optimized parameter option power, noise or speed. Variations of measured parameters for different operation conditions have been also considered. The main results have shown that CBL-Current Balanced Logic-family presents the best behaviour.
Switching noise reduction in clock distribution in mixed-mode VLSI circuits
P. Parra, A.J. Acosta and M. Valencia
Conference · Conference on VLSI Circuits and Systems 2003
resumen
One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry and the clock generation and distribution logic. It is well known for the mixed-signal community that harmonics of clock signal are easily injected in the analog part. This paper analyzes how some actuations like the insertion of buffers, the suited, placement and routing of the clock tree cells, as well as the suited sizing of devices can save switching noise. In fact, different solutions for the clocking logic generate very different results for switching noise.
A new hybrid CBL-CMOS cell for optimum noise/power application
R. Jiménez, P. Parra, P.M. Sanmartín and A.J. Acosta
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2003
resumen
The design of a new configurable hybrid current-mode/static CBL-CMOS cell is presented. This cell can be used in order to obtain the optimum partitioning between conventional and low-noise logic in the digital part of a mixed-signal circuit, resulting in a optimum power/noise solution. This new cell has been compared with the original logic families obtaining acceptable results with low hardware cost. A combinational multiplier has been designed as a demonstrator example of the utility of the proposed cells.
Design of Synchronous Counters for Low Noise Low Power Applications Using Clock Gating Techniques
P. Parra-Fernández, A.J. Acosta-Jimenez and M. Valencia-Barrero
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2002
resumen
Abstract not avaliable
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
R. Jiménez, P. Parra, P. Sanmartín and A.J. Acosta
Conference · Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2002
resumen
In this comunication, a new technique to generate flip-flops based on differential structures is presented. This technique is based on the modification of size in transistors of existing differential latches. The limitations of the differential structures to apply this technique are few, so the range of application is high. The main application field is in mixed-signal analog-digital circuits, due to the low switching noise generated by these flip-flops. In this parameter, the behavior is similar in both the proposed flip-flop and the original structure, and better than existing flip-flops.
Libros
La Nanotecnología, el mundo de las máquinas a escala nanométrica
A.J. Acosta-Jiménez
Book · 176 p, 2019
resumen
Nos fascina la inmensidad del cosmos porque abarca lo grande pero en él también existe lo pequeño. Hasta hace muy poco no habíamos podido aventurarnos en la estructura de la materia y actualmente sabemos que hay un universo en su interior. Estamos empezando a controlar los mandos de ese nanomundo y, con sus ladrillos, átomos y moléculas, a construir aplicaciones en nuestro beneficio. La nanotecnología desarrolla procedimientos y técnicas revolucionarias con infinidad de usos en múltiples áreas, como la medicina, la electrónica y el diseño de nuevos materiales. Descubre en estas páginas todo su potencial. Las enormes posibilidades de la escala más pequeña.
La nanotecnología: explorando un cosmos en miniatura
A.J. Acosta Jiménez
Book · Colección: Un paseo por el cosmos, 2016
resumen
Abstract not available
Capítulos de libros
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Otras publicaciones
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