Security and privacy in communication are certainly one major right for institutions and people in general, being those factors of strategic interest in our society. Nowadays there are many electronic devices in which security is a must and most of these systems use cryptographic techniques to achieve confidentiality and inviolability in private data management. Many secure electronic systems include cryptographic devices implementing mathematical algorithms that are directed to hide sensitive information. However, due to their specific implementation as a circuit, side channel attacks can be successfully performed and information extracted. Therefore, paying special attention to the physic implementation of cryptographic devices is a crucial point to minimize the leak of information under side channel attacks. Hence, hardware implementations in the case of cryptographic algorithms require an adequate and correct realization of algorithms from the functional point of view as much as the inclusion of robust security mechanisms in order to diminish vulnerability. Most of portable security applications (RFID keys, USB memories, smart cards, etc.) use symmetric encryption that has to be integrated in very low power hardware (lightweight cryptography) what has to be required in the new environments resulting of the Internet of things. This Project aims to obtain a set of countermeasures libraries to be included in high performance hardware implementations (ASICs) in CMOS nanometer technology. The focus will be to increase the security of portable systems against side attacks facing secure (de)ciphering problems. Countermeasures will be proposed at a variety of abstraction levels, going from architecture to layout. These will be ready to be used in any stream or block cipher for any kind of application. Different strategies of passive attacks based on power analysis (DPA), electromagnetic emissions (DEMA) and active non-invasive attacks based on fault injection (clock signal, power supply, temperature) and invasive (light source or pulsed laser) will be considered. Hardware implementations (ASIC) will be developed, including area, frequency and power consumption optimization as well as side channel attacks security improvement. The main concern will be to optimize the systems performance accomplishing security increases with no penalties for this performance. To this aim, vulnerability measures, both experimental and simulated will be very important to qualify the countermeasures and the designed hardware.
The three primary targets of the Project are:
To develop automatic experimental mechanisms to analyze the vulnerability of hardware implementations of ciphering circuits and its application on real implementations.
To propose, design and test hardware countermeasures of different categories to diminish vulnerability in crypto circuits.
To design, integrate and test an ASIC with ciphers including the proposed countermeasures and include the ASIC in a IoT system to evaluate the improvements in security in real systems.