Publicaciones del IMSE

Encontrados resultados para:

Autor: Adoración Rueda Rueda
Año: Desde 2002

Artículos de revistas


Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder
A.J. Ginés, E. Peralías, C. Aledo and A. Rueda
Journal Paper · International Journal of Circuit Theory and Applications, vol. 47, no. 3, pp 333-349, 2019
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This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs
A.J. Gines, E. Peralias and A. Rueda
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp 2966-2970, 2017
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This brief presents a digital calibration technique for compensating timing-skew errors between the sub-ADC and the MDAC in the first stage of sample-and-hold amplifier (SHA)-less pipeline ADCs. In the presence of clock-skew errors, sub-ADC comparators produce time-variant offsets depending on the input-signal slope at the sampling instants. These increase residue excursions at the MDAC output, potentially causing overranging and an increment in nonlinear errors. This paper derives close analytical expressions for these effects. The proposed method uses the overranging information to perform a low-cost estimation and correction of the skew error with the following features: 1) very fast convergence (in the order of 1-k input samples); 2) indirect evaluation of the skew error signal, without any previous knowledge of the input signal's frequency distribution; and 3) relatively simple digital logic--basically, two digital comparators and one small accumulator. The method was verified in behavioral and transistor-level simulations. As a demonstrator, its implementation in a 1.8-V 80-dB SNDR 100-Msps SHA-less pipeline ADC in a 0.18-μm CMOS process is shown.

Black-Box Calibration for ADCs with Hard Nonlinear Errors using a Novel INL-Based Additive Code: A Pipeline ADC Case Study
A.J. Ginés, E.J. Peralías and A. Rueda
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 7, pp 1718-1729, 2017
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This paper presents a digital nonlinearity calibration technique for ADCs with strong input-output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affecting the ADC's performance. As a solution to this problem, this paper proposes a novel INL-based calibration which incorporates information from the ADC's internal signals to provide a robust estimation of static nonlinear errors for multivalued ADCs. The method is fully generalizable and can be applied to any existing design as long as there is access to internal digital signals. In pipeline or subranging ADCs, this implies access to partial subcodes before digital correction; for algorithmic or SAR ADCs, conversion bit/bits per cycle are used. As a proof-of-concept demonstrator, the experimental results for a 1.2 V 23 mW 130 nm-CMOS pipeline ADC with a SINAD of 58.4 dBc (in nominal conditions without calibration) is considered. In a stressed situation with 0.95 V of supply, the ADC has SINAD values of 47.8 dBc and 56.1 dBc, respectively, before and after calibration (total power consumption, including the calibration logic, being 15.4 mW).

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
J. Núñez, A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 89, no. 33, pp 593-609, 2016
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This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100 fsrms) for high-performance ADCs. The key ideas of the design methodology are: (a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, (b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100 fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8 V 0.18 μm and 1.2 V 90 nm). Post-layout simulation results for a case of study with typical jitter of 68 fs for a 1.8 V 80 dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.

Background Digital Calibration of Comparator Offsets in Pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 203, no. 7, pp 1345-1349, 2015
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This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

The bio-oscillator: A circuit for cell-culture assays
G. Huertas, A. Maldonado, A. Yufera, A. Rueda and J.L. Huertas
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 2, pp 164-168, 2015
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A system for cell-culture real-time monitoring using an oscillation-based approach is proposed. The system transforms a cell culture under test into a suitable 'biological' oscillator, without needing complex circuitry for excitation and measurement. The obtained oscillation parameters are directly related to biological test, owed to an empirically extracted cell-electrode electrical model. A discrete prototype is proposed and experimental results with living cell culture are presented, achieving the expected performances.

On-chip sinusoidal signal generation with harmonic cancelation for analog and mixed-signal BIST applications
M. Barragan, G. Leger, D. Vazquez and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 82, no. 1, pp 67-79, 2015
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This work presents a technique for the on-chip generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. The proposed generation technique consists of a modified low-order analog filter, that provides a sinusoidal output as response to a DC input, combined with a harmonic cancellation strategy to improve the linearity of the generated signal. The proposed generator has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. An integrated prototype designed in a 180 nm CMOS technology is presented in order to show the feasibility of the technique. Results obtained from the prototype show a THD around -80 dB.

Blind adaptive estimation of integral nonlinear errors in ADCs using arbitrary input stimulus
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 60, no. 2, pp 452-461, 2011
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An adaptive digital test procedure for the static characterization of analog-to-digital converters (ADCs) is described in this paper. The proposed technique performs a blind and accurate estimation of the integral nonlinearity (INL) of the ADC under test (ADCUT) without requiring any particular test stimulus. Its practical implementation implies no modifications on the ADCUT analog section and needs a very simple low-cost digital logic, which makes this useful for: 1) simple digital automatic test equipment (ATE)-based ADC static test and 2) built-in self-test (BIST) for ADCs test working either in concurrent (online) or nonconcurrent (offline) modes. The validation of these test methods has been performed through realistic behavioral simulations including noise, mismatch, and nonlinear errors. Experimental results for a custom-designed pipeline ADC and for the commercial AD664 chip are also reported.

Alternate test of LNAs through ensemble learning of on-chip digital envelope signatures
M.J. Barragán, R. Fiorelli, G. Léger, A. Rueda and J.L. Huertas
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 27, no. 3. pp 277-288, 2011
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This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. A new Figure of Merit (FOM) is proposed to evaluate the prediction accuracy of the statistical model, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445 GHz low-power LNA and a simple envelope detector, and has been developed in a 90 nm CMOS technology. Post-layout simulations are provided to verify the functionality of the proposed test technique.

Analog sinewave signal generators for mixed-signal built-in test applications
M.J. Barragán, D. Vázquez and A. Rueda
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 27, no. 3, pp 305-320 2011
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This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators-a continuous-time generator and a discrete-time one-have been integrated in a standard 0.35 mu m CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.

On chopper effects in discrete-time ΣΔ modulators
G. Leger, A.J. Ginés-Arteaga, E. Peralías-Macias and A. Rueda
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 57, no. 9, pp 2438-2449, 2010
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Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.

A BIST solution for frequency domain characterization of analog circuits
M.J. Barragán, D. Vázquez and A. Rueda
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 26, no. 4, pp 429-441, 2010
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This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1st-order I I" pound modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35 mu m-3.3 V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of 70 dB@62.5 kHz (1 MHz clock) has been demonstrated.

Design of a CMOS closed-loop system with applications to bio-impedance measurements
A. Yúfera and A. Rueda
Journal Paper · Microelectronics Journal, vol. 41, no. 4, pp 231-239, 2010
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This paper proposes a method for impedance measurements based on a closed-loop implementation of CMOS circuits. The proposed system has been conceived for alternate current excited systems, performing simultaneously driving and measuring functions, thanks to feedback. The system delivers magnitude and phase signals independently, which can be optimized separately, and can be applied to any kind of load (resistive and capacitive). Design specifications for CMOS circuit blocks and trade-offs for system accuracy and loop stability have been derived. Electrical simulation results obtained for several loads agree with the theory, enabling the proposed method to any impedance measurement problem, in special, to bio-setups including electrodes. (C) 2010 Elsevier Ltd. All rights reserved.

On-chip characterization of RF systems based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Journal Paper · Electronics Letters, vol. 46, no. 1, pp 36-37, 2010
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A simple on-chip procedure for testing embedded RF blocks is presented. It is based on the detection and spectral analysis of the two-tone response envelope of the device under test (DUT). A main difference with similar methods is its inherent simplicity, avoiding a preprocessing stage and resorting to simpler circuitry to process the envelope. As a consequence, the main nonlinearity specifications of the DUT can be easily estimated from the envelope signal without the need of expensive RF test equipment.

Low-cost digital detection of parametric faults in cascaded sigma delta modulators
G. Léger and A. Rueda
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 7, pp 1326-1338, 2009
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The test of sigma-delta modulators is cumbersome due to the high performance that they reach. Moreover, technology scaling trends raise seRíous doubts on the intradie repeatability of devices. An increase of variability will lead to an increase in parametric faults that are difficult to detect. In this paper, a design-oriented testing approach is proposed to perform a simple and low-cost detection of variations in important design variables of cascaded Sigma Delta modulators. The digital tests could be integrated in a production test flow to improve fault coverage and bring data for silicon debug. A study is presented to tailor signature generation, with test-time minimization in mind, as a function of the desired measurement precision. The developments are supported by experimental results that validate the proposal.

Enhanced double-histogram test
M.A. Jalón, A. Rueda and E. Peralías
Journal Paper · Electronics Letters, vol. 45, no. 7, pp 349-350, 2009
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A method is introduced for reducing experimental setup complexity and time costs associated with the A/D converters linearity test using double histograms. The method is independent of the waveform of the test signal and it does not require inclusion of any time-interleaved technique to reduce time-drift effects.

Simple evaluation of the nonlinearity signature of an ADC using a spectral approach
E.J. Peralías, M.A. Jalón and A. Rueda
Journal Paper · VLSI Design, vol. 2008, article 657207, 2008
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This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The method is based on a nonnecessarily polynomial continuous and differentiable mathematical model of the converter transfer function, and on the spectral processing of the converter output under a sinusoidal input excitation. The simulation and experiments performed on different ADC examples prove the feasibility of the proposed method, even when the ADC nonlinearity pattern has very strong discontinuities. When compared with the traditional code histogram method, it also shows its low cost and efficiency since a significant lower number of output samples can be used still giving very realistic INL signature values. Copyright © 2008 E. J. Peralías et al.

New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 57, no. 1-2, pp 57-68, 2008
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A novel swapping technique for stage non-linear error calibration in Pipeline ADCs (analogue-to-digital converters) is presented in this paper. The proposed algorithm obtains an estimation of the mismatch between sampling capacitors in the MDAC (multiplying digital-to-analogue converter) inside each stage, without the necessity of interrupting the ADC operation, and therefore, suitable for background calibration applications. The technique also shows its applicability for the amplifier finite DC-gain error, providing a low-cost solution for full calibration of the main static errors in the Pipeline topology with less convergence time, memory resources and simpler calibration hardware than other existing calibration methods. In addition, this work overcomes practical limitations of previous adaptive approaches based on capacitor swapping by introducing a novel modulation scheme. This new scheme minimizes the impact on the analogue part and employs a very simple digital modulation logic.

A CMOS optical PSD with submicrometer resolution
R. Doldán, E. Peralías, A. Yufera and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 53, no. 2-3, pp 109-118, 2007
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This paper presents the design of an optical Position Sensing Detector (PSD) for application in biological material gene identification. The system is able to measure changes in the position of a light spot emitted by a Vertical Cavity Surface Emitting Laser (VCSEL). Changes in spot position are produced by the deflections of a microcantilever used to sense the hybridisation process of the biological material. Detection of these deflections requires submicrometer resolution. The photodetectors and the detection algorithm proposed in this paper have been designed and optimized for this resolution. A 0.35 mu m CMOS prototype consisting of an array of 22 PSDs has been implemented and experimentally characterized. The obtained results confirm that displacements of the light spot position as low as 0.15 mu m can be detected.

A highly sensitive microsystem based on nanomechanical biosensors for genomics applications
L.M. Lechuga,J. Tamayo, M. Álvarez, L.G. Carrascosa, A. Yufera, R. Doldán, E. Peralías, A. Rueda, J.A. Plaza, K. Zinoviev, C. Domínguez, A. Zaballos, M. Moreno, C. Martínez-A, D. Wenn, N. Harris, C. Bringer, V. Bardinal, T. Camps, C. Vergnenègre, C. Fontaine, V. Díaz and A. Bernad
Journal Paper · Sensors and Actuators, B: Chemical, vol. 118, no. 1-2, pp 2-10, 2006
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Microcantilever-based biosensors are a promising tool to detect biomolecular interactions in a direct way with high accuracy. We show the development of a portable biosensor microsystem able to detect nucleic acid hybridization with high sensitivity. The microsystem comprises an array of 20 micromechanical cantilevers produced in silicon technology, a polymer microfluidic system for delivery of the samples, an array of 20 vertical cavity surface emitting lasers (VCSELs) with collimated beams thanks to an integrated microlens array, an optical coupling element to provide the optical path required, and chips with the photodetectors and the CMOS circuitry for signal acquisition and conditioning, capable of measuring the cantilever deflection with sub-nanometer resolution. Robust immobilization and regeneration procedures have been implemented for the oligonucleotide receptor sequences. In a further innovation, an optical waveguide cantilever transducer has been also developed in order to improve the final performance of the device. This has a number of advantages in terms of a simple optical geometry and improved sensitivity.

A tissue impedance measurement chip for myocardial ischemia detection
A. Yufera, A. Rueda, J.M. Muñoz, R. Doldán, G. Léger and E.O. Rodríguez-Villegas
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 12, pp 2620-2628, 2005
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In this paper, the design of a specific integrated circuit for the measurement of tissue impedances is presented. The circuit will be part of a multi-micro-sensor system intended to be used in cardiac surgery for sensing biomedical parameters in living bodies. Myocardium tissue impedance is one of these parameters which allows ischemia detection. The designed chip will be used in a four-electrode based setup where the effect of electrode interfaces are cancelled by design. The chip includes a circuit to generate the stimulus signals (sinusoidal current) and the circuitry to measure the magnitude and phase of the tissue impedance. Several integrated circuits have been designed, fabricated and tested, in a 0.8-mu m CMOS process, working at 3 V of power supply. Some of them including building blocks, and other with the whole measurement system. Experimental tests have shown the circuit feasibility giving expected results for both in-vitro and in-vivo test conditions.

Sine-wave signal characterization using square-wave and Sigma Delta-modulation: Application to mixed-signal BIST
D. Vázquez, G. Huertas, A. Luque, M.J. Barragán, G. Léger, A. Rueda and J.L. Huertas
Journal Paper · Journal of Electronic Testing-Theory and Applications, vol. 21, no. 3, pp 221-232, 2005
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This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. It is based on a double-modulation, square-wave and sigma-delta, together with a simple Digital Processing Algorithm. It leads to an efficient and robust approach very suitable for BIST applications. In this line, some considerations for on-chip implementation are addressed together with simulation results that validate the feasibility of the proposed approach.

Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs
G. Léger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · IEEE Transactions on Circuits and Systems I, vol. 51, no. 1, pp 140-150, 2004
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Using several analog-to-digital converters (ADCs) in parallel with convenient time offsets is considered an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this time-interleaving technique is that any mismatch between the channels will damage the precision. This paper gives a probabilistic description of the problem, studying the impact of time skews, gain, and offset mismatches. The probability density function of both signal-to-noise ratio (SNR) and spurious-free-dynamic range (SFDR) are explicitly calculated, giving access to important statistical parameters. It is shown that the SNR and SFDR dispersion should not be neglected in making practical considerations for design decisions. © 2004 IEEE.

Cascade ΣΔ modulator with digital correction for finite amplifier gain effects
G. Léger and A. Rueda
Journal Paper · Electronics Letters, vol. 40, no. 21, pp 1322-1323, 2004
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A simple and fully digital solution to correct the effect of amplifier finite gain in cascade SigmaDelta modulators is presented. The main contribution of this study is a simple digital method to evaluate the integrator pole errors, which are further taken into account to modify the reconstruction filter. The method is applied to a 2-1 cascade modulator.

Digital test for the extraction of integrator leakage in first- and second-order sigma delta modulators
G. Léger and A. Rueda
Journal Paper · IEEE Proceedings-Circuits Devices and Systems, vol. 151, no. 4, pp 349-358, 2004
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A digital technique for evaluating the integrator leakage within first- and second-order EA modulators is proposed. It involves a very small amount of hardware, which makes it specially suitable for built-in self-test (BIST) implementation. Integrator leakage is known to be related to the converter precision and, hence, the proposed test technique serves as an indirect test of the signal-to-noise ratio (SNR) degradation. As an additional result, a strategy has been derived for digitally correcting the SNR loss due to integrator leakage in cascaded modulators.

A 1.25-V micropower Gm-C filter based on FGMOS transistors operating in weak inversion
E. Rodríguez-Villegas, A. Yufera and A. Rueda
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp 100-111, 2004
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This paper presents a novel linearized transconductor architecture working at 1.25 V in a 0.8-mum CMOS technology with very low power consumption. The special features of the floating-gate MOS (FGMOS) transistor are combined in weak and strong inversion leading to a simplified topology with fewer stacked transistors and a very low noise floor. The design methodology is thoroughly explained, together with the advantages and disadvantages of working with the FGMOS transistor. Furthermore, second-order effects arising from nonideal behavior of the device, are analyzed and limits for the performance are established Experimental results from a second-order low-pass/bandpass filter that was implemented using the transconductor show a tunability of over one and a half decades in the audio range, a dynamic, range of over 62 dB, and a maximum power consumption of 2.5 muW. These results demonstrate the suitability of the FGMOS transistor for implementing analog continuous-time filters, while at, the same time pushing down, the voltage limits of process technologies and simplifying the circuit topologies to obtain significant power savings.

A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion
E. Rodríguez-Villegas, A. Yufera and A. Rueda
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp 256-259, 2004
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This paper describes the implementation of a low-power floating gate MOS-(FGMOS)-based log-domain integrator that reduces the minimum required voltage supply and the risk of instabilities. The performance of the block is illustrated with the experimental results of a second-order low-pass/bandpass filter working in the audio range with a 1-V voltage supply and a maximum power consumption of 2 muW. The experimental results show that the FGMOS transistor is a powerful device that enables the design of low-voltage-supply low-power-consumption filters which have very simple topologies.

Low-voltage CMOS log-companding techniques for audio applications
F. Serra-Graells, A. Rueda and J.L. Huertas
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 38, no. 2-3, pp 121-135, 2004
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This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down to 1 V) low-power (few hundreds of muA) complete SoCs in CMOS technologies. The new design proposal is based on both, the Log Companding theory and the MOSFET operating in subthreshold. Several basic building blocks for audio amplification, AGC and arbitrary filtering are given. The feasibility of the proposed CMOS circuits is illustrated through experimental data for different design case studies in 1.2 and 0.35 mum VLSI technologies.

A switched opamp-based bandpass filter: Design and implementation in a 0.35 μm CMOS technology
L. Quintanilla, J. Arias, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez and A. Rueda
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 34, no. 3, pp 201-209, 2003
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A fully differential SC bandpass filter (central frequency, 58 kHz; Q = 15; and voltage gain, 8) based on the switched-opamp approach is designed and implemented in this work. The filter operates from a single 1 V supply voltage and is realized in a 0.35 mum CMOS technology. It has been characterized with a sampling frequency of 1 MHz and its power consumption is about 230 muW. As a main internal filter component, an appropiate switched opamp was also designed. Its common-mode feedback circuit was implemented by using an error amplifier and sampling of the output common-mode voltage is carried out by applying a DC offset to level shift the common-mode sample. It provides an accurate common-mode output for a wide temperature and supply voltage ranges.

Oscillation-based test in oversampled ΣΔ modulators modulators
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · Microelectronics Journal, vol. 33, no. 10, pp 799-806, 2002
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This paper discusses a way of applying the oscillation-based test (OBT)/oscillation-based built-in-self test concept to oversampled ΣΔ modulators, exploiting previous experience coined through the implementation of OBT in SC integrated filters. Analytical and simulation results demonstrate that it is always feasible to find out an OBT configuration for a typical discrete-time second-order modulator structure without adding a substantial extra circuitry, but only resorting to local feedback loops. A feedback strategy can be chosen providing enough freedom to force oscillations, which can be worthwhile for testing purposes. The selected oscillation parameters allow us to establish criteria for a high fault coverage.

On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits
D. Vázquez, G. Huertas, G. Leger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 201-211, 2002
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This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.

Practical oscillation-based test of integrated filters
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · IEEE Design & Test of Computers, vol. 19, no. 6, pp 64-72, 2002
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Oscillation-based test techniques show promise in detecting faults in mixed-signal circuits and require little modification to the circuit under test. Comparing both the oscillation's amplitude and frequency yields acceptable test quality.

Testing mixed-signal cores: A practical oscillation-based test in an analog macrocell
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper · IEEE Design & Test of Computers, vol. 19, no. 6, pp 73-82, 2002
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A formal set of design decisions can aid in using oscillation-based test for analog subsystems in SoCs. The goal is to offer designers testing options that don't have significant area overhead, performance degradation, or test time.

A simple and secure start-up circuitry for oscillation-based-test application
D. Vázquez, G. Huertas, A. Rueda and J.L. Huertas
Journal Paper · Analog Integrated Circuits and Signal Processing, vol 32, no. 2, pp 187-190, 2002
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A simple start-up strategy specially suitable for the oscillation-based-test application of opamp-based circuits is presented. The proposed approach not only ensures that the oscillator will start to run (safe start-up) but also the steady-state (SS) can be reached very fast (short transient-time).

VHDL behavioural modelling of pipeline analog to digital converters
A.J. Acosta, E. Peralias, A. Rueda and J.L. Huertas
Journal Paper · Measurement, vol. 31, no. 1, pp 47-60, 2002
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This paper describes a VHDL implementation of a behavioural model for pipeline analog to digital converters (ADCs). The goal is using this VHDL description to facilitate the synthesis of the digital part, which in our example includes digital correction, digital calibration, and control of the ADC testing modes. Among other aspects of general interest, we will show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. As an application example, an ADC of 10-bits and 10 MSamples/s has been modelled and simulated. Results front these high level simulations carried out using QuickHDL in Mentor Graphics are compared with those obtained experimentally from a silicon prototype, validating the suitability of the model. (C) 2002 Elsevier Science Ltd. All rights reserved.

Congresos


Mismatch and Offset Calibration in Redundant SAR ADC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
resumen     

This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can occur due to saturation of the redundancy intervals associated with implemented weights, eventually leading to a faulty behavior even with lower effective resolution than the case without calibration. To overcome this limitation, this work proposes a foreground technique which reuses the leastsignificant bit (LSB) capacitors in the array in a design with redundancy for offset compensation. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit SAR ADC case study with 3 redundant bits.

Fast Simulation of Non-linear Circuits using Semi-Analytical Solutions based on the Matrix Exponential
J.A. Serrano, A.J. Ginés, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
resumen     

This paper presents a new simulation method for fast evaluation of non-linear circuits. The proposed approach solves the non-linear ordinary differential equation (ODE) set of the system using a semi-analytical solution based on the matrix exponential. The method is fully general and suitable for different circuits, including switched-capacitor (SC) architectures, analog to digital converters (Pipeline, SAR, Sigma-Delta ADCs) or digital to analog converters (SC, Current-steering DACs). For illustration purpose in this paper, an analog signal processing front-end for discrete-time data acquisition system is considered as case study. The circuit comprises a Flip-Around Sample&Hold followed by a programmable gain amplifier (PGA) based on a Correlated Double-Sampling amplifier. The model includes non-linearity associated to switches, capacitive parasitics, finite non-linear Dcgain and non-linear settling behavior including slew-rate. Comparison with traditional ODE numerical solvers shows a reduction of the computation time in more than two orders of magnitude with negligible difference in terms of accuracy.

SAR ADCs with Redundant Split-capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2018
resumen     

This paper analyzes the effect of redundancy in Successive Approximation Register (SAR) ADCs with splitcapacitor DAC (Split-CDAC). It also presents a general hardware-based model which provides closed-relationships, suitable for design, between the capacitor scale factors, the bridge capacitance and the practical implementation of the digital correction logic. In conventional binary Split-CDAC (without redundancy), the voltage at the floating nets in the array could exceed the ADC references, stressing the operation of switches. Using the proposed model, we will show that this effect also occurs in SAR ADCs with redundancy, but with some particularities depending on the selection of the weighting coefficients in the digital correction logic. We will demonstrate the excursion can be controlled, as in the binary case, with a simple DAC modification which includes an extra limiting capacitor.

Redundant SAR ADCs with Split-Capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2018
resumen     

This paper presents an unified formulation for Successive Approximation Register (SAR) ADCs with splitcapacitor arrays providing explicit expressions, suitable for design, of the relationships between capacitors and the weighting coefficient in the digital correction logic. A closed-form estimation of the optimum limiting capacitor to control the voltage excursion in the floating node of the Least Significant Bit (LSB) array is, in the authors´ bibliography best knowledge, firstly derived in this work. The proposed hardware-based formulation has been verified by behavioral and electrical simulations.

Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach
A. Gines, A. Lopez-Angulo, E. Peralias and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
resumen     

This paper analyzes the state-of-the-art in Successive-Approximation-Register (SAR) ADCs with digital redundancy using a unified nomenclature and modeling. Redundancy provides tolerance intervals for dealing with comparison errors during the SAR search algorithm due to incomplete settling in the DAC. Employing redundancy improves conversion speed/power trade-off as well as relaxes switch sizes and comparator design. The proposed description presents a common theoretical and physical framework for analyzing existing (apparently different) techniques in the bibliography, independently of the practical realization (binary or arbitrary scaled capacitors with redundant bits) and switching schemes. Several examples are modeled and simulated using the proposed approach.

Unified Hardware-Based Description for SAR ADCs with Redundancy
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2017
resumen     

This paper presents an analysis and review of digital redundancy techniques in Successive-Approximation-Register (SAR) ADCs for correction of comparator errors during the SAR search algorithm. The use of redundancy provides safety margin for dealing with incomplete settling in the DAC network, improving conversion speed and power, as well as relaxing switch sizes and comparator design. Techniques like binaryscaled, radix-based or arbitrary weighing capacitors with redundant bits are discussed using a unified nomenclature and modeling. The proposed unified description is closely related to the hardware realization eliminating the gap between theoretical and physical implementations, and allowing a clear identification of pros and cons of different approaches. For illustration purpose, several examples are modeled and simulated using the proposed description.

On the limits of machine learning-based test: A calibrated mixed-signal system case study
M.J. Barragan, G. Leger, A. Gines, E. Peralias and A. Rueda
Conference · Design, Automation and Test in Europe DATE 2017
resumen     

Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system -i.e. a state-of-the-art pipeline ADC-that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.

A Compact R-2R DAC for BIST Applications
A. Rabal, A. Otin, I. Urriza, A.J. Gines, G. Leger and A. Rueda
Conference · International Mixed-Signals Testing Workshop IMSTW 2016
resumen     

This paper presents the implementation of a compact R-2RDigital-to-Analog Converter (DAC) for BIST applications of analog and mixed-signal circuits. It focuses on evaluating the DAC design requirements and its possibilities in structural and alternate test methodologies. More concretely, the aim of the paper is the low-cost generation of digitally programmable DC voltages for parametric deviation injection. For the sake of validation, these voltages will be considered to modify the voltage references of bias circuit or cascode voltages in op-amps. The DAC has been implemented in a UMC 65nm LL CMOS process, and comprises a front-end passive R-2R ladder followed by an active buffer based on a two-stage amplifier with Miller's compensation. Special care has been taken in the resistors ladder layout, as a critical parameter to minimize the mismatch impact due to process variations and maximize the final static behavior. The total power consumption and overall die area for the R-2R DAC ladder are 120 μW and 88x64 μm2, respectively. The op-amp design could be optimized depending on the load and driving requirements.

Monitoring Tissue Evolution on Electrodes with Bio-Impedance Test
A. Maldonado, P. Pérez, G. Huertas, A. Yúfera, A. Rueda, and J.L. Huertas
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
resumen     

A technique for real-time monitoring of bio-impedances using a Voltage Oscillation (VO) methodology is proposed. The main idea relies on connecting the bio-system in such a way that a suitable electrical oscillator, which only uses a DC power source, is built. Thanks to the employed electrical models, the oscillation parameters can be directly related to the biological test. System simulations show that the impedance values of a tissue, called herein Zx, can be determined by measuring the actual frequency and amplitude of the proposed VO system, being possible to select the frequency range to optimize the system sensitivity.

Design Trade-offs for On-chip Driving of High-speed High-performance ADCs in Static BIST Applications
A.J. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M.J. Barragan and S. Mir
Conference · International Mixed-Signals Testing Workshop IMSTW 2016
resumen     

This paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering stage, often overlooked in the literature, is in fact an essential building block for the correct functionality of the BIST in high-speed highperformance applications. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 2.5V 65nm CMOS process is presented here as demonstrator. Transistor-level simulations with a 2Vpp sinusoidal test-stimulus show an effective resolution with realistic switched-capacitor load greater than 15 bits, being a suitable solution for the static test of ADCs with effective resolutions in the order of 12 bits and 80 Msps of sampling frequency.

Linearity Test of High-speed High-performance ADCs using a Self-Testable On-chip Generator
A.J. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M.J. Barragan and S. Mir
Conference · IEEE European Test Symposium ETS 2016
resumen     

This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutionsin the order of 13 bits and 100Msps of sampling frequency.

Cell-Culture Measurements using Voltage Oscillations
A. Maldonado, P. Pérez, G. Huertas, A. Yúfera, A. Rueda and J.L. Huertas
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2016
resumen     

A comprehensive system for real-time monitoring of a set of cell-cultures using a Voltage Oscillation (VO) methodology is proposed. The main idea is to connect the bioelectrical elements (electrodes&cell-culture) in such a way that sequentially a suitable electrical oscillator, which only uses a DC power source, is built. Using the employed electrical models given in [1, 2], the attained oscillation parameters (frequency and amplitude) can be directly related to the biological test. A digital circuitry is developed to pick-up the experimental measurements, which are gathered and shown in real-time in a web application.

From voltage oscillations to tissue-impedance measurements
A. Maldonado, P. Perez, G. Huertas, A. Yufera, A. Rueda and J.L. Huertas
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2015
resumen     

A technique for real-time monitoring of bio-impedances using a Voltage Oscillation (VO) methodology is proposed. The main idea relies on connecting the bio-system in such a way that a suitable electrical oscillator, which only uses a DC power source, is built. Thanks to the employed electrical models, the oscillation parameters can be directly related to the biological test. System simulations show that the impedance values of a tissue, called herein Zx, can be determined by measuring the actual frequency and amplitude of the proposed VO system, being possible to select the frequency range to optimize the system sensitivity.

Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
J. Núñez, A.J. Gines, E. Peralías and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
resumen     

High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (< 200fs) are introduced and compared in a 0.18μm commercial CMOS process.

Towards Bio-Impedance Based Labs: A Review
P. Pérez, A. Maldonado, A. Yúfera, G. Huertas, A. Rueda and J.L. Huertas
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2015
resumen     

Conference Paper

An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs
J. Núñez, A.J. Ginés, E.J. Peralías and A. Rueda
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2015
resumen     

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for highperformance ADCs. The key idea is twofold: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) performing a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm).

Power Optimization and Stage Op-amp Linearity Relaxation in Pipeline ADCs with Digital Comparator Offset Calibration
A. Ginés, E. Peralias, C. Aledo and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2014
resumen     

This paper presents a power optimization technique for Pipeline ADCs using digital background calibration of comparator offsets as an extra design variable. Thanks to calibration, comparator offset errors above half the stage least-significant bit (LSB) margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax the power consumption of stage amplifiers within the Pipeline queue, since output swing and driving capability are significantly lower. The proposal was validated using realistic hardware-behavioral models and transistor-level simulations. A 1.8V 15-bit 74dB-SNDR 100Msps Pipeline ADC was used as a demonstrator. Thanks to comparator calibration, the total power of stage subADCs was reduced by 75%, while a factor of 19% was found in stage amplifiers.

INL Systematic Reduced Test Technique for Pipeline ADCs
E. Peralías, A. Ginés and A. Rueda
Conference · IEEE European Test Symposium ETS 2014
resumen     

This paper presents a procedure to implement a high efficient test of the Integral Non-linearity (INL) of Pipeline ADCs using an extremely reduced set of test input amplitude levels (one order of magnitude lower than the total number of codes in the ADC). For a given architecture, the method provides the way to determine these levels to robustly capture the nonlinearity information. The location of each test level within the input range has low sensitivity to the internal ADC noise, and therefore, they are a good basis to continuously monitor the impact of process, aging and environment conditions variations (PVT) on the non-linearity, as well as miscalibration and possible failures in both foreground and background applications. The proposed method has been validated by realistic behavioral models in several examples.

Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
A.J. Ginés, G. Leger, E. Peralías and A. Rueda
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2014
resumen      pdf

This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.

Oscillation-Based Test applied to cell culture monitoring
G. Huertas, A. Maldonado, A. Yufera and A. Rueda
Conference · IEEE SENSORS 2013
resumen     

A method for cell-culture real-time monitoring by means of Oscillation-Based Test (OBT) technique is proposed. The idea is inspired in previous works from the authors in the area of testing analogue integrated circuits and deals with solving some critical points in this kind of biological measurements. A simple topology based on a non-linear element in a feedback loop is employed for converting the Cell-Culture Under Test (CCUT) into a suitable ¿biological¿ oscillator. Then, the oscillator parameters (frequency, amplitude, phase, etc...) are used as empirical markers to carry out an appropriate interpretation in terms of cell size identification, cell counting, cell growth, etc. The Describing Function (DF) approach employed, for the involved mathematical calculations in the analysis of the 'biological circuit', predicting the frequency and amplitude of the oscillations. The precise values of oscillation parameters are closely related to the cell-electrode area overlap in the cell-culture.

Electrical Cell-substrate Impedance Spectroscopy (ECIS) Measurements based on Oscillation-Based Test Techniques
G. Huertas, A. Maldonado, A. Yufera, A. Rueda and J.L. Huertas
Conference · International Workshop on Impedance Spectroscopy IWIS 2013
resumen     

A system for cell-culture real-time monitoring based on ECIS techniques, using the Oscillation-Based Test (OBT) meethodology is proposed. The system transforms a Cell-Culture under Test (CCUT) ¡nto a suitable 'bioIogical' oscillator, using only a DC power supply. Thanks to cell-electrode electrical models employed, the oscillation parameters obtained can be directly related with biological test. The system simulations solve with a 0.16 Hz/μm2 resolution on cell area detection for a proposed 50 x 50 μm2 microelectrode area.

A Design for yield approach for redundant flash ADC
H. Youssef Darweesh, G. Leger and A. Rueda
Conference · European Workshop on CMOS Variability VARI 2013
resumen     

For the design of high-speed ADCs, the traditional speed-accuracy trade-off can only be solved at the expense of power consumption. Using fast small transistors takes full advantage of technology scaling but induces large amounts of random variability. In the case of FLASH ADCs comparator redundancy has been proposed as a way to relax this speedaccuracy trade-off. In this paper, the design of a FLASH ADC using comparator redundancy is addressed from a statistical viewpoint. Closedform expressions for the yield are derived as functions of the redundancy system variables. These expressions bring the possibility to compute adequate cost functions and rapidly explore the design space to select an optimal point. The case of a 6-bit ADC implemented in a 0,18μm CMOS technology is used as a practical application example of this methodology.

Inductor Characterization in RF LC-VCOs
R. Doldan, A.J. Gines and A. Rueda
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2013
resumen     

This paper analyzes the characterization of inductors in resonant radio frequency (RF) circuits, with emphasis in LC voltage-controlled oscillators (VCOs). We will demonstrate how inductor quality factor is often underestimated in the vicinity of self-resonance frequency, because its capacitive parasitic contribution is not properly considered. In consequence, some valid inductor geometries could be incorrectly discarded during the initial circuit optimization process. To overcome this design space limitation, the paper presents an alternative method to characterize inductors at the wanted resonant frequency. The comparison between the conventional and the proposed methods is illustrated with the characterization of a complete inductor library in a commercial 90nm CMOS RF technology.

Analysis of process variations' impact on a 2.4 GHz 90 nm CMOS LNA
J. Gonzalez, J. Cruz, D. Vazquez and A. Rueda
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2013
resumen     

This work presents the analysis of a 90nm CMOS LNA under process variations. The main parameters charactering the performance of this kind of devices are analyzed. It shows how the performance degradation is mainly derived from the resonant frequency shifting due to the output matching passive network. A way to partially compensate the degradation is presented. Preliminary results are shown.

Cell-culture Real-Time Monitoring: an Oscillation-based Approach
G. Huertas, A. Maldonado, J. Normando Olmo, A. Yúfera, A. Rueda and J.L. Huertas
Conference · Conference on the Design of Circuits and Integrated Systems DCIS 2013
resumen      pdf

In this paper, a way to cell-culture real-time monitoring by means of Oscillation-Based Test (OBT) methodology is proposed. The proposed idea is inspired in previous works from the authors in the area of testing analogue integrated circuits and deals with solving some critical points of biological measurements. A simple topology based on a non-linear element in a feedback loop is employed for converting the Cell-Culture Under Test (CCUT) into a suitable 'biological' oscillator. Then, the oscillator parameters (frequency, amplitude, phase, etc...) are used as empirical markers to carry out an appropriate interpretation in terms of cell size identification, cell counting, cell growth, etc. The precise values of oscillation parameters are closely related to the cell-electrode area overlap in the cellculture. To establish the accuracy of these predictions, the oscillators have been implemented and validated in Simulink.

Mixed-Signal Techniques for Robust Auto-Tuning of Split-Tuned PLL Frequency Synthesizers
C. Aledo, A.J. Ginés, E. Peralías and A. Rueda
Conference · Conference on the Design of Circuits and Integrated Systems DCIS 2013
resumen     

This paper proposes two different phase-locked loop (PLL) auto-tuning techniques for low-cost sub-band selec-tion in split-tuned frequency synthesizers. The methods conti-nuously monitor the tuning voltage Vtune of the voltage-controlled oscillator (VCO) using two comparators whose threshold voltages define the PLL design region. Considering the comparators deci-sion, a simple digital control unit (DCU) generates a correction signal which assures Vtune is always within the allowable range, hence concurrently dealing with process, voltage and tempera-ture (PVT) variations. Two alternative algorithms depending on the DCU implementation have been proposed as trade-off between hardware complexity and convergence response. Both algorithms have been experimentally validated in a 1.2V PLL frequency synthesizer. This PLL block is part of a monolithical 2.4GHz IEEE 802.15.4 ZigBee transceiver implemented in a RF 90nm CMOS technology.

Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique
M.J. Barragan, G. Leger, D. Vazquez and A. Rueda
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2013
resumen      pdf

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. The proposed generation technique is based on a modified analog filter, that provides a sinusoidal output as the response to a DC input, combined with a harmonic cancellation technique. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. Simulation results are provided in order to validate the proposed generation technique.

Background Calibration of Comparator Offsets in Pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · International Conference on Analog VLSI Circuits AVIC 2012
resumen     

A digital low-cost adaptive technique for calibrating comparator offsets in Pipeline ADCs is proposed in this paper. The method is suitable for a generic topology including standalone dynamic-latch comparators (SA-DLCs) with no external reference and no preamplifier. It performs an accurate blind estimation and an adaptive correction of comparator offsets without redundant hardware or calibration stimuli, and without interruption of the ADC operation (background mode). The method also allows relaxing the power consumption of stage amplifiers, since their output swing and driving capability are significantly reduced. The technique has been validated by realistic hardware-behavioral models and transistor-level simulations.

Semi-empirical model of MOST and passive devices focused on narrowband RF blocks
R. Fiorelli, F. Silveira, A. Rueda and E. Peralías
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2012
resumen      pdf

This paper presents a semi-empirical modeling of MOST and passive elements to be used in narrowband radiofrequency blocks for nanometer technologies. This model is based on a small set of look-up tables (LUTs) obtained via electrical simulations. The MOST description is valid for all-inversion regions of MOST and the data is extracted as function of the gm=ID characteristic; for the passive devices the LUTs include a simplified model of the element and its principal parasitic at the working frequency f0. These semi-empirical models are validated by designing a set of 2.4-GHz LNAs and 2.4-GHz and 5-GHz VCOs in three different MOST inversion regions.

Self-Biased Input Common-Mode Generation for Improving Dynamic Range and Yield in Inverter-Based Filters
A.J. Ginés, A. Villegas, A. Rueda and E. Peralías
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
resumen     

A simple and robust circuit for the input commonmode voltage generation in CMOS pseudo-differential inverter-based transconductors is proposed. The solution can improve the in-band IIP3 in 7.8dBVp and the 1-dB compression point in 5.3dBVp compared to conventional approaches, with less noise, power consumption and occupied die area. A 1.2V 3.42mW 1.3-3.7MHz high-linear 8th order bandpass complex filter is presented as demonstrator in a CMOS 90nm process. The yield for an image rejection ration IRR above 50dB is 86%, which represents a 31% improvement respect to the classical approach.

A 0.2pJ/conversion-step 6-bit 200MHz flash ADC with redundancy
H. Darwish, G. Léger and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2012
resumen      pdf

In this paper, a 200MHz 6-bit Flash analog-to-digital converter (ADC) is presented. The principal objective is to obtain a digital-friendly converter. Hence, small and simple latched comparators are used and redundancy allows reducing the offset down to an acceptable level. This obviously requires calibration but reduces power consumption, since small size transistors can be used and the unused comparators are powered down. The proposed ADC is designed in UMC 0:18μm CMOS technology. Full electrical simulations show that the ADC reaches an effective number of bits (ENOB) of 5.3 associated to a signal-to-noise-anddistortion ratio (SNDR) is 33dB. The converter consumes only 1.56mW and has figure-of-merit (FoM) of 0.2 pJ / conversion step.

Analysis of steady-state common-mode response in differential LC-VCOs
R. Doldán, A.J. Ginés, E. Peralías and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2012
resumen      pdf

This paper analyzes the common-mode response of LC voltage-controlled oscillators (VCOs) in DC and periodic steady state regimes. The dependence of the common-mode voltage (v cm) on the oscillation amplitude is theoretically studied. Closed and simple expressions for v cm suitable for the VCO design and optimization are derived. The agreement with transistor level simulations has been verified in a 1.2V low-power 90nm CMOS case of study.

A 3.6mW @ 1.2V high linear 8th-order CMOS complex filter for IEEE 802.15.4 standard
A. Villegas, D. Vázquez, E. Peralías and A. Rueda
Conference · European Solid-State Circuits Conference ESSCIRC 2011
resumen      pdf

This paper presents a fully differential 1.2V 8th-order inverter-based gm-C complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm CMOS technology. Tuning is carried out through voltage controlled capacitors instead of transconductors, resulting in a significant improvement in terms of linearity. The filter presents attractive attributes in terms of power, IRR, SFDR, noise and selectivity, demonstrated by experimental measurements from a fabricated prototype. © 2011 IEEE.

Improving the accuracy of RF alternate test using multi-VDD conditions: Application to envelope-based test of LNAs
M.J. Barragán-Asián, R. Fiorelli-Martegani, G. Leger, A. Rueda and J.L. Huertas-Díaz
Conference · Asian Test Symposium ATS 2011
resumen      pdf

This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.

2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS
R. Fiorelli, A. Villegas, E. Peralías, D. Vázquez and A. Rueda
Conference · European Conference on Circuit Theory and Design ECCTD 2011
resumen      pdf

A 2.4-GHz CMOS single ended-input differential-output front-end built with a common source low noise amplifier (CS-LNA) and a switched transconductor mixer (SW-MIX) is presented. The circuit is designed and optimized to work in a ZigBee receiver. Since this is a low power consumption standard, a single-ended LNA is preferred over a fully-differential topology because it leads to lower cost in area and power consumption. Also, moderate and weak inversions regions were selected for the operation of the principal transistors. The front-end prototype has been implemented in a 90 nm RF process and occupies a chip area of 0.74 mm2 including on-chip inductors. Very competitive results are observed: a maximum conversion gain (CG) of 30 dB, a DSB noise figure of 7.5 dB, a maximum IIP3 of -12.8 dBm and IIP2 of 14.4 dBm while it consumes 4.7 mW from a 1.2 V supply. © 2011 IEEE.

Regression Modeling for Digital Test of Sigma-Delta Modulators
G. Leger and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
resumen      pdf

Automatic Test Equipment. In this paper, we apply the concept of Alternate Test to achieve digital testing of converters. By training an ensemble of regression models that maps simple digital defect-oriented signatures onto Signal to Noise and Distortion Ratio (SNDR), an average error of 1:7% is achieved. Beyond the inference of functional metrics, we show that the approach can provide interesting diagnosis information.

Power Optimization of CMOS Programmable Gain Amplifiers with High Dynamic Range and Common-Mode Feed-Forward Circuit
A.J. Gines, R. Doldán, A. Rueda and E. Peralias
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2010
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A 1.2V 1.95mW low-power Programmable Gain Amplifier (PGA) with high-input range is proposed and implemented in a 90nm CMOS process. The PGA is formed by three stages with a bandwidth of 20MHz for a 2pF capacitive load. Gain is in the range between 0 and 72dB in steps of 6dB. The stage core consists in a differential super-source follower (SSF) with programmable resistive degeneration. Each stage uses a front-end capacitive decoupling network which allows a robust selection of the operating point for improving linearity and reducing power. Further power saving is achieved with a common-mode feed-forward circuit (CMFFC), based on a simple current conveyor. The total PGA area is 165×33μm2 in a 90nm CMOS process. Post-layout simulations at maximum gain show a THD of -57dB and -42dB for output amplitudes of 0.6Vpp and 1.2Vpp, respectively. Input referred noise is just 10.2nVrms/√Hz from 1MHz to 4MHz.

A low-power programmable gain amplifier with optimized input range in 90nm CMOS process
A.J. Ginés, R. Doldán, A. Rueda and E. Peralías
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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Abstract not available

A 5 GHz LC-VCO with active common mode feedback circuit in sub-micrometer cmos technology
R. Doldán-Lorenzo, A.J. Ginés-Arteaga, A. Rueda and E. Peralías
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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A 1.2V 5GHz low-cost voltage-controlled oscillator (VCO) with active common mode feedback has been implemented in a CMOS/RF 90nm technology for a robust I/Q generation using a frequency divider-by-2 (DIV2). As the input common mode of the DIV2 affects critically its performance, a calibration method to correct the output common mode of the VCO has been proposed and validated through post-layout simulations.

A 1.2V CMOS-90nm gm-c complex filter with frequency tuning for wireless network applicatons
A. Villegas, D. Vázquez and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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Abstract not available

1.2V, 1.96mw At 2.4 GHz CMOS-90nm Switched-Transconductor Mixer
A. Villegas, D. Vázquez and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2010
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Abstract not available

Low-cost signature test of RF blocks based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE European Test Symposium ETS 2010
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This paper presents a novel and low-cost methodology that can be used for testing RP blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach. © 2010 IEEE.

An adaptive BIST for INL estimation of ADCs without histogram evaluation
A.J. Ginés, E. Peralías and A. Rueda
Conference · IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop IMS3TW 2010
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A robust low-cost test solution for static characterization of analog-to-digital converters (ADCs) is presented in this paper. It uses an adaptive algorithm to perform a blind and accurate estimation of the Integral Non-Linearity (INL) of the ADC under test (ADCUT). Its main applications are for: a) simple off-line ADC test using modern mixed-signal ATEs (Automatic Test Equipments) without requiring any dedicated input stimulus, b) Built-in Self-test (BIST) for ADC INL evaluation either in concurrent (on-line) or non-concurrent (off-line) modes. The test validation has been performed through realistic behavioral simulations including noise, mismatch and non-linear errors. Experimental results for a custom-designed 10-bit Successive Approximation (SAR) ADC are also reported. ©2010 IEEE.

A low power low voltage mixer for 2.4 GHz applications in CMOS-90nm technology
A. Villegas, D. Vázquez and A. Rueda
Conference · IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
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This paper presents the design of a fully differential double balanced switched transconductor mixer for ZigBee applications in the 2.4GHz band. It provides programmable conversion gain by using an active load stage. The design includes RF and LO input matching networks. It has been implemented in a 90nm 1P9M CMOS process. Post-layout simulations show conversion gains of 12dB/20dB, NF of 18.9dB/18.1dB and power consumption of 4.1mW/4.4mW at high and low gain mode respectively from a 1.2V power supply. It also offers very good linearity performance. © 2010 IEEE.

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems
M.J. Barragán, G. Huertas, A. Rueda and J.L. Huertas
Conference · IEEE International Symposium on Electronic Design, Test and Applications DELTA 2010
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This paper presents an overview of test techniques that offer promising features when Built-In-Self-Test (BIST) must be applied to complex intgrated systems including analog, mixed-signal and RF parts. Emphasis is on techniques exhibiting a good trade-off between test requirements (basically in terms of signal accuracy and frequency) and test quality. © 2010 IEEE.

On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation
A.J. Ginés, R. Doldán, M.J. Barragán, A. Rueda and E. Peralías
Conference · International Symposium on Circuits and Systems ISCAS 2010
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In this work a CMOS 1.2V 5GHz low-power voltage-controlled oscillator (VCO) is proposed. It uses an on-chip biased LC-tank topology and introduces a temperature compensation technique which stabilizes the oscillation amplitude for a robust I/Q generation using a frequency divider-by-2. Compared to a standard design with constant bias, it reduces the oscillation variation by almost two orders of magnitude between 0 degrees C and 100 degrees C with negligible impact on the phase noise. Worst case estimations of the VCO phase noise after layout parasitic extraction are -110.1dBc/Hz and -126.6dBc/Hz at 1MHz and 5MHz offsets from the carrier, respectively. Its nominal current consumption is 198μA (plus 22.5μA for biasing) and it occupies 370x530μm2.

Random Chopping in Sigma-Delta Modulators
G. Léger, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2009
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ΣΔ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency range. As a result ΣΔ modulators are often the preferred option for sensor and instrumentation. Offset and Flicker noise are usual concerns for this type of applications and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Frequency-shaped random chopping has been proposed to minimize the impact of reference voltage interference. It is shown in this paper that the chopper signal is not the only term that modulates the offset and Flicker noise and that unwanted crosstalk can significantly degrade the performance of the modulator.

A CMOS Bio-impedance Sensor System for Cell Culture Monitoring
A. Yúfera and A. Rueda
Conference · IEEE Circuits and Systems for Medical and Environmental Applications Workshop CASME 2009
resumen     

Abstract not avaliable

On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation
A.J. Ginés, E. Peralías and A. Rueda
Conference · European Conference on Circuit Theory and Design ECCTD 2009
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An adaptive digital built-in self-test (BIST) for the static characterisation of analogue-to-digital converters (ADCs) has been developed in this work. The proposed technique performs a blind and accurate estimation of the Integral Non-Linearity (INL) of the ADC under test (ADCUT) without affecting to the normal converter operation, using any test stimuli or replicated hardware. The practical implementation of the BIST technique implies no modifications on the analogue section of the ADCUT and uses a very simple low-cost digital logic, which overcomes the classical area overhead of histogram-based approaches for INL measurement.

A survey on digital background calibration of ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · European Conference on Circuit Theory and Design ECCTD 2009
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In this paper, a general description of digital ADC calibration approaches in current state-of-the-art is presented, with particular emphasis in Pipeline converters. The study performs a classification of the existing techniques considering two basic aspects: a) the principle of operation and the particular errors which can be compensated after calibration, b) the process from which a measurement of the errors, and therefore the calibrated output code, is obtained. Attention will be paid to those approaches applied in background mode and hence not requiring the interruption of the normal ADC operation.

Practical test cores for the on-chip generation and evaluation of analog test signals: Application to a network/spectrum analyzer for analog BIST
M.J. Barragán, D. Vázquez and A. Rueda
Conference · IEEE PhD. Research in Microelectronics and Electronics PRIME 2009
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This paper presents practical implementations of test cores for analog and mixed-signal BIST. A sinewave generator for test stimulus generation, and a peRíodical signal characterization system for response evaluation are discussed. Integrated prototypes and experimental results are provided, and a prototype of a network/spectrum analyzer featuring both test cores has been developed and tested in the lab.

Efficient functional built-In test for RF systems using two-tone response envelope analysis
M.J. Barragán, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE AFRICON 2009
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This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

A BIST solution for the functional characterization of RF systems based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE Asian Test Symposium ATS 2009
resumen      pdf

This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally practical simulation examples show the feasibility of the approach.

A CMOS bio-impedance measurement system
A. Yufera and A. Rueda
Conference · IEEE Design and Diagnostics of Electronics Systems DDECS 2009
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This paper proposes a new method for bio-impedance measurement useful to 2D processing of cell cultures. It allows to represent biological samples by using a new impedance sensing method, and exploiting the electrode-to-cell model for both electrical simulation and imaging reconstruction. Preliminary electrical simulations are reported to validate the proposal for Electrical Cell Impedance Spectroscopy (ECIS) applications. The results reported show that low concentration cell culture can be correctly sensed and displayed at several frequencies using the proposed CMOS system.

A 2.5MHz bandpass active complex filter with 2.4MHz bandwidth for wireless communications
A. Villegas, R. Bianca, A. Ginés, R. Doldán, M.A. Jalón, A.J. Acosta, E. Peralías, D. Vázquez and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2008
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This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The filter compliants with the requirements of the IEEE802.15.4 standard. Simulation results including mismatching and process variations over the extracted view of the circuit are shown. The filter has a nominal gain of 12dB, good selectivity (20dB@2MHz offset), high image rejection (51dB nominal) and low power consumption (3.6mA @2.5V).

A 2.4 GHz LNA in a 90-nm CMOS technology designed with ACM model
R. Fiorelli, F. Silveira, E. Peralías, D. Vazquez, A. Rueda and J.L Huertas
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2008
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As part of a Low-IF ZigBee receiver, a 2.4GHz differential common source low noise amplifier, implemented in a 90nm mixed/RF 7M CMOS process and designed in moderate inversion, is presented in this work. Design methodology and simulation results from Spectre-RF simulator are presented. With 2.5V supply voltage, the LNA achieves a noise figure of 2.5dB, an IIP3 of 1dB and gain higher than 10dB, with a current consumption of 12mA. The LNA area without pads is 720m x 710m. Copyright 2008 ACM.

A 5 GHz wide tuning range LC-VCO in sub-micrometer CMOS technology
R.D. Lorenzo, A.J. Ginés-Arteaga, A. Rueda and E. Peralías
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
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A 1.2V low-cost voltage-controlled oscillator (VCO) has been implemented in a CMOS/RF 90nm technology. The VCO, which uses a LC- tank topology, has a centre frequency of 5GHz with a 30% tuning range from 4.24GHz to 5.74GHz. Worst case estimations of the phase noise after layout and package parasitic extraction are -98.8dBc/Hz and -115dBc/Hz at 1MHz and 5MHz offsets from the carrier, respectively. The power consumption is 2.52mW and it occupies less than 0.07mm(2).

A 1.2V 5.14 mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4 GHz ZigBee applications
A.J. Ginés, R. Doldán, A. Villegas, A.J. Acosta, M.A Jalón, D. Vázquez, A. Rueda and E. Peralías
Conference · IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
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A low-cost 1.2V 5.14mW phase-lock loop (PLL) quadrature frequency synthesizer compliant with the 2.4GHz ZigBee standard (IEEE 802.15.4) has been implemented in 90nm CNIOS technology. In-phase and quadrature (I/Q) components exhibit a phase noise of-105.9dBc/Hz at 1MHz offset from the carrier. The PLL die area including decoupling capacitors and testing buffers is 209x422 mu m(2).

A method for bioimpedance measure with four- and two-electrode sensor systems
A. Yufera and A. Rueda
Conference · Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society EMBS 2008
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This paper presents an alternative method to measure impedances based on constant amplitude voltage excitation. The method makes use of feedback principle to adapt the measure conditions to load under test, being easily applied to bioimpedance measure with electrode sensors. The method has been tested for several frequencies and loads, employing four and two electrode setups. Results from electrical simulations, using CMOS circuits, fulfil the expected performance. This technique can be extended to wide frequency and load ranges, being an excellent option for impedance spectroscopy and EIT applications.

Practical implementation of a network analyzer for analog BIST applications
M.J. Barragán, D. Vázquez and A. Rueda
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2008
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This paper presents a practical implementation of a network analyzer for analog BIST applications. The network analyzer consists of a sinewave generator and a sinewave evaluator based on switch-capacitor techniques. Both the generator and the evaluator have been integrated in a 0.35 mu m CMOS technology. The functionality of the system has been proved in the lab. For this purpose, a demonstrator board has been developed including the proposed network analyzer and a filter as DUT Measurements in the lab demonstrate a dynamic range of 70dB in the frequency range up to 20kHz.

Novel swapping techniques for background calibration of capacitor mismatching in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · Symposium on Integrated Circuits and System Design SBCCI 2007
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A novel swapping technique for calibration of the stage non-linear errors in Pipeline ADCs is proposed in this paper. The algorithm obtains an estimation of the mismatching between sampling capacitors in practical SC implementations of the multiplying-DAC without the necessity of interrupting the converter operation, and therefore, suitable for both foreground and background calibration applications. This work overcomes the practical limitations of previous adaptive approaches based on the capacitor swapping introducing a novel modulation scheme which minimizes the impact on the analogue part and employs a simple calibration logic.

Improved background algorithms for pipeline ADC full calibration
A.J. Ginés, E. Peralías and A. Rueda
Conference · International Symposium on Circuits and Systems ISCAS 2007
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A unified description of the correlation-based techniques for background calibration of Pipeline ADCs using additive modulation at the MDAC output is presented in this paper. Two different algorithms for full calibration of this kind of converter which at least a factor 2 improvement in convergence speed, memory resources and stage output swing requirements over previous MDAC modulation approaches are also proposed.

On-chip analog sinewave generator with reduced circuitry resources
M.J. Barragán, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2006
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This paper proposes an analog sinewave signal generator with minimal circuitry resources. It is based on a linear time variant filter that gives a high quality sine signal in response to a DC input. The proposed architecture has the attributes of digital programming and control capability, robustness and reduced area overhead, what make it suitable for BIST applications. Experimental results from a practical design demonstrate the feasibility of the approach.

Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs(1)
A.J. Ginés, E. Peralías and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2006
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This paper presents a theoretical analysis of the statistical requirements of a background correlation-based technique for calibration of Pipeline ADCs. The calibration algorithm estimates adaptively the appropriate additive error codes which compensate both the gain and non-linear errors in the stage under calibration (SUC). Close equations for the transient evolution towards the stationary situation are obtained. Expressions for the effective number of bits (ENOB) and signal-to-noise ratio (SNR) at any updating step are also derived.

Experimental validation of a fully digital BIST for cascaded Sigma Delta modulators
G. Léger and A. Rueda
Conference · IEEE European Test Symposium ETS 2006
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This work presents a Sigma Delta modulator prototype that gives experimental support to a fully digital Built-In Self-Test scheme. The goal of the proposed BIST is to provide digital signatures that are directly related to some important behavioural parameters of Sigma Delta modulators. As a result, parametric drafts can be detected before they seRíously affect performance. The modulator required modifications are minimal and few gates would be necessary to implement a full BIST version, enabling infield self-test.

A sinewave analyzer for mixed-signal BIST applications in a 0.35 mu m technology
M.J. Barragán, D. Vázquez and A. Rueda
Conference · IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems DDECS 2006
resumen     

This paper presents an integrated prototype of a mixed-signal sinewave analyzer. It extracts, in the digital domain, the DC level and the amplitude of the harmonics of a distorted analog sinewave signal. It Is based on a double modulation, squarewave and sigma-delta, together with a simple digital processing algorithm. The presented prototype has been integrated In a 0.35 pm technology. It is intended for the characterization of sinewave signals In the range of audio. Experimental measurements in the lab verify the feasibility of the approach and the functionality of the prototype.

Mixed-mode simulation of optical-based systems: PSD application
R. Doldán, E. Peralías, A. Yufera and A. Rueda
Conference · Conference on Bioengineered and Bioinspired Systems II, 2005
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This paper reports a new model for electrical simulation of photodetector cells, that includes its complete dynamics, and enables full system characterization, both optical and electrical parts by using the same simulation environment (Spectre in our case). The modelling of the optical parts presented in this work allows the designer to change parameters such as incident spot position and optical power, speed in spot position, photodevices responsivity, pixel fill-factor, etc. The paper presents the design and the simulation-based verification of a Position Sensing Detection (PSD) system for applications with resolutions in the micrometer range and with spot movement tracking operation originated in a DNA sensing process.

Full calibration digital techniques for pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · International Symposium on Circuits and Systems ISCAS 2005
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This paper presents a new digital algorithm for full calibration of Pipeline ADCs with digital redundancy. The proposed algorithm corrects both the MDAC gain error of the stage under calibration (SUC) and its non-linear errors. It is based on the modulation of the analogue output of the SUC using a digital control signal to introduce a constant displacement in the references of the comparators in the SUC sub-ADC without reduction of the input dynamic rate. This process can be performed without interruption of the conversion (background mode) including a digital pseudo-random number generator (RNG). The foreground implementation of this algorithm uses a DC calibration stimulus which relaxes the hardware requirements.

Integrated Opto-Nanomechanical biosensor for functional genomic analysis (OPTONANOGEN)
F.J. Tamayo de Miguel, M. Álvarez, L.G. Carrascosa, L.M. Lechuga, J.A. Plaza, K. Zinoviev, C. Domínguez-Matas, A. Yúfera, A. Rueda, A. Zaballos, M. Moreno, C. Martínez-Alonso, C. Fontaine, V. Díaz and A. Bernad
Conference · Workshop on Nanomechanical Sensors 2004
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Abstract not available

A digital test for first-order sigma delta modulators
G. Léger and A. Rueda
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen     

This paper presents a digital structural test for first order Sigma-Delta modulators. A periodic digital sequence is used as a stimulus to obtain a signature of the integrator leakage. This parameter is known to be related to the modulator precision and its estimation is of great importance to assess if the modulator works as expected. As the proposed technique is fully digital, it is specially suitable to test modulators embedded in complex Mixed-Signal circuits.

Noisy signal based background technique for gain error correction in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen     

The paper presents a new digital technique for background calibration of gain errors in pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration (SUC) and the global gain error associated with the least significant stages. This process is performed without interruption of the conversion and without reduction of the dynamic range. It uses a stage with two input-output characteristics depending on the value of a digital pseudorandom noisy signal to modulate the output residue of the SUC and to estimate the calibration code by an adaptive averaging process. The proposed method introduces no significant modifications in the analogue blocks of the pipeline ADCs, making this technique a very promising alternative for background calibration of the nonlinearity associated with the gain errors. Simulation results have proved the stability of the algorithm and the tracking capability for fast gain error changes considering second order effects in both the sub-ADC of the SUC and the back-end stages.

Digital background gain error correction in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen     

This paper presents a new digital technique for background calibration of gain errors in Pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration and the global gain error associated to the uncalibrated stages without interruption of the conversion and without reduction of the dynamic rate. It is based on the use of a stage with two input-output characteristics, depending on the value of a digital noise signal.

Method for parameter extraction of analog sine-wave signals for mixed-signal built-in-self-test applications
D. Vázquez, G. Léger, G. Huertas, A. Rueda and J.L. Huertas
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen     

This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. The required circuitry for on-chip implementation is very simple and robust, which makes the present approach very suitable for BIST applications. Solutions in this sense are addressed together with simulation results that validate the feasibility of the proposed approach.

Digital test for first-order sigma delta modulators
G. Léger and A. Rueda
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen     

This paper presents a digital structural test for first order Sigma-Delta modulators. A peRíodic digital sequence is used as a stimulus to obtain a signature of the integrator leakage. This parameter is known to be related to the modulator precision and its estimation is of great importance to assess if the modulator works as expected. As the proposed technique is fully digital, it is specially suitable to test modulators embedded in complex Mixed-Signal circuits.

A first order incremental analog to digital converter based on continuous time circuits
R. Doldán, A. Yúfera and A. Rueda
Conference · International Measurements Conference XVII IMEKO 2003
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In this paper, an incremental Analog-to-Digital Converter (ADC) designed as part of the signalconditioning circuitry for tissue impedance measurement system is presented. Continuous-time design techniques has been used and a modified implementation of the conversion algorithm, with respect to its discrete-time counterpart, has been developed. To reduce the influence of the no-idealities, analog and digital corrections have been also implemented. A prototype in 0.8μm CMOS technology has been fabricated and tested. Experimental results are reported.

A LP-LV high performance monolitic DTMF receiver with on-chip test facilities
D. Vázquez, G. Huertas, M.J. Avedillo, J.M. Quintana, A. Rueda and J.L. Huertas
Conference · Conference on VLSI Circuits and Systems 2003
resumen     

This paper presents a mixed-signal DTMF receiver implemented in a double-poly double-metal 0.6um technology able to operate in the range of 2.7V-5V of voltage supply with a low current consumption (<1mA). An smart digital detector and decoder algorithm provides a very good speech immunity. On-chip test facilities for the analog part have.. been incorporated into the chip. A modified opamp (called sw-opamp) has been used to provide external accessing to inputs and outputs of the main analog blocks for off-line testing purposes. The so-called Oscillation-Based-Test (OBT) has also been integrated to perform a structural testing of the analog part. The additional cost of such on-chip test facilities is very small: just one extra pin and an area overhead of around 7%. Experimental results demonstrate the good performance of the design and the feasibility of the testing approaches.

A charge correction cell for FGMOS-based circuits
E.O. Rodríguez-Villegas, A. Yúfera and A. Rueda
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2003
resumen     

This paper describes a novel cell used in circuits with Floating Gate MOS transistors (FGMOS) to compensate variations in the device effective threshold voltages caused by the trapped charge at the floating gate. The performance of the circuit is illustrated with experimental results showing a residual error below 1%. This coarse compensation makes possible to reduce charge effects to the same order of magnitude than the conventional mismatching in normal MOS transistors.

Digital background calibration technique for pipeline ADCs with multi-bit stages
A.J. Ginés, E. Peralías and A. Rueda
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2003
resumen     

This paper presents a technique for background calibration of Pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations Of the LMS algorithm have been studied, concluding that the traditional SS-LMS algorithm has inherent convergence problems in high accuracy ADCs that can be solved considering a SD-LMS implementation.

Oscillation-based test in bandpass oversampled A/D converters
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE International Mixed-Signal Testing Workshop IMSTW 2003
resumen     

This paper extends a study performed by the authors in Previous papers dealing with the OBT approach applied to low-pass modulators 'Microelectron. J. 33/10 (2002) 799', showing herein the specific features associated to the bandpass case. A practical feedback strategy will be proposed in order to built an effective oscillator, which can be valuable for testing purposes. Critical points of the proposed OBT solution will be considered in order to establish useful guidelines to apply this test approach to generic bandpass SigmaDelta modulators. (C) 2003 Elsevier Ltd. All rights reserved.

Threshold-logic-based design of compressors
J.M. Quintana, M.J. Avedillo, E. Rodríguez-Villegas and A. Rueda
Conference · IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
resumen     

The design of efficient compressor circuits is a key problem in the design of high-performance applications where the impact of carry propagation must be reduced as much as possible. Examples of application for these compressors extend from arithmetic units such as parallel multipliers to high-performance, high-capacity digital neural networks (DNNs). This paper proposes new, threshold logic based, compressors to improve the delay in the critical signal path. Optimal design of such compressors has been addressed in both logical and electrical directions and our results show that such compressors have the best performance in delay and power-delay product when compared to conventional implementations.

Practical solutions for the application of the oscillation-based-test in analog integrated circuits
D. Vázquez, G. Huertas, G. Léger, A. Rueda and J.L. Huertas
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen     

This paper presents practical solutions for solving the problems arising when applying Oscillation-Based-Test. It is devoted to discuss a practical on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.

SNR probability in time-interleaved ADCs with random channel mismatches
G. Léger, E. Peralías and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen     

One of the ways to push the speed limits of Analog to Digital Converters (ADCs) is to time-interleave several channels. However, any mismatch between channels degrades the converter resolution. This work is a deep study of the impact of random time skew, gain and offset mismatches on the Signal-to-Noise-Ratio (SNR). The SNR probability density function (PDF) is determined as a function of both these errors and the number of channels. It provides valuable information about the performance margins that could be expected in a design.

A micropower log domain FGMOS filter
E.O. Rodríguez-Villegas, A. Rueda and A. Yufera
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen     

In this paper, a CMOS implementation of a low voltage micropower logarithmic biquad based on Floating Gate MOS transistors (FGMOS) is presented. The translinear principle applied to the floating gate MOS transistor leads to an easy implementation of the state-space equations without using the source terminal in the loop. The voltage supply can be reduced and also there is no need of separate wells. The technique is proven in this low/band pass filter working at 1V with a maximum power consumption of 2muW. The filter parameters can be adjusted in more than two decades, being the upper frequency around 150kHz.

Simple parallel weighted order statistic filter implementations
M.J. Avedillo, J.M. Quintana and E. Rodríguez-Villegas
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen     

This paper describes a simple parallel architecture for the implementation of Weighted Order Statistic Filters (WOS), an important class of digital non-linear filters. The new architecture combines the design easiness of stack architectures with the area efficiency of those based in ordering matrices. It decomposes the M-valued signals into a reduced number of binary signals which are filtered by identical boolean logic circuits. Both area-efficient and fast implementations are obtained straight-forward from filter specifications. The design of a complex WOS filter is described. Results show a sample frequency over 60 Mhz in a 0.35mum MOS technology.

High-speed low-power logic gates using floating gates
E. Rodríguez-Villegas, J.M. Quintana, M.J. Avedillo and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen     

Low power consumption is attractive because of portability and reliability considerations. One way to reduce this power consumption is lowering the supply voltage. However, low supply voltages leads to reduced time performance if the transistor threshold voltage is not scaled accordingly. To solve this, technologies with reduced threshold voltage devices have emerged. Instead, in this paper we resort to a circuit technique based on floating gate devices in order to lower the threshold voltage. It allows fast operation of logic gates at a low supply voltage in standard technologies. The feasibility of the proposed technique is shown experimentally by a fabricated test chip working at a supply voltage of 0.4V.

Practical oscillation-based test in analog integrated filters: Experimental results
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Conference · IEEE International Workshop on Electronic Design, Test and Applications DELTA 2002
resumen     

This paper presents experimental results corresponding to the use of Oscillation-based Test (OBT) when applied to a switched-capacitor integrated filter. A universal biquad is used as an example to demonstrate the feasibility of the OBT technique.

Practical solutions for the application of the oscillation-based-test: Start-up and on-chip evaluation
D. Vázquez, G. Huertas, G. Léger, A. Rueda and J.L. Huertas
Conference · IEEE VLSI Test Symposium VTS 2002
resumen     

This paper presents practical solutions for two of the main topics arising when applying Oscillation-Based-Test: the start-up of the configured oscillator and the on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.

An integrated circuit for tissue impedance measure
A. Yufera, G. Léger, E.O. Rodríguez-Villegas, J.M. Muñoz, A. Rueda, A. Ivorra, R. Gómez, N. Noguera and J. Aguilo
Conference · Conference on Microtechnologies in Medicine & Biology IEEE-EMB 2002
resumen     

In this paper, the design of aa Integrated Circuit (IC) for the measurement of tissue impedance is presented. The chip is intended to be used in monitoring biomedical parameters in living bodies. Tissue impedance is one of these parameters which allows ischemia monitoring. The designed IC is used in a four-electrode based set-up in order to minimize the effect of electrode-electrolyte interface impedance. A needle shaped probe which contains the four electrodes for the impedance measurement and Integrated Circuits (ICs) required for excitation and measurement purpose have been designed, fabricated and tested in-vivo. The IC has been fabricated in a 0.8mum CMOS process, working at 3V of power supply. Test results have shown the circuit feasibility.

A mixed-signal design reuse methodology based on parametric behavioural models with non-ideal effects
A.J. Ginés, E. Peralías, A. Rueda, N.M. Madrid and R. Seepold
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2002
resumen     

Current System-on-Chip (SoC) designs incorporate an increasing number of mixed-signal components. Design reuse techniques have proved successful for digital design but these rules are difficult to transfer to mixed-signal design. A top-down methodology is missing but the low level of abstraction in designs makes system integration and verification a very difficult, tedious and complex task. This paper presents a contribution to mixed-signal design reuse where a design methodology is proposed based on modular and parametric behavioural components. They support a design process where non-ideal effects can be incorporated in an incremental way, allowing easy architectural selection and accurate simulations. A working example is used through the paper to highlight and validate the applicability of the methodology.

A continuous-time incremental analog to digital converter
R. Doldán, A. Yufera and A. Rueda
Conference · Symposium on Integrated Circuits and Systems Design SBCCI 2002
resumen     

In this paper, an incremental Analog-to-Digital Converter (ADC) designed as part of the signal-conditioning circuitry for tissue impedance measurement system is presented. Continuous-time design techniques has been used for that which a modified implementation of the conversion algorithm, with respect to its discrete-time counterpart, has been developed. In order to reduce the influence of the no-idealities, analog and digital corrections has been also implemented. A first prototype in 0.8mum CMOS technology has been fabricated and tested. Simulation and experimental results are reported.

Libros


Oscillation-Based-Test in Mixed-Signal Circuits
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Book · FRET, vol. 36, 452 p, 2006
resumen      link      

Oscillation-Based Test in Mixed-Signal Circuits presents the development and experimental validation of the structural test strategy called Oscillation-Based Test - OBT in short. The results here presented allow to assert, not only from a theoretical point of view, but also based on a wide experimental support, that OBT is an efficient defect-oriented test solution, complementing the existing functional test techniques for mixed-signal circuits.

Low-Voltage CMOS Log Companding Analog Design
F. Serra-Graells, A. Rueda and J.L. Huertas
Book · SECS, vol. 733, 192 p, 2003
resumen      link      

Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.

Capítulos de libros


Design of an energy efficient ZigBee transceiver
A. Ginés, R. Fiorelli, A. Villegas, R. Doldán, M. Barragán, D. Vázquez, A. Rueda and E. Peralías
Book Chapter · Mixed-Signal Circuits, pp 171-203, 2018
resumen      doi      

This chapter tries to summarize our experience in the development of the analog front-end part of 2.4 GHz ZigBee transceivers with the main objective of optimizing power consumption during normal operation in both reception and transmission modes. Other interesting design aspects, such as optimizing the transceiver protocol, the design of the digital subsystems, or managing the sleep modes, have not been included due to space limitation. To gather together the presented design ideas, the chapter concludes in Section 7.5 with an example of a complementary metal-oxide semiconductor (CMOS) integrated transceiver analog front-end. The competitive experimental performances for this integration endorse the employed design flow, procedures, and analysis.

A close-loop method for bio-impedance measurement with application to four and two-electrode sensor systems
A. Yúfera and A. Rueda
Book Chapter · New Developments In Biomedical Engineering, pp 263-286, 2010
resumen      doi      pdf

Biomedical Engineering is a highly interdisciplinary and well established discipline spanning across engineering, medicine and biology. A single definition of Biomedical Engineering is hardly unanimously accepted but it is often easier to identify what activities are included in it. This volume collects works on recent advances in Biomedical Engineering and provides a bird-view on a very broad field, ranging from purely theoretical frameworks to clinical applications and from diagnosis to treatment. 

Test of ΣΔ converters
G. Leger and A. Rueda
Book Chapter · Test and Diagnosis of Analogue, Mixed-Signal and RF Integrated Circuits, pp 235-276, 2008
resumen     

In this chapter, we have tried to provide insights into ΣΔ modulator tests. It has been shown that the ever-increasing levels of functionality integration, the ultimate expression of which is SoC, raise new problems on how to test embedded components such as ΣΔ modulators. These issues may even compromise the test feasibility, or at least they may displace test time from its prominent position in the list of factors that determine the overall test cost. It is clear that considerable research is still necessary to produce a satisfying solution, but the first steps are encouraging. In particular, we believe that solutions based on behavioural model-based BIST may greatly simplify the test requirements.

Oscillation-based test strategies
G. Huertas-Sánchez, G. Leger, D. Vázquez, A. Rueda and J.L. Huertas
Book Chapter · Test and Design-For-Testability in Mixed-Signal Integrated Circuits, pp 259-298, 2004
resumen      doi      

This chapter aims to present a structural test methodology using the so-called OBT technique. The conceptual bases of the OBT approach are presented as well as many practical details on its application to practical integrated circuits.

Behavioral modeling of multistage ADCs and its use for design, calibration and test
E. Peralías and A. Rueda
Book Chapter · Test and Design-for-Testability in Mixed-Signal Integrated Circuits, pp 163-214, 2004
resumen      doi      

This chapter provides a general model for the static behavior description of multistage ADCs that intends to be independent of the topologies and design techniques used. Furthermore, under this general behavior, results for the correction of its main errors will be extracted by means of calibration in the digital domain. Finally, two well-consolidated state-of-the-art techniques will be explained by using the developed mathematical description.

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