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Author: Avedillo de Juan , María J.
Year: Since 2002
All publications
Phase Transition FETs for Improved Dynamic Logic Gates
M.J. Avedillo, M. Jiménez and J. Núñez
Journal Paper - IEEE Electron Device Letters, first online, 2018
IEEE    DOI: 10.1109/LED.2018.2871855    ISSN: 0741-3106    » doi
[abstract]
Transistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. In addition to the replacement of the transistors in conventional static CMOS logic circuits, the distinguishing features of Phase Change FETs can be exploited in other application domains or can be useful for solving specific design challenges. In this paper, we take advantage of them to implement a smart dynamic gate in which undesirable contention currents are reduced, leading to speed advantage without power penalties.

Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jiménez, M.J. Avedillo and J. Núñez.
Conference - Conference on Ph.D Research in Microelectronics and Electronics PRIME 2018
[abstract]
Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.

Impact of the RT-level architecture on the power performance of tunnel transistor circuits
M.J. Avedillo and J. Núñez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 46, no. 3, pp 647-655, 2018
JOHN WILEY & SONS    DOI: 10.1002/cta.2398    ISSN: 0098-9886    » doi
[abstract]
Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer-level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.

Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
J. Nuñez and M.J. Avedillo
Journal Paper - IEEE Journal of the Electron Devices Society, vol. 5, no. 6, pp 530-534, 2017
IEEE    DOI: 10.1109/JEDS.2017.2737598    ISSN: 2168-6734    » doi
[abstract]
RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this paper, we analyze the limitations of typical TFET rectifier topologies associated with the forward biasing of their intrinsic diode and show that this can occur at relatively weak input signals depending on the specific characteristic of the used tunnel device. We propose a simple modification in the implementation of the rectifiers to overcome this problem. The impact of our proposal is evaluated on the widely used gate cross-coupled topology. The proposed designs exhibit similar peak PCE and sensitivity but significantly improve PCE for larger input signal amplitude and larger input power.

Insights into the Operation of Hyper-FET-Based Circuits
M.J. Avedillo and J. Nuñez
Journal Paper - IEEE Transactions on Electron Devices, vol. 64, no. 9, pp 3912-3918, 2017
IEEE    DOI: 10.1109/TED.2017.2726765    ISSN: 0018-9383    » doi
[abstract]
Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the I-ON/I-OFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called hyper-FET to simulate different circuits, and to analyze the impact of the degraded dc output voltage levels of hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements. We show that these estimations can reduce, cancel, or even lead to power penalties in low switching and/or low-frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design.

Exploring Logic Architectures Suitable for TFETs Devices
J. Núñez and M.J. Avedillo
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are critical for IoT development. Although they show higher ON currents than CMOS at low supply voltages, currently TFETs do not reach those exhibited by CMOS at its nominal supply voltage and so they have being identified to be competitive for moderate operating frequencies. However, in many cases, architectural choices are not taken into account when benchmarking them against CMOS. In this paper we claim that the logic architecture should be selected in order to take full advantage of the specific characteristics of these devices. Widely used circuits are designed and evaluated showing how properly tuning the logic architecture results in raising the frequency up to which TFETs are competitive or in increasing power savings at lower frequencies.

Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
J. Núñez and M.J. Avedillo
Journal Paper - IEEE Transactions on Nanotechnology, vol. 16, no, 1, pp 83-89, 2017
IEEE    DOI: 10.1109/TNANO.2016.2629264    ISSN: 1536-125X    » doi
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four MOSFET and FinFET transistors. The impact of logic depth, switching activity and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.

Complementary Tunnel Gate Topology to Reduce Crosstalk Effects
J. Núñez and M.J. Avedillo
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2016
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated.

Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits
M.J. Avedillo and J. Núñez
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2016
[abstract]
Tunnel transistors are one of the most attractive steep sub threshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, we analyze the impact of the logic depth into the power consumption and energy efficiency of logic circuits and show critical differences between tunnel transistors and CMOS technologies, due to the distinct delay versus supply voltages exhibited by each type of device. Obtained results show that reducing logic depth as a power reduction technique is more efficient for tunnel transistors circuits than for their CMOS counterparts. A simple model to estimate the power reductions achieved when using pipeline to cut down logic depth, and taking into account the power overheads associated to the pipelined registers is developed. It shows that in CMOS power benefits cancels with the incorporation of a number of flip-flops equal to the 5% of the number of gates in the original circuit while this number rises to 90% for tunnel circuits. Simulation experiments of a simple adder tree are carried out to validate our analysis. No power savings are obtained by the CMOS pipelined circuit while the TFET pipelined circuit saves 77% of power. The results of this work suggest that architectural issues should be considered in the evaluation of this type of transistors.

Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
J. Núñez and M.J. Avedillo
Journal Paper - IEEE Transactions on Electron Devices, vol. 63, no. 12, pp 5012-5020, 2016
IEEE    DOI: 10.1109/TED.2016.2616891    ISSN: 0018-9383    » doi
[abstract]
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas.

Experiencia en desarrollo de sistemas empotrados hardware-software como Trabajo Fin de Grado
J.M. Calahorro, L. Acasandrei, A. Barriga and M.J. Avedillo
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
[abstract]
Se presenta en esta comunicación el desarrollo de un Trabajo Fin de Grado (TFG) de la Titulación de Ingeniería Informática-Ingeniería de Computadores. El objetivo es mostrar la experiencia en el desarrollo de un TFG que aúne aspectos multidisciplinares, que permitan desarrollar en el alumno las capacidades adquiridas durante el proceso educativo en el Grado en Ingeniería de Computadores. En concreto se plantea la especificación de un sistema empotrado hardware-software dentro del campo de aplicación del reconocimiento de caras en imágenes y/o video, competitivo en términos de velocidad respecto a una implementación puramente software.

Hardware-Software Embedded Face Recognition System
M.J. Avedillo, A. Barriga, L. Acasandrei and J.M. Calahorro
Conference - International Conferences in Central Europe on Computer Graphics, Visualization and Computer Vision WSCG 2016
[abstract]
This paper describes the design and implementation of a hardware-software embedded system for face recognition applications in images and/or videos. The system has hardware components to speed up the face detection and recognition stages. It is a system suitable for applications requiring real-time, due that the response times are deterministic and bounded. The system is based on a previous implementation that had accelerated the image capturing process, and the face detection. This paper will focuses in the face recognition acceleration.

Assessing application areas for tunnel transistor technologies
M.J. Avedillo and J. Núñez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.

Improving robustness of dynamic logic based pipelines
H.J. Quintero, M.J. Avedillo and J. Núñez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the non-inverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its non-inverting feature.

Improving speed of tunnel FETs logic circuits
M.J. Avedillo and J. Núñez
Journal Paper - Electronics Letters, vol. 51, no. 21, pp 1702-1704, 2015
IEEE    DOI: 10.1049/el.2015.2416    ISSN: 0013-5194    » doi
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital tunnel FET circuits leading to delay degradation. A minor modification of the complementary gate topology to avoid the bootstrapping problem is proposed and its impact on speed at the circuit level is shown. Speed improvements up to 33% have been obtained for 8-bit ripple carry adders when implemented with the solution.

DOE Based High-Performance Gate-Level Pipelines
J. Núñez, M.J. Avedillo and H.J. Quintero
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2014
[abstract]
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the noninverting behavior of domino gates, there are also performance disadvantages when compared to inverting dynamic gates, which can be related to this feature. These penalties rise from the fact that in order to produce a logic one, a non-inverting gate requires one or more of its inputs to be also at logic one. We analyze the operation of gate-level pipelines implemented with domino and with Delayed Output Evaluation (DOE), an inverting dynamic gate we have recently proposed, and compare their performance. Using domino and DOE gates similar in terms of delay, improvements in operating frequencies around 50% have been obtained by the DOE pipelines.

Experimental validation of a two-phase clock scheme for fine-grained pipelined circuits based on monostable to bistable logic elements
J. Nuñez, M.L. Avedillo and J.M. Quintana
Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp 2238-2242, 2014
IEEE    DOI: 10.1109/TVLSI.2013.2283306    ISSN: 1063-8210    » doi
[abstract]
Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating two series connected negative differential resistance devices with a clock bias. This brief describes and experimentally validates a two-phase clock scheme for such MOBILE-based ultragrained pipelines. Its advantages over other reported interconnection schemes for MOBILE gates, and also over pure CMOS two-phase counterparts, are stated and analyzed. Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE circuit to have been reported with this interconnection architecture.

Novel dynamic gate topology for superpipelines in DSM technologies
J. Nuñez, M.J. Avedillo and J.M. Quintana
Conference - Euromicro Conference on Digital System Design DSD 2013
[abstract]
Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high throughput. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and the Carry-Merge chain of a Kogge-Stone adder is designed as an application example.

Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications
J. Núñez, M.J. Avedillo, J.M. Quintana and H.J. Quintero
Conference - Conference on the Design of Circuits and Integrated Systems DCIS 2013
[abstract]
Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high through-output. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and a gate per phase Carry Look Ahead adder is designed as an application example.

Novel pipeline architectures based on Negative Differential Resistance devices
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper - Microelectronics Journal, vol. 44, no. 9, pp 807-813, 2013
ELSEVIER    DOI: 10.1016/j.mejo.2013.06.012    ISSN: 0026-2692    » doi
[abstract]
Devices exhibiting Negative Differential Resistance (NDR) in their I-V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.

Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J. Nuñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference - IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
[abstract]
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an 'all MOS' version of one previously reported which uses Resonant Tunneling Diodes (RTDs). The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.

Two-phase RTD-CMOS pipelined circuits
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper - IEEE Transactions on Nanotechnology, vol. 11, no. 6, pp 1063-1066, 2012
IEEE    DOI: 10.1109/TNANO.2012.2213839    ISSN: 1536-125X    » doi
[abstract]
MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have been reported using different clock schemes including a four-phase strategy and a single-phase clock scheme. In particular, significant power advantages of single-phase RTD-CMOS MOBILE circuits over pure CMOS have been shown. This letter compares the RTD-CMOS realizations using a single clock and a novel two-phase clock solution. Significant superior robustness and performance in terms of power and area are obtained for the two-phase implementations.

Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications
J. Núñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2012
[abstract]
Monostable to Bistable (MOBILE) gates are very suitable for the implementation of gate-level pipelines which can be achieved without resorting to memory elements. MOBILE operating principle is implemented using two series connected Negative Differential Resistance (NDR) devices with a clocked bias. This paper describes and experimentally validates a two-phase clock scheme for such MOBILE based ultra-grain pipelines. Up to our knowledge it is the first MOBILE working circuit reported with this interconnection architecture. The proposed interconnection architecture is applied to the design of a 4-bit Carry Look-ahead Adder.

Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J. Núñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference - Iberchip XVIII Workshop IWS 2012
[abstract]
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an ¿all MOS¿ version of one previously reported which use Resonant Tunneling Diodes (RTDs) The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.

Compact and Power Efficient MOS-NDR Muller C-Elements
J. Núñez-Martínez, M. J. Avedillo and J.M. Quintana-Toledo
Conference - IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems DoCEIS 2012
[abstract]
Recently there is a renewed interest in the development of transistor circuits which emulate the Negative Differential Resistance (NDR) exhibited by different emerging devices like Resonant Tunneling Diodes (RTDs). These MOS-NDR circuits easily allow the prototyping of design concepts and techniques developed for such NDR devices. The importation of those concepts into transistor technologies can result in circuit realizations which are advantageous for some functionalities and application fields. This paper describes a Muller C-element which illustrates this statement which is inspired in an RTD-based topology. The required RTD is implemented by means of the MOS-NDR device. A 4-input Muller C-element has been fabricated and experimentally validated. The proposed circuit compares favorably with respect to a well-known conventional gate realization.

Domino inspired MOBILE networks
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper - Electronics Letters, vol. 48, no. 5, pp 292-293, 2012
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2011.3295    ISSN: 0013-5194    » doi
[abstract]
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported that alternates rising and falling edge-triggered MOBILE gates. A novel two-phase interconnection scheme resembling conventional domino pipelines is proposed and validated. It exhibits advantages in terms of speed with respect to both four-phase and single-phase interconnection schemes. In addition, the new architecture improves logic flexibility regarding the domino pipeline counterpart, since inverting and non-inverting stages can be interspersed.

Efficient realization of RTD-CMOS logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference - Great Lakes Symposium on VLSI GLSVLSI 2011
[abstract]
The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined. Lower average power and energy per cycle are obtained for RTD/CMOS implementations. Copyright © 2011 by ASME.

RTD-CMOS pipelined networks for reduced power consumption
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper - IEEE Transactions on Nanotechnology, vol. 10, no. 6, pp 1217-1220, 2011
IEEE    DOI: 10.1109/TNANO.2011.2157518    ISSN: 1536-125X    » doi
[abstract]
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work in this direction is required. In this letter, we compare RTD-CMOS and pure CMOS realizations of a logic gate network which can be operated in a gate-level pipeline. Significantly lower average power is obtained for RTD-CMOS implementations.

Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs
J. Nuñez, M.J. Avedillo and J.M. Quintana
Conference - SPIE Microtechnologies for the New Millennium 2011
[abstract]
The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. We compare RTD-CMOS and pure CMOS realizations of a network of logic gates which can be operated in a gate-level pipeline. Significant lower average power is obtained for RTD-CMOS implementations.

Simplified single-phase clock scheme for MOBILE networks
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper - Electronics Letters, vol. 47, no. 11, pp 648-649, 2011
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2011.0186    ISSN: 0013-5194    » doi
[abstract]
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required for this. A single-phase scheme is possible adding latches to the MOBILE gates. Proposed and experimentally validated is a new single-phase interconnection scheme that simplifies the inter-stage element, which translates in power, area and clock load advantages with respect to using latches.

Improved nanopipelined RTD adder using generalized threshold gates
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Journal Paper - IEEE Transactions on Nanotechnology, vol. 10, no. 1, pp 155-162 2011
IEEE    DOI: 10.1109/TNANO.2009.2035311    ISSN: 1536-125X    » doi
[abstract]
Many logic circuit applications of resonant tunneling diodes are based on the monostable-bistable logic element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e., these circuits are built from threshold gates (TGs). This paper describes the design of full adders (FAs), using TG-based circuit topologies. Both the selection of different MOBILE TG networks and the use of gates that can be considered extensions of the MOBILE TG are addressed. The FAs are applied to the design of nanopipelined carry propagations adders, which are evaluated and compared to a previously reported one, showing advantages in terms of speed, power, and power-delay product.

Redes MOBILE MOS-NDR operando con reloj de una fase
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference - Iberchip XVI Workshop IWS 2010
[abstract]
La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative Differential Resistance, NDR) resulta atractiva desde el punto de vista del diseño de circuitos, como ha sido demostrado por los circuitos que usan diodos basados en el efecto túnel resonante (Resonant Tunneling Diodes, RTDs). Ideas procedentes de diseños con RTDs pueden exportarse a un entorno 'todo CMOS' en el que la característica NDR se obtiene mediante transistores (MOS-NDR). En este artículo se proponen estructuras MOS-NDR para realizar puertas lógicas (Threshold Gates, TGs) que operan según el principio de operación MOBILE (MOnostable to BIstable Logic Element). Además, se demuestra que estas puertas pueden interconectarse para formar redes que operan en modo pipeline usando un esquema de reloj de una fase.

Analytic Approach to the Operation of RTD Ternary Inverters Based on MML
J. Núñez, J.M. Quintana and M.J. Avedillo
Book Chapter - Cutting Edge Nanotechnology, pp 97-112, 2010
INTECH    DOI: 10.5772/8847    ISBN: 978-953-7619-93-0    » doi
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaMultiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.

Evaluation of RTD-CMOS logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference - Euromicro Conference on Digital System Design DSD 2010
[abstract]
The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined fashion, thus allows estimating logic networks operating frequency. Lower power-delay products are obtained for RTD/CMOS implementations. © 2010 IEEE.

An improved RNS generator 2 n ± k based on threshold logic
H. Pettenghi, R. Chaves, L. Sousa and M.J. Avedillo
Conference - IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2010
[abstract]
This paper presents a new scheme for designing residue generators using threshold logic. This approach is based on the periodicity of the series of powers of 2 taken modulo 2 n± k. In addition, a new algorithm is proposed to obtain a new set of partitions which are more advantageous in terms of area and delay for the presented topology. Experimental results in the analized range of k and n show that new proposed circuits using the novel partitioning are 70% faster and provide area savings of 64%, when compared with similar circuits using the partitioning methods presented to date. © 2010 IEEE.

Single phase MOS-NDR mobile networks
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2010
[abstract]
Devices with an I-V characteristic exhibiting Negative Differential Resistance (NDR) are attractive from the circuit design point of view as it has been demonstrated by Resonant Tunneling Diodes (RTDs) circuits. Ideas coming from RTD-based designs can be exported to an "all CMOS" environment by using transistor circuits to generate the NDR characteristic (MOS-NDR). In this paper novel programmable MOS-NDRs are proposed and used to realize threshold logic gates on the basis of the MOnostable to BIstable Operating principle. It is shown that these gates can be connected to build up networks that are operated in a pipelined fashion using a single phase clock scheme.

Fast and area efficient multi-input Muller C-element based on MOS-NDR
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2009
[abstract]
A new multi-input Muller C-element based on a MOS-NDR device is proposed in this contribution. This design overcomes some drawbacks of previously proposed structures. A comparison in terms of area, delay and power consumption over another efficient CMOS Muller C-element circuit has been performed, resulting that our structure improves this performance.

Efficient realisation of MOS-NDR threshold logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper - Electronics Letters, vol. 45, no. 23, pp 1158-1159, 2009
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2009.1651    ISSN: 0013-5194    » doi
[abstract]
A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.

Operation limits for RTD-based MOBILE circuits
J.M. Quintana, M.J. Avedillo, J. Nuñez and H.P. Roldan
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 2, pp 350-363, 2009
IEEE    DOI: 10.1109/TCSI.2008.925943    ISSN: 1549-8328    » doi
[abstract]
Resonant-tunneling-diode (RTD)-based MOnostable-BIstable Logic Element (MOBILE) circuits operate properly in a certain frequency range. They exhibit both a minimum operating frequency and a maximum one. From a design point of view, it should be desirable to have gates with a correct operation from do up to the maximum operating frequency (i.e., without the minimum bound). This paper undertakes this problem by analyzing how transistors and RTDs interact in RTD-based circuits. Two malfunctions have been identified: the incorrect evaluation of inputs and the lack of self-latching operation. The difficulty to study these problems in an analytical way has been overcome by resorting to series expansions for both the RTD and the heterojunction field-effect transistor I-V characteristics in the points of interest. We have obtained analytical expression linking representative device parameters and technological setup, for a MOBILE-based circuit to operate correctly.

Transient Response in MOBILE-based Circuits
J.M. Quintana and M.J. Avedillo
Conference - IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2008
[abstract]
Abstract not avaliable

RTD based Logic Circuits using Generalized Threshold Gates
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference - IEEE Conference on Design of Circuits and Integrated Systems DCIS 2008
[abstract]
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates (TGs). The MOBILE realization of generalized threshold gates is being investigated. Multi-Threshold Threshold Gates (MTTGs) have been proposed which further increase the functionality of the original TGs. Recently, we have proposed a novel MOBILE circuit topology obtained by fundamental properties of threshold functions. This paper describes the design of n-bit adders using these novel MOBILE circuit topologies. A comparison with designs based on TGs and MTTGs is carried out showing advantages in terms of speed and power delay product and device counts.

Observation of Frequency Division and Chaos Behavior in a Laser Diode
B. Romeira, J.M.L. Figueiredo, T.J. Slight, L. Wang, E. Wasige, C.N. Ironside, J.M. Quintana and M.J. Avedillo
Conference - Conf. on Lasers and Electro-Optics/Quantum Electronics and Laser Science CLEO/QELS 2008
[abstract]
We report optical experimental frequency division and chaos results in a resonant tunneling diode laser diode driver configuration that forms a self-oscillating circuit. Circuit behavior and laser output results are well predicted using Lienardpsilas equation.

Analysis of the critical rise time in MOBILE-based circuits
J.M. Quintana and M.J. Avedillo
Conference - IEEE International Conference on Electronics, Circuits and Systems ICECS 2008
[abstract]
It is well known that there is a critical value for the rising time of the clocked bias signal which limits the operating speed of MOBILE-based circuits. This paper analyzes the transient response of a MOBILE-based follower and obtains analytical expressions to calculate the critical value for the rising time of the bias signal below which the circuit does not operate correctly. This analysis has been extended to more complex circuits such as threshold gates, we have also derived operating speed limits for these circuits. Results obtained have been validated through extensive simulations with HSPICE. © 2008 IEEE.

Design of RTD-based NMIN/NMAX gates
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE Conference on Nanotechnology, IEEE-NANO 2008
[abstract]
A novel implementation of NMIN/NMAX gates based on RTDs and transistors is presented. In this paper we will derive the relations that circuit representative parameters must verify to obtain a correct behaviour by means of the principles of the Monostable-to-Multistable Logic (MML). HSPICE simulations will be used to check our theoretical results. © 2008 IEEE.

Synchronisation and chaos in a laser diode driven by a resonant tunnelling diode
B. Romeira, J.M.L. Figueiredo, T.J. Slight, L. Wang, E. Wasige, C.N. Ironside, J.M. Quintana and M.J. Avedillo
Conference - Conference on Semiconductor Integrated Optoelectronics SIOE 2008
[abstract]
The authors report on a hybrid integration of a resonant tunnelling diode laser diode driver configuration that can operate as a self-oscillating circuit, and when externally perturbed shows regions of frequency division and frequency multiplication, quasi-peRíodic and chaotic oscillations, both in the optical and electrical outputs. The authors also demonstrate that this optoelectronic circuit is well described as a Lienard's oscillator. The synchronisation capabilities of the circuit have potentially novel functions for optical communications systems including clock recovery, clock division and data encryption.

Limits to a correct operation in RTD-based ternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2008
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.

A novel contribution to the RTD-based threshold logic family
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference - International Symposium on Circuits and Systems ISCAS 2008
[abstract]
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates. More recently, generalized threshold gates, also suitable to be realized with MOBILE RTD structures, are being investigated. In this paper we propose a novel MOBILE circuit topology obtained by exploiting threshold logic concepts and properties. A comparison in terms of speed and power performance between the proposed topologies and previous reported ones is carried out.

Limits to a correct evaluation in RTD-based quaternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - International Symposium on Multiple-Valued Logic ISMVL 2007
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML quaternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.

A quasi-differential quantizer based on SMOBILE
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - Symposium on Integrated Circuits and Systems Design SBCCI 2007
[abstract]
A quasi-differential quantizer based on a Symmetric-MOBILE (SMOBILE) configuration is proposed and compared to traditional structures based on MOBILE. This novel structure is adequate for high frequency operation since it can operate at a double clock-rate. A previous analysis before any frequency study should be done in order to obtain the correct operation region. In this paper, this region is analyzed for the proposed quantizer and it is compared to the corresponding ones based on MOBILE. The obtained results show that the correct operation regions are very similar, thus the advantages regarding to the operation frequency make our proposal very attractive.

Operation limits in RTD-based ternary quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - Great Lakes Symposium on VLSI GLSVLSI 2007
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary quantizer, and determines the relations that circuit representative parameters must verify to obtain a correct DC operation.

Holding preserving in RTD-based multiple-valued quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE Conference on Nanotechnology IEEE-NANO 2007
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are of the basis of advanced circuits for communications. The operation of a quantizer has two steps: sampling and holding. Once the quantizer samples the signal, it must maintain the sampled value even if the input changes. However, holding property is not inherent to RTD-based MML circuit topologies. A procedure to obtain the relation between circuit parameters in order to achieve a correct operation is described.

Correct operation in SMOBILE-based quasi-differential quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - European Conference on Circuit Theory and Design ECCTD 2007
[abstract]
A quasi-differential quantizer based on a Symmetric-MOBILE (SMOBILE) configuration is proposed and compared to traditional structures based on MOBILE. This novel structure is adequate for high frequency operation since it can operate at a double clock-rate. A previous analysis before any frequency study should be to obtain the correct operation region. In this paper, this region is analyzed for the proposed quantizer and it is compared to the corresponding based on MOBILE. The obtained results show that the correct operation regions are very similar, thus the advantages regarding to the operation frequency make our proposal very attractive.

Non return mobile logic family
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference - International Symposium on Circuits and Systems ISCAS 2007
[abstract]
Many logic circuit applications of RTDs are based on the MOnostable-BIstable Logic Element (MOBILE). Cascaded MOBILE gates are operated in a pipelined fashion using a four phase overlapping clocking scheme. To improve the robustness of MOBILE networks, a simpler clock scheme is desirable. We have demonstrated that removing the return to a "precharge" voltage behaviour of conventional MOBILE gates, operation with a single phase clock scheme is possible. In this paper, a non return MOBILE logic family is described and its single phase operation shown. A comparison between return and non return gates is carried out showing that in addition to the simpler clock scheme required, speed and power-delay product improvements can be achieved with the proposed ones.

Correct DC operation in RTD-based ternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE International Conference of Nano/Micro Engineered and Molecular Systems IEEE-NEMS 2007
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.

Operation limits for MOBILE followers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE Conference on Nanotechnology IEEE-NANO 2006
[abstract]
This paper analyses how the presence of the HFET transistor modifies the DC operation of a Resonant Tunneling Logic Follower MOBILE, and can prevent its correct operation. The difficulty of an analytical study for the resulting circuit has been overcome by resorting to series expansions for both the RTD and the HFET I-V characteristics in the points of interest. We have obtained analytical expressions describing the regions where a MOBILE follower operates correctly. © 2006 IEEE.

Monostable-bistable transition logic elements: Threshold logic vs. boolean logic comparison
D. Bol, J.D. Legat, J.M. Quintana and M.J. Avedillo
Conference - IEEE International Conference on Electronics, Circuits and Systems ICECS 2006
[abstract]
Threshold logic is an interesting alternative to Boolean logic in the field of high-performance arithmetic circuits. It offers reduced logic depth and gate count. A competitive implementation of threshold logic uses MOnostable-BIstable transition Logic Elements (MOBILE). The aim of this contribution is to evaluate a specific implementation of MOBILE based on Negative-Differential-Resistance (NDR) MOS structures. This implementation is compared as fairly as possible to Boolean-logic circuits. Simulations of majority-voting gates with 1 to 7 inputs are carried out using the same CMOS process for both logic styles. Results show the improvement brought by the MOBILE implementation regarding to area, power consumption and power-delay product, when the number of inputs becomes large. © 2006 IEEE.

Limits to a correct evaluation in RTD-based ternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE International Conference on Electronics, Circuits and Systems ICECS 2006
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a correct DC evaluation is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct operation.

Design guides for a correct DC operation in RTD-based threshold gates
J.M. Quintana, M.J. Avedillo and J. Núñez
Conference - Conference on Digital System Design - Architectures, Methods and Tools EUROMICRO 2006
[abstract]
A correct DC operation is essential before analyzing other aspects of the circuit behavior. This paper analyzes how the presence of the HFET transistor modifies the DC operation of follower circuits based on MOBILE, and can prevent its correct operation. On the basis of this analysis, guidelines for the design of threshold gates which are implemented as a generalization of the follower circuit topology are derived.

Self-latching operation limits for MOBILE circuits
J.M. Quintana, M.J. Avedillo and H. Pettenghi
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2006
[abstract]
One of the most attractive feature of MOBILE-based circuits is their self-latcbing operation, which allows pipelining at the gate level, and thus very high tbrough-output, without any area overhead associated to the addition of the latches. However, the self-latching behavior is not inherent to the practical circuit topologies employed to implement MOBILE circuits. This paper reports on very simple MOBILE structures supporting this statement. The analysis performed allow extracting design guidelines to guarantee the required behavior.

DC correct operation in MOBILE inverters
J.M. Quintana, M.J. Avedillo and J. Núñez
Conference - IEEE International Midwest Symposium on Circuits and Systems MWSCAS 2006
[abstract]
The verification of an appropriate DC behavior is essential before analyzing other aspects of the operation of a circuit. This paper analyses the case of MOBILE inverters and determines the relations that circuit representative parameters (such as the relation of the ratio of gate width to the gate length of the HFET, and the area factors in the RTDs) must verify to obtain a MOBILE inverter which operates correctly. The difficulty of an analytical study has been overcome by resorting to series expansions for both the RTD and the HFET I-V characteristics in the points of interest, so obtaining simplified descriptions for describing these behaviors.

Single phase clock scheme for mobile logic gates
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Journal Paper - Electronics Letters, vol. 42, no. 24, pp 1382-1383, 2006
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el:20062393    ISSN: 0013-5194    » doi
[abstract]
Many logic circuit applications of resonant tunnelling diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Cascaded MOBILE gates are operated in a pipelined fashion using a four phase overlapping clocking scheme. To improve the robustness of MOBILE networks, a simpler clock scheme is desirable. It is demonstrated that a network of MOBILE gates can be operated with a single clocked bias signal. Both schemes are compared.

Increased logic functionality of clocked series-connected RTDS
M.J. Avedillo, J.M. Quintana and H.P. Roldan
Journal Paper - IEEE Transactions on Nanotechnology, vol. 5, no. 5, pp 606-611, 2006
IEEE    DOI: 10.1109/TNANO.2006.880889    ISSN: 1536-125X    » doi
[abstract]
The augmentation of transistor technologies with resonant tunnelling diodes (RTDs) has demonstrated improved circuit performance. The negative differential resistance exhibited by these devices can be exploited to increase the functionality implemented by a single gate in comparison to transistor-only technologies. Complex threshold gates (TGs) are efficiently realized by resorting to the operation principle of the clocked series connection of a pair of RTDs (MOBILE). This paper focuses the implementation of logic blocks using RTDs and transistors which further increase the functionality of previously reported topologies. Multithreshold-threshold gates (MTTGs) is the logic concept underlying the proposed realizations. The MOBILE principle is extended to three or more RTDs in series which allows us to implement MTTGs. Novel and extremely compact realizations of programmable gates using the MTTG topology are presented. A number of logic blocks useful for digital design are shown and their operation is verified through simulation with extensively validated models for actual devices.

Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors
M.J. Avedillo, J.M. Quintana and H. Pettenghi
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 5, pp 334-338, 2006
IEEE    DOI: 10.1109/TCSII.2005.862280    ISSN: 1057-7130    » doi
[abstract]
One of the most attractive features of MOBILE-based circuits is their self-latching operation, which allows pipelining at the gate level, and thus very high through-output, without any area overhead associated to the addition of the latches. However, the self-latching behavior is not inherent to the practical circuit topologies employed to implement MOBILE circuits. This paper reports on very simple MOBILE structures supporting this statement. The analysis performed is useful in extracting design guidelines to guarantee the required behavior.

Holding Dissapearance in RTD-based Quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - European Nano Systems Worshop ENS 2005
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. The operation of such quantizer has two steps : sampling and holding. Once the quantizer samples the signal, it must maintain the sampled value even if the input changes. However, holding property is not inherent to MML circuit topologies. This paper analyses the case of an MML ternary inverter used as a quantizer, and determines the relations that circuit representative parameters must verify to avoid this malfunction.

New circuit topology for logic gates based on RTDs
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference - IEEE Conference on Nanotechnology IEEE-NANO 2005
[abstract]
The augmentation of transistor technologies with Resonant Tunnelling Diodes (RTDs) has demonstrated improved circuit performance and it has been claimed that it could be the way to extend lifetime of current technologies. Thus the research on circuit topologies using RTDs and transistors is of critical importance for these emergent technologies. In particular, threshold logic gates (TGs) and multi threshold gates (MTTGs) have been efficiently implemented. In this Letter we propose a novel circuit topology to implement MTTGs which exhibits advantages in terms of speed and power consumption with respect to a previously reported circuit. A comparison between both topologies is carried out for an useful logic block: a gate which simultaneously implements the EXOR and the NAND functions. ©2005 IEEE.

Using multi-threshold threshold gates in RTD-based logic design: A case study
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference - European Nano Systems Worshop ENS 2005
[abstract]
The basic building blocks for resonant tunneling diode (RTD) logic circuits are threshold gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, TGs can be implemented as efficiently as conventional ones, but realize more complex functions. Recently, RTD structures implementing multi-threshold threshold gates (MTTGs) have been proposed which further increase the functionality of the original TGs while maintaining their operating principle and allowing also the implementation of nanopipelining at the gate level. This paper describes the design of n-bit adders using these MTTGs. A comparison with a design based on TGs is carried out showing advantages in terms of power consumption and power delay product. (C) 2007 Elsevier Ltd. All rights reserved.

Novel improved RTD-based implementation of multi-threshold logic gates
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference - International Conference on PhD Research in Microelectronics and Electronics PRIME 2005
[abstract]
The augmentation of transistor technologies with Resonant Tunnelling Diodes (RTDs) has demonstrated improved circuit performance and it has been claimed that it could be the way to extend lifetime of current technologies. Thus the research on circuit topologies using RTDs and transistors is of critical importance for these emergent technologies. In particular, threshold logic gates (TGs) and multi threshold gates (MTTGs) have been efficiently implemented. In this paper we propose a novel circuit topology to implement MTTGs which exhibits advantages in terms of speed and power consumption with respect to the previously reported circuit. A comparison between both topologies is carried out for an useful logic block: a gate which simultaneously implements the EXOR and the NAND functions.

Logic models supporting the design of MOBILE-based RTD circuits
M.J. Avedillo,J.M. Quintana and H. Pettenghi
Conference - IEEE International Conference on Application-Specific Systems, Architecture and Processors ASAP 2005
[abstract]
Threshold logic is a computational model widely used in the design of Resonant Tunnelling Diodes (RTDs) based circuits, i.e. these circuits are built from threshold gates. This paper explores two other computational models, Generalized Threshold Gates (GTG) and Multi-Threshold Threshold Gates (MTTGs), also suitable to be realized with MOBILE based RTD structures. Circuits implementing them are described Both logic models are generalizations of threshold logic and so the proposed circuit topologies further increase the functionality of the original TGs. Implementations of a non threshold function with the GTG and MTTG topologies are shown and compared.

Robust frequency divider based on resonant tunneling devices
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2005
[abstract]
The behaviour of a novel and extremely compact resonant tunnelling diode (RTD)-based circuit able to implement a frequency divider is studied. It exhibits very high operating frequency and low power consumption. Compared to a previous similar reported circuit, it has wider operation windows, narrower quasi-peRíodicity regions and an higher division factor for the driver frequency, while maintaining the extremely high operating frequency, simplicity, and division factor tunability by selection of circuit parameters.

Analysis of frequency divider RTD circuits
J.M. Quintana and M.J. Avedillo
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 10, pp 2234-2247, 2005
IEEE    DOI: 10.1109/TCSI.2005.852918    ISSN: 1057-7122    » doi
[abstract]
The behavior of a novel circuit topology able to implement a frequency divider is studied. This circuit is composed of a resonant tunnelling diode (RTD), an inductor, and a capacitor, so it exhibits a very high operating frequency and low power consumption. It employs the peRíod-adding sequences which appear in its bifurcation diagram to perform the frequency division. Compared to a previously reported similar circuit, it has wider operation windows and a higher division factor for the driver frequency, while maintaining the extremely high operating frequency, its simplicity, and the division factor tunability through the selection of circuit parameters. Simulation results using the HSPICE RTD model from project LOCOM as well as several realistic parasitics elements are given, which confirm the theoretical capabilities previously analyzed.

Transistor critical sizing in MOBILE follower
J.M. Quintana and M.J. Avedillo
Journal Paper - Electronics Letters, vol. 41, no. 10, pp 583-584, 2005
IEEE    DOI: 10.1049/el:20050388    ISSN: 0013-5194    » doi
[abstract]
Analyses are presented of how the presence of the HFET transistor modifies the DC operation of a resonant tunnelling logic follower MOBILE. The difficulty of an analytical study for the resulting circuit has been overcome by resorting to simplified descriptions for both the RTD and the HFET I-V characteristics. We have obtained an analytical expression for the relation of the ratio of gate width to the gate length of the HFET below which a theoretically well designed follower does not operate correctly.

Useful logic blocks based on clocked series-connected RTDs
H. Pettenghi, M.J. Avedillo and J.M. Quintana
Conference - IEEE Conference on Nanotechnology IEEE-NANO 2004
[abstract]
This paper presents novel and extremely compact implementations, based of the multi-threshold threshold gate concept, for some useful building blocks for logic design. The circuits consist of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs). They can be used in nanopipelined architectures enabling high frequency operation of systems.

A threshold logic synthesis tool for RTD circuits
M.J. Avedillo and J.M. Quintana
Conference - Symposium on Systems on Digital System Design EUROMICRO 2004
[abstract]
Functional devices and circuits based on Resonant Tunnelling Diodes (RTDs) are receiving much attention since they allow high speed and/or low power operation. RTDs exhibit a negative differential resistance in their current-voltage characteristic which can be exploited to significantly increase the functionality implemented by a single gate in comparison to other technologies. In particular they have proven to efficiently implement threshold gates which are a generalization of conventional boolean gates. Suitable logic synthesis tools are required to handle these complex building blocks in order to translate the advantages of this emergent technology to the circuit and system levels. This paper describes an efficient approach to the automatic design of networks of threshold gates from functional specifications. Results for widely used logic functions and standard benchmark circuits are reported.

Programmable logic gate based on resonant tunneling devices
J.M. Quintana, M.J. Avedillo and H. Pettenghi
Conference - International Symposium on Circuits and Systems ISCAS 2004
[abstract]
This paper presents a novel and extremely compact circuit able to implement a two-input programmable gate on the basis of the multi-threshold threshold gate concept. The circuit consists of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs). We provide detailed analysis on circuit design and simulation of such a programmable gate.

RTD-based compact programmable gates
J.M. Quintana, M.J. Avedillo and H. Pettenghi
Conference - IEEE International Joint Conference on Neural Networks IJCNN 2004
[abstract]
This paper presents novel and extremely compact implementations of programmable gates on the basis of the multi-threshold threshold gate concept. The circuit consists of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs) and its operating principle is based on the controlled quenching of clocked series-connected RTDs. The proposed generic circuit topology is presented and the methodology to design specific programmable gates is introduced. A number of programmable gates are shown and their operation is validated.

A practical parallel architecture for stacks filters
M.J. Avedillo, J.M. Quintana, H. El Alami and A. Jiménez-Calderón
Journal Paper - Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, vol. 38, no. 2, pp 91-100, 2004
KLUWER ACADEMIC    DOI: 10.1023/B:VLSI.0000040422.03985.04    ISSN: 0922-5773    » doi
[abstract]
Stack filters belong to the class of non-linear filters and include the well-known median filter, weighted median filters, order statistic filters and weighted order statistic filters. Any stack filter can be implemented by using the parallel threshold decomposition architecture which allows implementing their non-linear processing by means of a collection of identical binary filters (Boolean logic circuits). Although it is conceptually simple and useful to study the filter properties, this architecture is not practical for direct hardware implementation because as many as (M-1) binary filters are required for a M-valued input signal and M is large in many applications. In this paper we introduce a new parallel architecture for stack filter implementations. The complexity is now proportional to the window width L of the filter, instead of to M. In most applications L is much smaller than M which translates into efficient hardware implementations. The attractive characteristic of ease of design exhibited by the threshold decomposition architecture is kept. In fact, for a given stack filter both in the conventional implementation and in the proposed one, the same binary filter is required. The key concept supporting the new architecture is a modified decomposition scheme which generates L binary signals for a multi-valued input. As an application example, a complex WOS filter is designed and prototyped in an FPGA.

Pass-transistor based implementations of threshold logic gates for WOS filtering
M.J. Avedillo, J.M. Quintana and R. Jiménez-Naharro
Journal Paper - Microelectronics Journal, vol. 35, no. 11, pp 869-873, 2004
ELSEVIER    DOI: 10.1016/j.mejo.2004.07.006    ISSN: 0026-2692    » doi
[abstract]
This paper presents a systematic procedure to implement threshold functions by using a pass-transistor network. A main feature of the threshold gates (TGs) produced by this technique is that they do not exhibit the fan-in limitations usual when other implementation techniques are used. Thus, they are especially useful for Weighted Order Statistical (WOS) filters because the binary filters required are threshold functions which usually present a high total sum of weights. A WOS filter with its binary filters implemented as pass-transistor TGs is demonstrated in an standard 0.35 mum CMOS technology at 3.3 V. The filter shows a sample frequency well over 100 MHz at the nominal process condition and it is cheaper, faster and consumes less power than a conventional approach. (C) 2004 Elsevier Ltd. All rights reserved.

Nonlinear dynamics in frequency divider RTD circuits
J.M. Quintana and M.J. Avedillo
Journal Paper - Electronics Letters, vol. 40, no. 10, pp 586-587, 2004
IEEE    DOI: 10.1049/el:20040409    ISSN: 0013-5194    » doi
[abstract]
A novel and extremely compact circuit topology able to implement a selectable frequency divider using the peRíod-adding sequences which appear in the bifurcation diagram for the circuit is presented. It is based on resonant tunnelling devices (RTDs), so allowing very high operating frequency and a low power consumption. Compared to a previous similar reported circuit, it has wider operation windows, narrower chaos regions and a higher division factor.

Weighted order statistics filter for real-time signal processing applications based on pass transistor logic
M.J. Avedillo, J.M. Quintana and H. El Alami
Journal Paper - IEEE Proceedings-Circuits Devices and Systems, vol. 151, no. 1, pp 31-36, 2004
IEEE    DOI: 10.1049/ip-cds:20040210    ISSN: 1350-2409    » doi
[abstract]
The authors describe the rationale of the design of complex weighted order statistics filters (WOS filters) suitable for real-time signal processing applications. It is based on a simple stack-like architecture that decomposes the M-valued signals into a reduced number of binary signals which are filtered by identical boolean logic circuits (binary filters). The main distinguishing feature of the proposed procedure is the efficient implementation of both the decomposition stage and the binary filters. The former is achieved on the basis of introducing a new decomposition scheme which can be economically translated to hardware. The latter comes from realising that the binary filters required for WOS filtering are threshold functions and from the development of a systematic methodology for building pass-transistor networks that implement them. Results for a complex example filter show a sample frequency of over 175 MHz in a 0.35 mum MOS technology at 3.3 V.

Simplified Reed-Muller expressions for residue threshold functions
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Journal Paper - Circuits Systems and Signal Processing, vol. 23, no.1, pp 45-56, 2004
BIRKHAUSER BOSTON INC    DOI: 10.1007/s00034-004-7003-7    ISSN: 0278-081X    » doi
[abstract]
Residue threshold functions are a broad class of symmetric functions that include all the unit-weighted threshold functions. In this paper, we investigate the complexity of the Reed-Muller (RM) expressions for these functions. We prove that an important subclass of the functions has very simple RM expansions and determine the conditions that define such a subclass. Additionally, we show that such an expansion is also the optimal one concerning its polarity. As an interesting practical application, an analysis of the RM expansion of the output functions for parallel counters is performed.

Design of residue generators using threshold logic
J.M. Quintana, M.J. Avedillo and H. Pettenghi
Conference - International Midwest Symposium on Circuits and Systems MWSCAS 2003
[abstract]
A new design for residue generators modulo 3 is presented. It resorts to the potential of the computational model which uses threshold gates to significantly reduce both the complexity and depth of the resulting circuit.

A LP-LV high performance monolitic DTMF receiver with on-chip test facilities
D. Vázquez, G. Huertas, M.J. Avedillo, J.M. Quintana, A. Rueda and J.L. Huertas
Conference - Conference on VLSI Circuits and Systems 2003
[abstract]
This paper presents a mixed-signal DTMF receiver implemented in a double-poly double-metal 0.6um technology able to operate in the range of 2.7V-5V of voltage supply with a low current consumption (<1mA). An smart digital detector and decoder algorithm provides a very good speech immunity. On-chip test facilities for the analog part have.. been incorporated into the chip. A modified opamp (called sw-opamp) has been used to provide external accessing to inputs and outputs of the main analog blocks for off-line testing purposes. The so-called Oscillation-Based-Test (OBT) has also been integrated to perform a structural testing of the analog part. The additional cost of such on-chip test facilities is very small: just one extra pin and an area overhead of around 7%. Experimental results demonstrate the good performance of the design and the feasibility of the testing approaches.

VLSI implementations of threshold logic - A comprehensive survey
V. Beiu, J.M. Quintana and M.J. Avedillo
Journal Paper - IEEE Transactions on Neural Networks, vol. 14, no. 5, pp 1217-1243, 2003
IEEE    DOI: 10.1109/TNN.2003.816365    ISSN: 1045-9227    » doi
[abstract]
This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

Multi-threshold threshold logic circuit design using resonant tunnelling devices
M.J. Avedillo, J.M. Quintana, H. Pettenghi, P.M. Kelly and C.J. Thompson
Journal Paper - Electronics Letters, vol. 39, no. 21, pp 502-1504, 2003
IEEE    DOI: 10.1049/el:20030989    ISSN: 0013-5194    » doi
[abstract]
A novel and extremely compact circuit topology able to implement a gencralised threshold logic function with two thresholds is presented. The circuit consists of resonant tunnelling diodes and heterostructure field effect transistors.

Review of capacitive threshold gate implementations
V. Beiu, M.J. Avedillo and J.M. Quintana
Conference - Joint Int. Conf. on Artificial Neural Networks ICANN 2003/Int. Conf. on Neural Inf. Processing ICONIP 2003
[abstract]
This is an in-depth survey paper on capacitive hardware implementations of threshold logic gates. The different VLSI solutions include the switched capacitor and the floating gate and their variations. It will be shown how the distinct original proposals from both categories have evolved to become quite similar. The problems with this kind of implementations are pointed out, and their applications are discussed.

Threshold-logic-based design of compressors
J.M. Quintana, M.J. Avedillo, E. Rodríguez-Villegas and A. Rueda
Conference - IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
[abstract]
The design of efficient compressor circuits is a key problem in the design of high-performance applications where the impact of carry propagation must be reduced as much as possible. Examples of application for these compressors extend from arithmetic units such as parallel multipliers to high-performance, high-capacity digital neural networks (DNNs). This paper proposes new, threshold logic based, compressors to improve the delay in the critical signal path. Optimal design of such compressors has been addressed in both logical and electrical directions and our results show that such compressors have the best performance in delay and power-delay product when compared to conventional implementations.

Simplified Reed-Muller expressions for residue threshold functions
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
Residue threshold functions are a broad class of boolean functions which includes all the unit-weighted threshold functions. In this Paper we investigate the complexity of the Reed-Muller (RM) expressions for these functions. We prove that an important subclass of them have very simple RM expansions and determine the conditions that define it. As an interesting practical application, we show that the output functions of parallel counters belong to this subclass.

Simple parallel weighted order statistic filter implementations
M.J. Avedillo, J.M. Quintana and E. Rodríguez-Villegas
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
This paper describes a simple parallel architecture for the implementation of Weighted Order Statistic Filters (WOS), an important class of digital non-linear filters. The new architecture combines the design easiness of stack architectures with the area efficiency of those based in ordering matrices. It decomposes the M-valued signals into a reduced number of binary signals which are filtered by identical boolean logic circuits. Both area-efficient and fast implementations are obtained straight-forward from filter specifications. The design of a complex WOS filter is described. Results show a sample frequency over 60 Mhz in a 0.35mum MOS technology.

An encoding technique for low power CMOS implementations of controllers
M. Martínez, M.J. Avedillo, J.M. Quintana, M. Koegst, S. Rulke and H. Susse
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2002
[abstract]
Power consumption is becoming one of the most critical parameters in VLSI design. In this paper we describe a novel state assignment algorithm targeting towards low power CMOS realizations of controllers. The main features of the new approach can be summarized as follows: 1) flexible column encoding strategy which allows handling the area and the register activity cost functions separately and 2) preliminary analysis of the FSM to control relative weight of each cost function. Experimental results show that on average there is a 25% reduction in power consumption compared to an standard tool and without area penalty.

COPAS: A new algorithm for the partial input encoding problem
M. Martinez, M.J. Avedillo, J.M. Quintana and J.L. Huertas
Journal Paper - VLSI Design, vol. 14, no. 2, pp 171-181, 2002
TAYLOR & FRANCIS    DOI: 10.1080/10655140290010088    ISSN: 1065-514X    » doi
[abstract]
Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols should be chosen to optimize the final implementation. Conventionally, this input encoding (IE) problem has been solved in a two-step process. First step generates constraints on the relationship between codes for different symbols, called group constraints. In a following step, symbols are encoded such that constraints are satisfied. This paper addresses the partial input encoding problem (PIE), a variation of the IE problem which generates codes of minimum length. The role of group constraints within the framework of the PIE problem has been questioned. This paper describes an algorithm that unlike conventional approaches, which try to maximize the number of satisfied constraints, targets the economical implementation of each input constraint. The proposed approach is based on a powerful heuristic that produces high quality results in shorter time compared to previous algorithm.

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