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Author: Huertas Díaz , José L.
Year: Since 2002
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Monitoring Tissue Evolution on Electrodes with Bio-Impedance Test
A. Maldonado, P. Pérez, G. Huertas, A. Yúfera, A. Rueda, and J.L. Huertas
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2016
[abstract]
A technique for real-time monitoring of bio-impedances using a Voltage Oscillation (VO) methodology is proposed. The main idea relies on connecting the bio-system in such a way that a suitable electrical oscillator, which only uses a DC power source, is built. Thanks to the employed electrical models, the oscillation parameters can be directly related to the biological test. System simulations show that the impedance values of a tissue, called herein Zx, can be determined by measuring the actual frequency and amplitude of the proposed VO system, being possible to select the frequency range to optimize the system sensitivity.

Experiencia de puesta en marcha y desarrollo de un Máster on-line en Microelectrónica
A.J. Acosta, A. Barriga, B. Pérez and J.L. Huertas
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
[abstract]
Desde octubre de 2008 la Universidad de Sevilla oferta el título oficial de ‘Máster Universitario en Microelectrónica, Diseño y Aplicaciones de Sistemas Micro/nanométricos’. Dicho máster tiene, como característica diferenciadora respecto a la práctica totalidad de cursos similares existentes, la peculiaridad de ser impartido on-line. En su momento de aparición fue una auténtica novedad, que supuso un extraordinario reto, tanto en su puesta en marcha como en su desarrollo día a día, ya que aúna las características y problemática de realizar a la vez docencia a distancia y de contenido técnico muy especializado. Esta comunicación describe las características y la experiencia de puesta en marcha y desarrollo de un título exitoso en esta área.

Cell-Culture Measurements using Voltage Oscillations
A. Maldonado, P. Pérez, G. Huertas, A. Yúfera, A. Rueda and J.L. Huertas
Conference - IEEE Latin American Symposium on Circuits and Systems LASCAS 2016
[abstract]
A comprehensive system for real-time monitoring of a set of cell-cultures using a Voltage Oscillation (VO) methodology is proposed. The main idea is to connect the bioelectrical elements (electrodes&cell-culture) in such a way that sequentially a suitable electrical oscillator, which only uses a DC power source, is built. Using the employed electrical models given in [1, 2], the attained oscillation parameters (frequency and amplitude) can be directly related to the biological test. A digital circuitry is developed to pick-up the experimental measurements, which are gathered and shown in real-time in a web application.

From voltage oscillations to tissue-impedance measurements
A. Maldonado, P. Perez, G. Huertas, A. Yufera, A. Rueda and J.L. Huertas
Conference - IEEE Biomedical Circuits and Systems Conference BioCAS 2015
[abstract]
A technique for real-time monitoring of bio-impedances using a Voltage Oscillation (VO) methodology is proposed. The main idea relies on connecting the bio-system in such a way that a suitable electrical oscillator, which only uses a DC power source, is built. Thanks to the employed electrical models, the oscillation parameters can be directly related to the biological test. System simulations show that the impedance values of a tissue, called herein Zx, can be determined by measuring the actual frequency and amplitude of the proposed VO system, being possible to select the frequency range to optimize the system sensitivity.

Towards Bio-Impedance Based Labs: A Review
P. Pérez, A. Maldonado, A. Yúfera, G. Huertas, A. Rueda and J.L. Huertas
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
Conference Paper

Del electrón al chip
G. Huertas, L. Huertas and J.L. Huertas
Book - 142 p, 2015
CSIC    ISBN: 978-84-00-09988-6    » link
[abstract]
¿Qué hay detrás de la revolución tecnológica a la que estamos expuestos? La televisión, los ordenadores. Los teléfonos móviles o los GPS son dispositivos con numerosas aplicaciones informáticas que usamos cada día. Hablamos con familiaridad de Facebook, WhatsApp, Twitter, Instagram y un sinfín de programas que han cambiado modos y hábitos sociales; pero ¿tenemos una idea de lo que hay detrás de esos programas y qué les permite cumplir su función? En realidad, todas esas herramientas dependen para su funcionamiento de procesos de conducción eléctrica; resumiendo mucho, del movimiento de una partícula que ahora nos parece familiar: el electrón. Pero el electrón no es una realidad visible para nosotros; solo lo son los equipos electrónicos y, en ellos, como máximo, sus componentes básicos: los chips. Este libro pretende hacer llegar al lector la relación de esos dos conceptos para entender el camino que nos ha conducido hasta estos instrumentos tecnológicos que tanto utilizamos.

The bio-oscillator: A circuit for cell-culture assays
G. Huertas, A. Maldonado, A. Yufera, A. Rueda and J.L. Huertas
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 2, pp 164-168, 2015
IEEE    DOI: 10.1109/TCSII.2014.2386233    ISSN: 1549-7747    » doi
[abstract]
A system for cell-culture real-time monitoring using an oscillation-based approach is proposed. The system transforms a cell culture under test into a suitable 'biological' oscillator, without needing complex circuitry for excitation and measurement. The obtained oscillation parameters are directly related to biological test, owed to an empirically extracted cell-electrode electrical model. A discrete prototype is proposed and experimental results with living cell culture are presented, achieving the expected performances.

Electrical Cell-substrate Impedance Spectroscopy (ECIS) Measurements based on Oscillation-Based Test Techniques
G. Huertas, A. Maldonado, A. Yufera, A. Rueda and J.L. Huertas
Conference - International Workshop on Impedance Spectroscopy IWIS 2013
[abstract]
A system for cell-culture real-time monitoring based on ECIS techniques, using the Oscillation-Based Test (OBT) meethodology is proposed. The system transforms a Cell-Culture under Test (CCUT) ¡nto a suitable 'bioIogical' oscillator, using only a DC power supply. Thanks to cell-electrode electrical models employed, the oscillation parameters obtained can be directly related with biological test. The system simulations solve with a 0.16 Hz/μm2 resolution on cell area detection for a proposed 50 x 50 μm2 microelectrode area.

Cell-culture Real-Time Monitoring: an Oscillation-based Approach
G. Huertas, A. Maldonado, J. Normando Olmo, A. Yúfera, A. Rueda and J.L. Huertas
Conference - Conference on the Design of Circuits and Integrated Systems DCIS 2013
[abstract]
In this paper, a way to cell-culture real-time monitoring by means of Oscillation-Based Test (OBT) methodology is proposed. The proposed idea is inspired in previous works from the authors in the area of testing analogue integrated circuits and deals with solving some critical points of biological measurements. A simple topology based on a non-linear element in a feedback loop is employed for converting the Cell-Culture Under Test (CCUT) into a suitable 'biological' oscillator. Then, the oscillator parameters (frequency, amplitude, phase, etc...) are used as empirical markers to carry out an appropriate interpretation in terms of cell size identification, cell counting, cell growth, etc. The precise values of oscillation parameters are closely related to the cell-electrode area overlap in the cellculture. To establish the accuracy of these predictions, the oscillators have been implemented and validated in Simulink.

Multi-condition alternate test of analog, mixed-signal, and RF systems
M.J. Barragán-Asián, G. Léger and J.L. Huertas-Díaz
Conference - IEEE Latin American Test Workshop LATW 2012
[abstract]
This work proposes a generic path to improve Alternate Test strategies. It demonstrates that multi-condition test increases the amount of information present in the test data and consequently decreases the prediction error of the trained models. The ambition of this paper is to be a methodological contribution to the field of AMS-RF test, and formal guidelines are provided that justify the interest of the approach. For the sake of validation, the proposed methodology has been applied to several alternate test strategies for analog, mixed signal, and RF circuits. Promising results are found for the following case studies: an analog filter, a ΣΔ A/D converter, and an RF LNA.

OBT for settling error test of sampled-data systems using signal-dependent clocking
M.J. Barragán-Asián, G. Léger and J.L. Huertas-Díaz
Conference - IEEE European Test Symposium ETS 2012
[abstract]
This work presents a modification of traditional Oscillation-Based Test schemes for sampled-data systems. This new test scheme is based on doubling the sampling frequency when the oscillation changes its sign. This way, the DC level of the output oscillation signal becomes a simple signature sensitive to the settling errors in the device under test and to its oscillation features. The proposed technique is illustrated on a switched-capacitor second-order lowpass filter. This case study is used to show the sensitivity of the proposed signature to the linearity of the DUT. Electrical simulation results are provided to validate the proposal. © 2012 IEEE.

Characterization and Modelling of Circular Piezoelectric Micro Speakers for Audio Acoustic Actuation
J. Mendoza-López, S. Sánchez-Solano and J.L. Huertas-Díaz
Journal Paper - ISRN Mechanical Engineering, vol. 2012, article ID 635268, 2011
INTERNATIONAL SCHOLARLY RESEARCH NETWORK    DOI: 10.5402/2012/635268    ISSN: 2090-5122    » doi
[abstract]
A study of circular piezoelectric micro speakers is presented for applications in the audio frequency range, including values for impedance, admittance, noise figures, transducer gain and acoustic frequency responses. The micro speakers were modelled based on piezoelectric micro ultrasonic transducer (pMUT) design techniques and principles. In order to reach the audio frequency range, transducer radii were increased to the order of one centimetre whilst piezoelectric layer thicknesses ranged the order of several .m. The micro actuators presented might be used for a variety of electroacoustic applications including noise control, hearing aids, earphones, sonar and medical diagnostic ultrasound. This work main contribution is the characterization of the design space and transducer performance as a function of transducer radius, piezoelectric layer thickness and frequency range, with views towards an optimized fabrication process.

Characterization and Modeling of Piezoelectric Integrated Micro Speakers for Audio Acoustic Actuation
J. Mendoza-López, S. Sánchez-Solano and J.L. Huertas-Díaz
Conference - IEEE International Conference on Electronics, Circuits, and Systems ICECS 2011
[abstract]
An array of piezoelectric micro actuators can be used for radiation of an ultrasonic carrier signal modulated in amplitude with an acoustic signal, which yields audio frequency applications as the air acts as a self-demodulating medium. This application is known as the parametric array. We propose a parametric array with array elements based on existing piezoelectric micro ultrasonic transducer (pMUT) design techniques. In order to reach enough acoustic output power at a desired operating frequency, a proper ratio between number of array elements and array size needs to be used, with an array total area of the order of one cm square. The transducers presented are characterized via impedance, admittance, noise figure, transducer gain and frequency responses.

Improving the accuracy of RF alternate test using multi-VDD conditions: Application to envelope-based test of LNAs
M.J. Barragán-Asián, R. Fiorelli-Martegani, G. Leger, A. Rueda and J.L. Huertas-Díaz
Conference - Asian Test Symposium ATS 2011
[abstract]
This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.

Alternate test of LNAs through ensemble learning of on-chip digital envelope signatures
M.J. Barragán, R. Fiorelli, G. Léger, A. Rueda and J.L. Huertas
Journal Paper - Journal of Electronic Testing-Theory and Applications, vol. 27, no. 3. pp 277-288, 2011
SPRINGER    DOI: 10.1007/s10836-010-5193-4    ISSN: 0923-8174    » doi
[abstract]
This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. A new Figure of Merit (FOM) is proposed to evaluate the prediction accuracy of the statistical model, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445 GHz low-power LNA and a simple envelope detector, and has been developed in a 90 nm CMOS technology. Post-layout simulations are provided to verify the functionality of the proposed test technique.

Low-cost signature test of RF blocks based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Conference - IEEE European Test Symposium ETS 2010
[abstract]
This paper presents a novel and low-cost methodology that can be used for testing RP blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach. © 2010 IEEE.

Guidelines for the efficient design of sinewave generators for analog/mixed-signal BIST
M.J. Barragán, D. Vázquez, A. Rueda and J.L. Huertas
Conference - IEEE International Mixed-Signals, Sensors and Systems Test Workshop IMS3TW 2010
[abstract]
This paper presents a design methodology for the implementation of efficient and accurate sinewave generators suitable for analog and mixed-signal BIST applications. The design guidelines are based on an analytical discussion that contemplates the main non-idealities of the generator. A full design example is presented to illustrate the proposed methodology. ©2010 IEEE.

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems
M.J. Barragán, G. Huertas, A. Rueda and J.L. Huertas
Conference - IEEE International Symposium on Electronic Design, Test and Applications DELTA 2010
[abstract]
This paper presents an overview of test techniques that offer promising features when Built-In-Self-Test (BIST) must be applied to complex intgrated systems including analog, mixed-signal and RF parts. Emphasis is on techniques exhibiting a good trade-off between test requirements (basically in terms of signal accuracy and frequency) and test quality. © 2010 IEEE.

On-chip characterization of RF systems based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Journal Paper - Electronics Letters, vol. 46, no. 1, pp 36-37, 2010
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2010.2644    ISSN: 0013-5194    » doi
[abstract]
A simple on-chip procedure for testing embedded RF blocks is presented. It is based on the detection and spectral analysis of the two-tone response envelope of the device under test (DUT). A main difference with similar methods is its inherent simplicity, avoiding a preprocessing stage and resorting to simpler circuitry to process the envelope. As a consequence, the main nonlinearity specifications of the DUT can be easily estimated from the envelope signal without the need of expensive RF test equipment.

Efficient functional built-In test for RF systems using two-tone response envelope analysis
M.J. Barragán, D. Vázquez, A. Rueda and J.L. Huertas
Conference - IEEE AFRICON 2009
[abstract]
This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

A BIST solution for the functional characterization of RF systems based on envelope response analysis
M.J. Barragán, R. Fiorelli, D. Vázquez, A. Rueda and J.L. Huertas
Conference - IEEE Asian Test Symposium ATS 2009
[abstract]
This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally practical simulation examples show the feasibility of the approach.

A 2.4 GHz LNA in a 90-nm CMOS technology designed with ACM model
R. Fiorelli, F. Silveira, E. Peralías, D. Vazquez, A. Rueda and J.L Huertas
Conference - Symposium on Integrated Circuits and Systems Design SBCCI 2008
[abstract]
As part of a Low-IF ZigBee receiver, a 2.4GHz differential common source low noise amplifier, implemented in a 90nm mixed/RF 7M CMOS process and designed in moderate inversion, is presented in this work. Design methodology and simulation results from Spectre-RF simulator are presented. With 2.5V supply voltage, the LNA achieves a noise figure of 2.5dB, an IIP3 of 1dB and gain higher than 10dB, with a current consumption of 12mA. The LNA area without pads is 720m x 710m. Copyright 2008 ACM.

Oscillation-based test in data converters: On-line monitoring
G. Huertas and J.L. Huertas
Conference - IEEE International Symposium on Electronic Design, Test and Applications DELTA 2008
[abstract]
This paper discusses the test of data converters using the so-called Oscillation Based Test (OBT) approach [1]. Extension of the concept as applied to filters and sigma-delta converters are considered, paying attention to those applications where monitoring along the circuit lifetime can be worthwhile, as is the case for hostile environments. In this case, detection of threshold voltage shifting produced by Total Ionizing Dose (TID) is an example of what can be done by resorting to OBT.

Measuring SET effects in a CMOS operational amplifier using a built-in detector
J.M. Espinosa-Duran, J. Velasco-Medina, G. Huertas, R. Velasco and J.L. Huertas
Conference - IEEE AFRICON 2007
[abstract]
This paper studies the effects produced by radiation Single Event Transient (SET) injected in the transistors of a custom operational amplifier, in order to evaluate their sensitivity to the radiation transient faults. A BID (Built-In Detector), was included in the circuit in order to amplify and detect the SETs effect. The circuit was designed using a non-rad-hard AMS-CMOS 0.8um process. In this case, simulation results allow the identification of the operational amplifier most sensitive transistors and the operating conditions during which the worst effects in the operational amplifier response were produced. ©2007 IEEE.

Total ionizing dose effects in switched-capacitor filters using oscillation-based test
J.M. Espinosa-Duran, J. Velasco-Medina, G. Huertas and J.L. Huertas
Conference - Symposium on Integrated Circuits and System Design SBCCI 2007
[abstract]
This paper studies long-term effects produced by ionizing radiation in a switched-capacitor filter, using the Oscillation Based Test (OBT) approach [1]. In this case, threshold voltage shifting is considered as one of the major concerning effects produced by Total Ionizing Dose (TID). Simulation results show that the OBT approach is very well suited for detection of faulty filters. Copyright 2007 ACM.

Oscillation-Based-Test in Mixed-Signal Circuits
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Book - FRET, vol. 36, 452 p, 2006
SPRINGER    ISBN: 978-1-4020-5314-6    » link
[abstract]
Oscillation-Based Test in Mixed-Signal Circuits presents the development and experimental validation of the structural test strategy called Oscillation-Based Test - OBT in short. The results here presented allow to assert, not only from a theoretical point of view, but also based on a wide experimental support, that OBT is an efficient defect-oriented test solution, complementing the existing functional test techniques for mixed-signal circuits.

On-chip analog sinewave generator with reduced circuitry resources
M.J. Barragán, D. Vázquez, A. Rueda and J.L. Huertas
Conference - IEEE Midwest Symposium on Circuits and Systems MWSCAS 2006
[abstract]
This paper proposes an analog sinewave signal generator with minimal circuitry resources. It is based on a linear time variant filter that gives a high quality sine signal in response to a DC input. The proposed architecture has the attributes of digital programming and control capability, robustness and reduced area overhead, what make it suitable for BIST applications. Experimental results from a practical design demonstrate the feasibility of the approach.

Synthesis and design of nonlinear circuits
A. Rodríguez-Vázquez, M. Delgado-Restituto, J.L. Huertas-Díaz and F. Vidal-Verdú
Book Chapter - Nonlinear and Distributed Circuits, pp 2-1, 2-36, 2005
CRC PRESS    DOI: 10.1201/9781420037081.ch2    ISBN: 978-0-8493-7276-6    » doi
[abstract]
Abstract not available

Robust frequency divider based on resonant tunneling devices
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2005
[abstract]
The behaviour of a novel and extremely compact resonant tunnelling diode (RTD)-based circuit able to implement a frequency divider is studied. It exhibits very high operating frequency and low power consumption. Compared to a previous similar reported circuit, it has wider operation windows, narrower quasi-peRíodicity regions and an higher division factor for the driver frequency, while maintaining the extremely high operating frequency, simplicity, and division factor tunability by selection of circuit parameters.

Low-voltage CMOS subthreshold log-domain filtering
F. Serra-Graells and J.L. Huertas
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 10, pp 2090-2100, 2005
IEEE    DOI: 10.1109/TCSI.2005.853256    ISSN: 1057-7122    » doi
[abstract]
This paper presents both a complete set of very low-voltage basic building blocks and a compact design methodology for log filtering in standard or even digital CMOS technologies. The new proposals are based on an alternative translinear loop principle for the MOSFET operating in its subthreshold region. Three different sets of complete basic building blocks are proposed along with all required auxiliary circuitry and a specific matrix design procedure to obtain stable and compact filter implementations. Also, all-MOS filter implementations following these circuit techniques are studied. Simulated and experimental examples are given at IN supply voltage for 1.2- and 0.35-mu m CMOS technologies. The resulting circuit techniques are suitable to integrate very low-voltage low-power system-on-a-chip audio applications, such as hearing aids, in standard CMOS technologies.

Low-voltage CMOS subthreshold log amplification and AGC
F. Serra-Graells and J.L. Huertas
Journal Paper - IEEE Proceedings-Circuits Devices and Systems, vol. 152, no. 1, pp 61-70, 2005
IEEE    DOI: 10.1049/ip-cds:20041003    ISSN: 1350-2409    » doi
[abstract]
A new very-low-voltage CMOS circuit strategy is presented for amplifying and AGC stages. Voltage supply scaling is optimised through the combination of log companding and the MOSFET operating in subthreshold. Based on this idea, a complete set of CMOS basic building blocks is proposed for programmable amplifiers and AGC circuits. Simulated and experimental results are reported at 1V supply to demonstrate the validity of the proposed techniques for the design of low-voltage audio systems-on-chip, such as hearing aids.

Sine-wave signal characterization using square-wave and Sigma Delta-modulation: Application to mixed-signal BIST
D. Vázquez, G. Huertas, A. Luque, M.J. Barragán, G. Léger, A. Rueda and J.L. Huertas
Journal Paper - Journal of Electronic Testing-Theory and Applications, vol. 21, no. 3, pp 221-232, 2005
SPRINGER    DOI: 10.1007/s10836-005-6352-x    ISSN: 0923-8174    » doi
[abstract]
This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. It is based on a double-modulation, square-wave and sigma-delta, together with a simple Digital Processing Algorithm. It leads to an efficient and robust approach very suitable for BIST applications. In this line, some considerations for on-chip implementation are addressed together with simulation results that validate the feasibility of the proposed approach.

Test and Design-for-Testability in Mixed-Signal Integrated Circuits
J.L. Huertas (Ed.)
Book - 298 p, 2004
SPRINGER    ISBN: 978-1-4419-5422-0    » link
[abstract]
The integration level of systems is continuously increasing. In many application contexts the target is to reduce the system just to one chip -a socalled System-on-Chip (SoC)-, where different technologies are mixed up (analog, digital, sensors, RF ... ). Designing such systems is undoubtedly a major problem in today microelectronics, because of the inherent complexity of dealing with so heterogeneous technologies. However, another task becoming the real bottleneck of present and future IC projects is how to test those complex and heterogeneous systems in an efficient manner, in terms of test time, cost and proficiency.

Oscillation-based test strategies
G. Huertas-Sánchez, G. Leger, D. Vázquez, A. Rueda and J.L. Huertas
Book Chapter - Test and Design-For-Testability in Mixed-Signal Integrated Circuits, pp 259-298, 2004
SPRINGER    DOI: 10.1007/978-0-387-23521-9_9    ISBN: 978-1-4419-5422-0    » doi
[abstract]
This chapter aims to present a structural test methodology using the so-called OBT technique. The conceptual bases of the OBT approach are presented as well as many practical details on its application to practical integrated circuits.

Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs
G. Léger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper - IEEE Transactions on Circuits and Systems I, vol. 51, no. 1, pp 140-150, 2004
IEEE    DOI: 10.1109/TCSI.2003.821301    ISSN: 1057-7122    » doi
[abstract]
Using several analog-to-digital converters (ADCs) in parallel with convenient time offsets is considered an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this time-interleaving technique is that any mismatch between the channels will damage the precision. This paper gives a probabilistic description of the problem, studying the impact of time skews, gain, and offset mismatches. The probability density function of both signal-to-noise ratio (SNR) and spurious-free-dynamic range (SFDR) are explicitly calculated, giving access to important statistical parameters. It is shown that the SNR and SFDR dispersion should not be neglected in making practical considerations for design decisions. © 2004 IEEE.

Method for parameter extraction of analog sine-wave signals for mixed-signal built-in-self-test applications
D. Vázquez, G. Léger, G. Huertas, A. Rueda and J.L. Huertas
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2004
[abstract]
This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. The required circuitry for on-chip implementation is very simple and robust, which makes the present approach very suitable for BIST applications. Solutions in this sense are addressed together with simulation results that validate the feasibility of the proposed approach.

A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip
F. Serra-Graells, L. Gómez and J.L. Huertas
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp 1271-1281, 2004
IEEE    DOI: 10.1109/JSSC.2004.831469    ISSN: 0018-9200    » doi
[abstract]
This paper presents a true very low-voltage low-power complete analog hearing-aid. system-on-chip as a demonstrator of novel analog CMOS circuit, techniques based on log companding processing and using MOS transistors operating in subthreshold. Low-voltage circuit implementations are given for all of the required functions including amplification and automatic gain control filtering, generation, and pulse-duration modulation. Based on these blocks, a single 1-V 300-muA application specific integrated circuit integrating a complete hearing aid in a standard 1.2-mum CMOS technology is presented along with exhaustive experimental data. To the authors knowledge, the presented system is the only CMOS hearing aid with true internal operation at, the battery supply voltage and with one of the lowest current consumptions reported in literature. The resulting low-voltage CMOS circuit techniques may also be applied to the design of A/D converters for digital hearing aids.

Simplified Reed-Muller expressions for residue threshold functions
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Journal Paper - Circuits Systems and Signal Processing, vol. 23, no.1, pp 45-56, 2004
BIRKHAUSER BOSTON INC    DOI: 10.1007/s00034-004-7003-7    ISSN: 0278-081X    » doi
[abstract]
Residue threshold functions are a broad class of symmetric functions that include all the unit-weighted threshold functions. In this paper, we investigate the complexity of the Reed-Muller (RM) expressions for these functions. We prove that an important subclass of the functions has very simple RM expansions and determine the conditions that define such a subclass. Additionally, we show that such an expansion is also the optimal one concerning its polarity. As an interesting practical application, an analysis of the RM expansion of the output functions for parallel counters is performed.

Analysis of error mechanisms in switched-current sigma-delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 38, no. 2-3, pp 175-201, 2004
KLUWER ACADEMIC    DOI: 10.1023/B:ALOG.0000011167.24521.82    ISSN: 0925-1030    » doi
[abstract]
This paper presents a systematic analysis of the major switched-current ( SI) errors and their influence on the performance degradation of SigmaDelta Modulators (SigmaDeltaMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass SigmaDeltaM (2nd-LPSigmaDeltaM) and a 4th-order BandPass SigmaDeltaM (4th-BPSigmaDeltaM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in the case of 4th-BPSigmaDeltaMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI SigmaDeltaMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 mum CMOS SI 4th-BPSigmaDeltaM silicon prototype validate our approach.

Low-Voltage CMOS Log Companding Analog Design
F. Serra-Graells, A. Rueda and J.L. Huertas
Book - SECS, vol. 733, 192 p, 2003
SPRINGER    ISBN: 1-4020-7445-X    » link
[abstract]
Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.

A LP-LV high performance monolitic DTMF receiver with on-chip test facilities
D. Vázquez, G. Huertas, M.J. Avedillo, J.M. Quintana, A. Rueda and J.L. Huertas
Conference - Conference on VLSI Circuits and Systems 2003
[abstract]
This paper presents a mixed-signal DTMF receiver implemented in a double-poly double-metal 0.6um technology able to operate in the range of 2.7V-5V of voltage supply with a low current consumption (<1mA). An smart digital detector and decoder algorithm provides a very good speech immunity. On-chip test facilities for the analog part have.. been incorporated into the chip. A modified opamp (called sw-opamp) has been used to provide external accessing to inputs and outputs of the main analog blocks for off-line testing purposes. The so-called Oscillation-Based-Test (OBT) has also been integrated to perform a structural testing of the analog part. The additional cost of such on-chip test facilities is very small: just one extra pin and an area overhead of around 7%. Experimental results demonstrate the good performance of the design and the feasibility of the testing approaches.

Oscillation-based test in bandpass oversampled A/D converters
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Conference - IEEE International Mixed-Signal Testing Workshop IMSTW 2003
[abstract]
This paper extends a study performed by the authors in Previous papers dealing with the OBT approach applied to low-pass modulators 'Microelectron. J. 33/10 (2002) 799', showing herein the specific features associated to the bandpass case. A practical feedback strategy will be proposed in order to built an effective oscillator, which can be valuable for testing purposes. Critical points of the proposed OBT solution will be considered in order to establish useful guidelines to apply this test approach to generic bandpass SigmaDelta modulators. (C) 2003 Elsevier Ltd. All rights reserved.

1 V CMOS subthreshold log domain PDM
F. Serra-Graells, J.L. Huertas
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 34, no. 3, pp 183-187, 2003
KLUWER ACADEMIC    DOI: 10.1023/A:1022545414777    ISSN: 0925-1030    » doi
[abstract]
A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.

Sub-1-V CMOS proportional-to-absolute temperature references.
F. Serra-Graells and J.L. Huertas
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp 84-88, 2003
IEEE    DOI: 10.1109/JSSC.2002.806258    ISSN: 0018-9200    » doi
[abstract]
This paper presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (muA) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-muW integrated PTAT references are. presented and exhaustively tested for 1.2- and 0.35-mum very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+ > 60 dB. Hence, the resulting PTAT circuits are suitable for very-low-voltage system-on-a-chip applications in digital CMOS technologies.

On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits
D. Vázquez, G. Huertas, G. Leger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 201-211, 2002
SPRINGER    DOI: 10.1023/A:1021276218012    ISSN: 0925-1030    » doi
[abstract]
This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.

Practical solutions for the application of the oscillation-based-test in analog integrated circuits
D. Vázquez, G. Huertas, G. Léger, A. Rueda and J.L. Huertas
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
This paper presents practical solutions for solving the problems arising when applying Oscillation-Based-Test. It is devoted to discuss a practical on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.

Simplified Reed-Muller expressions for residue threshold functions
J.M. Quintana, M.J. Avedillo and J.L. Huertas
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
Residue threshold functions are a broad class of boolean functions which includes all the unit-weighted threshold functions. In this Paper we investigate the complexity of the Reed-Muller (RM) expressions for these functions. We prove that an important subclass of them have very simple RM expansions and determine the conditions that define it. As an interesting practical application, we show that the output functions of parallel counters belong to this subclass.

Practical oscillation-based test in analog integrated filters: Experimental results
G. Huertas, D. Vázquez, A. Rueda and J.L. Huertas
Conference - IEEE International Workshop on Electronic Design, Test and Applications DELTA 2002
[abstract]
This paper presents experimental results corresponding to the use of Oscillation-based Test (OBT) when applied to a switched-capacitor integrated filter. A universal biquad is used as an example to demonstrate the feasibility of the OBT technique.

Practical solutions for the application of the oscillation-based-test: Start-up and on-chip evaluation
D. Vázquez, G. Huertas, G. Léger, A. Rueda and J.L. Huertas
Conference - IEEE VLSI Test Symposium VTS 2002
[abstract]
This paper presents practical solutions for two of the main topics arising when applying Oscillation-Based-Test: the start-up of the configured oscillator and the on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.

Practical oscillation-based test of integrated filters
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper - IEEE Design & Test of Computers, vol. 19, no. 6, pp 64-72, 2002
IEEE COMPUTER SOCIETY PRESS    DOI: 10.1109/MDT.2002.1047745    ISSN: 0740-7475    » doi
[abstract]
Oscillation-based test techniques show promise in detecting faults in mixed-signal circuits and require little modification to the circuit under test. Comparing both the oscillation's amplitude and frequency yields acceptable test quality.

Testing mixed-signal cores: A practical oscillation-based test in an analog macrocell
G. Huertas, D. Vázquez, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper - IEEE Design & Test of Computers, vol. 19, no. 6, pp 73-82, 2002
IEEE COMPUTER SOCIETY PRESS    DOI: 10.1109/MDT.2002.1047746    ISSN: 0740-7475    » doi
[abstract]
A formal set of design decisions can aid in using oscillation-based test for analog subsystems in SoCs. The goal is to offer designers testing options that don't have significant area overhead, performance degradation, or test time.

COPAS: A new algorithm for the partial input encoding problem
M. Martinez, M.J. Avedillo, J.M. Quintana and J.L. Huertas
Journal Paper - VLSI Design, vol. 14, no. 2, pp 171-181, 2002
TAYLOR & FRANCIS    DOI: 10.1080/10655140290010088    ISSN: 1065-514X    » doi
[abstract]
Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols should be chosen to optimize the final implementation. Conventionally, this input encoding (IE) problem has been solved in a two-step process. First step generates constraints on the relationship between codes for different symbols, called group constraints. In a following step, symbols are encoded such that constraints are satisfied. This paper addresses the partial input encoding problem (PIE), a variation of the IE problem which generates codes of minimum length. The role of group constraints within the framework of the PIE problem has been questioned. This paper describes an algorithm that unlike conventional approaches, which try to maximize the number of satisfied constraints, targets the economical implementation of each input constraint. The proposed approach is based on a powerful heuristic that produces high quality results in shorter time compared to previous algorithm.

A simple and secure start-up circuitry for oscillation-based-test application
D. Vázquez, G. Huertas, A. Rueda and J.L. Huertas
Journal Paper - Analog Integrated Circuits and Signal Processing, vol 32, no. 2, pp 187-190, 2002
SPRINGER    DOI: 10.1023/A:1019538429162    ISSN: 0925-1030    » doi
[abstract]
A simple start-up strategy specially suitable for the oscillation-based-test application of opamp-based circuits is presented. The proposed approach not only ensures that the oscillator will start to run (safe start-up) but also the steady-state (SS) can be reached very fast (short transient-time).

VHDL behavioural modelling of pipeline analog to digital converters
A.J. Acosta, E. Peralias, A. Rueda and J.L. Huertas
Journal Paper - Measurement, vol. 31, no. 1, pp 47-60, 2002
ELSEVIER    DOI: 10.1016/S0263-2241(01)00014-8    » doi
[abstract]
This paper describes a VHDL implementation of a behavioural model for pipeline analog to digital converters (ADCs). The goal is using this VHDL description to facilitate the synthesis of the digital part, which in our example includes digital correction, digital calibration, and control of the ADC testing modes. Among other aspects of general interest, we will show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. As an application example, an ADC of 10-bits and 10 MSamples/s has been modelled and simulated. Results front these high level simulations carried out using QuickHDL in Mentor Graphics are compared with those obtained experimentally from a silicon prototype, validating the suitability of the model. (C) 2002 Elsevier Science Ltd. All rights reserved.

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