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Author: Guerra Vinuesa , Óscar
Year: Since 2002
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Effects of capacitors non-idealities in un-even split-capacitor array SAR ADCs
R. Fiorelli, O. Guerra, R. del Rio and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
This paper studies the effects of capacitors non-idealities in the performance of un-even split-capacitor SAR ADCs. Also, election of the m and l bits of MSB and LSB capacitors banks, respectively, is studied to reduce SAR errors. To exemplify and quantify the non-idealities, MOM capacitors are used. In particular, MOM layout parasitics and effective capacitors' value is obtained with an electrical extraction tool using a flattened view of the MOM. Effects of capacitors layout placement in the SAR and their surroundings in the effective capacitance value are quantified. A quantitative study of a 10-bit un-even split-capacitor SAR is done for different combinations of m and l bits. Finally, a qualitative set of guidelines to choose the distribution of these bits is listed.

5x5 SPAD Matrices for the Study of the Trade-offs between Fill Factor, Dark Count Rate and Crosstalk in the Design of CMOS Image Sensors
M. Moreno-García, R. del Río, Ó. Guerra, and Á. Rodríguez-Vázquez
Conference - Conference on Ph.D. Research in Microelectronics and Electronics PRIME 2014
[abstract]
CMOS Single Photon Avalanche Diodes (SPADs) are a dedicated type of photodetectors that are attracting increasing interest. Crosstalk and fill factor are magnitudes that become important when dealing with arrays of SPADs. There are tradeoffs that involve these two magnitudes and dark count rate (DCR) which are of great interest for the implementation of image sensors. A set of 5x5 matrices of SPADs with different sizes and shapes is designed to study the relationships between FF, crosstalk and DCR, and conceive an accurate behavioural model of SPAD arrays. The testchip is fully operative and preliminary experimental results are presented.

CMOS SPADs Selection, Modeling and Characterization Towards Image Sensors Implementation
M. Moreno-García, O. Guerra, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - International Conference on Electronics, Circuits, and Systems ICECS 2012
[abstract]
The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance.

A reconfigurable neural spike recording channel with feature extraction capabilities
A. Rodríguez-Pérez, J. Ruiz-Amaya, O. Guerra and M. Delgado-Restituto
Conference - IEEE Biomedical Circuits and Systems Conference BioCAS 2010
[abstract]
This paper describes the architecture of a neural spike recording channel with feature extraction capabilities and presents the design of one of its key elements, a reconfigurable 8-bit ADC. The ADC can be programmed for different conversion rates and embeds a 0-18dB programmable gain amplifier with discrete gain steps of 3dB. Simulation results from extracted layout of the ADC, designed in a 130nm CMOS technology, obtain almost 8-bit ENOB at 22.2kS/s and 90kS/s, with a power consumption of 500nW and 1.8uW, respectively. ©2010 IEEE.

Systematic top-down design of reconfigurable ΣΔ modulators for multi-standard transceivers
R. Castro-López, A. Morgado, O. Guerra, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and F. Fernández
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 58, no. 3, pp 227-241, 2009
SPRINGER    DOI: 10.1007/s10470-007-9122-0    ISSN: 0925-1030    » doi
[abstract]
This paper addresses the design techniques of reconfigurable analog-to-digital converters for multi-standard wireless communication terminals. While most multi-standard converters reported so far follow an ad hoc design approach, which do not guarantee either efficient silicon area occupation or power efficiency in the different operation modes, the methodology presented here formulates a systematic design flow that ensures that both factors are considered at all hierarchical levels. Expandible cascade modulators are considered as the starting point to further reconfigurability at the architectural level. From here on, and using a combination of accurate behavioral modeling, statistical optimization techniques, and device-level simulation, the proposed methodology handles the design complexity of a reconfigurable converter while ensuring adaptive power consumption and boosting hardware sharing. A case study is presented where a reconfigurable modulator is designed to operate under three communication standards, GSM, Bluetooth, and UMTS, in a 130 nm-CMOS technology.

An integrated layout-synthesis approach for analog ICs
R. Castro-López, O. Guerra, E. Roca and F.V. Fernández
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 7, pp 1179-1189, 2008
IEEE    DOI: 10.1109/TCAD.2008.923417    ISSN: 0278-0070    » doi
[abstract]
In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided.

Towards systematic design of multi-standard converters
V.J. Rivas, R. Castro-López, A. Morgado, O. Guerra, E. Roca, R. del Río, J.M. de la Rosa and F.V. Fernández
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
In the last few years, we are witnessing the convergence of more and more communication capabilities into a single terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements: (1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels, with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design information. The systematic design methodology is illustrated via the design of a multi-standard YEA modulator meeting the specifications of three wireless communication standards.

Reuse-Based Methodologies And Tools in the Design of Analog and Mixed-Signal Integrated Circuits
R. Castro-López, F.V. Fernández-Fernández, O. Guerra-Vinuesa and A. Rodríguez-Vázquez
Book - 393 p, 2006
SPRINGER    ISBN: 978-1-4020-5126-5    » link
[abstract]
Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits under stringent time-to-market requirements is lagging behind integration capacity, so far keeping pace with still valid Moore Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools, design methodologies and even a design paradigm shift, that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design -more subtle, hierarchically loose, and handicraft-demanding- has hindered a similar level of consensus and development. Aiming at the core of the problem, Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the first two for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits features a very detailed, tutorial, and in-depth coverage of all issues and must-have properties of reusable AMS blocks, as well as a thorough description of the methods and tools necessary to implement them. For the first time, this has been done hierarchically, covering one by one the different stages of the design flow, allowing us to examine how the reusable block yields its benefits, both in design time and correct performance.

A CMOS High-Resolution Automotive Sensor A/D Interface Based on a 110-dB @ 40kS/s Programmable-Gain Cascade 2-1 Sigma-Delta Modulator with Embedded Design-for-Testability Strategies
J.M. de la Rosa, S. Escalera, O. Guerra, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference - Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
[abstract]
Abstract not available

A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 sigma delta modulator with programmable gain and programmable chopper stabilization
O. Guerra, S. Escalera, J.M. de la Rosa, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
This paper describes a 0.35 μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/ 2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40 degrees C, 175 degrees C). The modulator architecture has been selected after an exhaustive comparison among multiple Sigma Delta M topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.

Embedded desing-for-testability strategies to test high-resolution SD modulators
S. Escalera, A. Espin, O. Guerra, J.M. de la Rosa, F. Medeiro and B. Pérez-Verdú
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
This paper describes the design-for-testability strategies integrated in a 0.35 mu m CMOS 17-bit@40-kS/s chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. After a brief review on the most important effects degrading the circuit performance, a test technique, based on the division of the circuit into several blocks that are tested separately, is presented. Experimental results shows the utility of the implemented test technique to detect errors in the circuit and to characterize the most important blocks with a minimum increase of extra area for the additional test circuitry.

A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs
J.M. de la Rosa, S. Escalera, B. Pérez-Verdú, F. Medeiro, O. Guerra, R. del Río and A. Rodríguez-Vázquez
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp 2246-2264, 2005
IEEE    DOI: 10.1109/JSSC.2005.857356    ISSN: 0018-9200    » doi
[abstract]
This paper describes a 0.35-mu m CMOS chopper-stabilized switched-capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values ( 0.5, x 1, x 2, and x 4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40 degrees C to 175 degrees C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm(2) silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution Sigma Delta modulators.

A 0.35 μm CMOS 17-bit@40 kS/s sensor A/D interface based on a programmable-gain cascade 2-1 sigma delta modulator
J.M. García-González, S. Escalera, J.M. de la Rosa, O. Guerra, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - International Symposium on Circuits and Systems ISCAS 2004
[abstract]
This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35mum standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) SigmaDelta modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage opamps, has a fixed gain of 10 and it is capable of handling signals with 20kHz-bandwidth and amplitudes ranging from muVs to hundreds of mVs with a signal-to-(noise+distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulation results show 17-bit@40kS/s for all cases of the modulator gain.

An alternative DFT methodology to test high-resolution sigma delta modulators
S. Escalera, J.M. García-González, O. Guerra, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2004
[abstract]
In this paper, a novel DfT methodology to test high-resolution SigmaDelta Modulators (SigmaDeltaM) is introduced. The aim of the proposal is to reduce the test time required by conventional methodologies without degrading the accuracy of the results. A detailed description of the additional circuitry needed to perform these tests is presented as well as some initial simulation results to show the utility of the approach.

Synthesis of a wireless communication analog back-end based on a mismatch-aware symbolic approach
R. Castro-López, O. Guerra, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 40, no. 3, pp 215-233, 2004
SPRINGER    DOI: 10.1023/B:ALOG.0000034825.47829.04    ISSN: 0925-1030    » doi
[abstract]
In this paper, a methodology to automate the synthesis of an industrial-purpose analog integrated circuit, namely the back-end of an I&Q transmit interface, is presented. A good matching between both I and Q channels is desirable to ensure the correct circuit functioning. The proposed methodology combines the use of symbolic expressions with numerical approaches. While the symbolic expressions allow a fast iterative evaluation of the circuit performance, the numerical capabilities ensure a rapid optimization of the results. Unlike other approaches, the methodology uses symbolic expressions explicitly considering device mismatch, which are evaluated performing a Monte-Carlo analysis. The expressions have been obtained using an error-control process guided by the mean and standard deviation values of the circuit performance characteristics. This provides two benefits. First, smaller expressions are obtained. Second, expression evaluation is faster: smaller number of operations - symbol products and term sums - are carried out since, at each Monte-Carlo run, only those symbols related to device mismatch are to be changed, while the rest remains constant. A comparison between the presented synthesis technique and other purely numerical and numerical/symbolic approaches is also given.

Design and Implementation of a 0.35μm CMOS Programmable-Gain 2-1 Cascade ΣΔ Modulator for Automotive Sensors
J.M. García-González, S. Escalera, J.M. de la Rosa, F. Medeiro, R. del Río, O. Guerra, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2003
[abstract]
Abstract not available

Design methodologies for sigma-delta converters
F.V. Fernández, R. del Río, R. Castro-López, F. Medeiro and B. Pérez-Verdú
Book Chapter - CMOS Telecom Data Converters, pp 523-559, 2003
SPRINGER    DOI: 10.1007/978-1-4757-3724-0_15    ISBN: 978-1-4419-5382-7    » doi
[abstract]
Oversampling converters have become very popular due to their ability to solve problems found in other architectures, like the need for high-accuracy analog antialiasing filtering and the large sensitivity to circuit imperfections and noisy environments.

A modem in CMOS technology for data communication on the low-voltage power line
O. Guerra, C.M. Domínguez-Matas, S. Escalera, J.M. García-González, G. Liñán, R. del Río, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper - Integration, the VLSI Journal, vol. 36, no. 4, pp 229-236, 2003
ELSEVIER    DOI: 10.1016/j.vlsi.2003.09.007    ISSN: 0167-9260    » doi
[abstract]
This paper presents a CMOS 0.8 mum mixed-signal half-duplex Modem ASIC for data transmission on the low-voltage power line. It includes all the analog circuitry needed for input interfacing and modulation/ demodulation (low-noise amplifier, PLL-based frequency synthesis, tunable filter banks, and decision circuitry), logic circuitry for control purposes, and an output amplifier used as front-end for an off-chip line driver. The chip demodulates signals down to 283muV(rms) (these are worst case values among 30 randomly-selected samples used as vehicles for detailed electrical characterization; most of the samples featured 200 muV(rms), sensitivity; bit error rate (BER) is below 0.5 x 10(-5)) at 10 kbps, and operates correctly in the whole industrial temperature range, from -45degreesC to 80degreesC, under 5% variations of the 5V supply voltage. This ASIC is now in commercial production. (C)2003 Published by Elsevier B.V.

On the development of a MODEM for data transmission and control of electrical household appliances using the low-voltage power-line.
S. Escalera, C.M. Domínguez-Matas, J.M. García-González, O. Guerra and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
This paper presents a CMOS 0,6mum, mixed-signal MODEM ASIC for data transmission on the low-voltage power line. The circuit includes all the analog circuitry needed for input interfacing and modulation/demodulation (PLL-based frequency synthesis, slave filter banks with PLL master VCO for tuning, decision circuitry, etc.) plus the logic circuitry needed for control purposes. The circuit operates correctly in the whole industrial temperature range, from -45 to 80degreesC, under 5% variations of the 3.3V supply voltage.

CMOS mixed-signal MODEM for data transmission and control of electrical household appliances using the low-voltage power-line
S. Escalera, C.M. Domínguez-Matas, J.M. García-González, O. Guerra and A. Rodríguez-Vázquez
Conference - Conference on VLSI Circuits and Systems 2003
[abstract]
This paper presents a CMOS 0.6mum mixed-signal MODEM ASIC for data transmission using the low-voltage power line. This circuit includes all the analog blocks needed for input interfacing and modulation/demodulation (PLL-based frequency synthesis, slave filter banks with PLL master VCO for tuning, and decision circuitry) plus the logic circuitry needed for control purposes. The circuit operates correctly within the industrial temperature range, from -45 to 80 degreesC, under 5% variations of the 3.3V supply voltage.

Técnicas avanzadas para el análisis simbólico aproximado de circuitos integrados analógicos
O. Guerra-Vinuesa
Thesis - Date of defense: 04/07/2002
UNIVERSIDAD DE SEVILLA, IMSE-CNM    
[abstract]
Esta Tesis introduce técnicas novedosas para permitir el análisis simbólico de circuitos analógicos. Se hace un análisis exhaustivo de las técnicas y herramientas desarrolladas anteriormente y, en base a las conclusiones de ahí obtenidas, se introducen nuevas metodologías que palian las anteriores limitaciones. En todos los casos, se muestran numerosas aplicaciones prácticas que permiten evaluar las capacidades de las técnicas desarrolladas. Este conjunto de nuevas metodologías (mecanismos de simplificación de expresiones simbólicas, análisis jerárquico, extracción simbólica de polos y ceros, etc.), se ha implementado en una herramienta de análisis simbólico, denominada SYMBA, con capacidad para analizar circuitos de gran tamaño.

A symbolic pole/zero extraction methodology based on analysis of circuit time-constants
O. Guerra, J.D. Rodríguez-García, F.V. Fernández and A. Rodríguez-Vázquez
Conference - International Workshop on Symbolic Methods and Applications to Circuit Design SMACD 2002
[abstract]
This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.

Approximate symbolic analysis of hierarchically decomposed analog circuits
O. Guerra, E. Roca, F.V. Fernandez and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 31, no. 2, pp 131-145, 2002
KLUWER ACADEMIC    DOI: 10.1023/A:1015094011107    ISSN: 0925-1030    » doi
[abstract]
This paper presents a methodology for the symbolic analysis of large analog integrated circuits using a hierarchical approach. The drawbacks of previous approaches are solved by the introduction of error-controlled approximation strategies. A proper modeling methodology through the different hierarchical levels allows to combine the optimum techniques for generation of the symbolic expressions and the most efficient numerical techniques for error control. These approximation strategies together with mechanisms for partitioning and union of blocks through the hierarchy yield optimum results in terms of speed, accuracy and complexity of the symbolic results.

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