Found results matching for:
Author: Antonio J. López Angulo
Year: Since 2002
Journal Papers
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Conferences
Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy
A. Lopez-Angulo, A. Gines and E. Peralias
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
abstract
This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can occur due to saturation of the redundancy intervals associated with implemented weights, eventually leading to a faulty behavior even with lower effective resolution than the case without calibration. To overcome this limitation, this work proposes a foreground technique which reuses the least-significant bit (LSB) capacitors in the array in a design with redundancy for offset compensation. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit SAR ADC case study with 3 redundant bits.
Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy
A. Lopez-Angulo, A. Gines and E. Peralias
Conference · IEEE International New Circuits and Systems Conference NEWCAS 2020
abstract
This work introduces a digital technique to measure and correct the mismatch between capacitors in SAR ADCs with split capacitor-based DAC (CDAC), including the bridge capacitor impairments. The method takes advantage of redundancy for calibration with negligible impact on the analog section. It reuses some of the capacitors in the array to also com-pensate the comparison offset, preventing redundancy interval saturation during the error measurement phase. The effec-tiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit split-CDAC SAR ADC case study.
Mismatch and Offset Calibration in Redundant SAR ADC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
abstract
This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can occur due to saturation of the redundancy intervals associated with implemented weights, eventually leading to a faulty behavior even with lower effective resolution than the case without calibration. To overcome this limitation, this work proposes a foreground technique which reuses the leastsignificant bit (LSB) capacitors in the array in a design with redundancy for offset compensation. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit SAR ADC case study with 3 redundant bits.
SAR ADCs with Redundant Split-capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2018
abstract
This paper analyzes the effect of redundancy in Successive Approximation Register (SAR) ADCs with splitcapacitor DAC (Split-CDAC). It also presents a general hardware-based model which provides closed-relationships, suitable for design, between the capacitor scale factors, the bridge capacitance and the practical implementation of the digital correction logic. In conventional binary Split-CDAC (without redundancy), the voltage at the floating nets in the array could exceed the ADC references, stressing the operation of switches. Using the proposed model, we will show that this effect also occurs in SAR ADCs with redundancy, but with some particularities depending on the selection of the weighting coefficients in the digital correction logic. We will demonstrate the excursion can be controlled, as in the binary case, with a simple DAC modification which includes an extra limiting capacitor.
Redundant SAR ADCs with Split-Capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2018
abstract
This paper presents an unified formulation for Successive Approximation Register (SAR) ADCs with splitcapacitor arrays providing explicit expressions, suitable for design, of the relationships between capacitors and the weighting coefficient in the digital correction logic. A closed-form estimation of the optimum limiting capacitor to control the voltage excursion in the floating node of the Least Significant Bit (LSB) array is, in the authors´ bibliography best knowledge, firstly derived in this work. The proposed hardware-based formulation has been verified by behavioral and electrical simulations.
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach
A. Gines, A. Lopez-Angulo, E. Peralias and A. Rueda
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract
This paper analyzes the state-of-the-art in Successive-Approximation-Register (SAR) ADCs with digital redundancy using a unified nomenclature and modeling. Redundancy provides tolerance intervals for dealing with comparison errors during the SAR search algorithm due to incomplete settling in the DAC. Employing redundancy improves conversion speed/power trade-off as well as relaxes switch sizes and comparator design. The proposed description presents a common theoretical and physical framework for analyzing existing (apparently different) techniques in the bibliography, independently of the practical realization (binary or arbitrary scaled capacitors with redundant bits) and switching schemes. Several examples are modeled and simulated using the proposed approach.
Unified Hardware-Based Description for SAR ADCs with Redundancy
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2017
abstract
This paper presents an analysis and review of digital redundancy techniques in Successive-Approximation-Register (SAR) ADCs for correction of comparator errors during the SAR search algorithm. The use of redundancy provides safety margin for dealing with incomplete settling in the DAC network, improving conversion speed and power, as well as relaxing switch sizes and comparator design. Techniques like binaryscaled, radix-based or arbitrary weighing capacitors with redundant bits are discussed using a unified nomenclature and modeling. The proposed unified description is closely related to the hardware realization eliminating the gap between theoretical and physical implementations, and allowing a clear identification of pros and cons of different approaches. For illustration purpose, several examples are modeled and simulated using the proposed description.
Books
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Book Chapters
Remote Sensing of Cell-Culture Assays
P. Pérez, A. Maldonado-Jacobi, A.J. López, C. Martínez, A. Olmo, G. Huertas and A. Yufera
Book Chapter · New Insights into Cell Culture Technology, pp 135-155, 2017
abstract
doi
This chapter describes a full system developed to perform the remote sensing of cell-culture experiments from any access point with internet connection. The proposed system allows the real-time monitoring of cell assays thanks to bioimpedance measurement circuits developed to count the number of cell present in a culture. Cell-culture characterization is performed through the measurement of the increasing bioimpedance parameter over time. The circuit implementation is based on the oscillation-based test (OBT) methodology. Bioimpedance of cell cultures is measured in terms of the oscillation parameters (frequency, amplitude, phase, etc.) and used as empirical markers to carry out an appropriate interpretation in terms of cell size identification, cell counting, cell growth, growth rhythm, etc. The device is capable of managing the whole sensing task and performs wireless communication through a Bluetooth module. Data are interpreted and displayed on a computer or a mobile phone through a web application. The system has its practical application in drug development processes, offering a label-free, high-throughput, and high-content screening method for cellular research, avoiding the classical end-point techniques and a significant workload and cost material reduction.
Other publications
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