IMSE Publications

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Author: Amirreza Yousefzadeh
Year: Since 2002

Journal Papers


Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity
A. Yousefzadeh, M.A. Khoei, S. Hoseini, P. Holanda, S. Leroux, O. Moreira, J. Tapson, B. Dhoedt, P. Simoens, T. Serrano-Gotarredona, B. Linares-Barranco
Journal Paper · IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 4, pp 668-678, 2019
abstract      doi      

Inference of Deep Neural Networks for stream signal (Video/Audio) processing in edge devices is still challenging. Unlike the most state of the art inference engines which are efficient for static signals, our brain is optimized for real-time dynamic signal processing. We believe one important feature of the brain (asynchronous state-full processing) is the key to its excellence in this domain. In this work, we show how asynchronous processing with state-full neurons allows exploitation of the existing sparsity in natural signals. This paper explains three different types of sparsity and proposes an inference algorithm which exploits all types of sparsities in the execution of already trained networks. Our experiments in three different applications (Handwritten digit recognition, Autonomous Steering and Hand-Gesture recognition) show that this model of inference reduces the number of required operations for sparse input data by a factor of one to two orders of magnitudes. Additionally, due to fully asynchronous processing this type of inference can be run on fully distributed and scalable neuromorphic hardware platforms.

On practical issues for stochastic STDP hardware with 1-bit synaptic weights
A. Yousefzadeh, E. Stromatias, M. Soto, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · Frontiers in Neuroscience, vol. 12, article 665, 2018
abstract      doi      pdf

In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware.

Active Perception with Dynamic Vision Sensors. Minimum Saccades with Optimum Recognition
A. Yousefzadeh, G. Orchard, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 12, no. 4, pp 927-939, 2018
abstract      doi      

Vision processing with dynamic vision sensors (DVSs) is becoming increasingly popular. This type of a bio-inspired vision sensor does not record static images. The DVS pixel activity relies on the changes in light intensity. In this paper, we introduce a platform for the object recognition with a DVS in which the sensor is installed on a moving pan-tilt unit in a closed loop with a recognition neural network. This neural network is trained to recognize objects observed by a DVS, while the pan-tilt unit is moved to emulate micro-saccades. We show that performing more saccades in different directions can result in having more information about the object, and therefore, more accurate object recognition is possible. However, in high-performance and low-latency platforms, performing additional saccades adds latency and power consumption. Here, we show that the number of saccades can be reduced while keeping the same recognition accuracy by performing intelligent saccadic movements, in a closed action-perception smart loop. We propose an algorithm for smart saccadic movement decisions that can reduce the number of necessary saccades to half, on average, for a predefined accuracy on the N-MNIST dataset. Additionally, we show that by replacing this control algorithm with an artificial neural network that learns to control the saccades, we can also reduce to half the average number of saccades needed for the N-MNIST recognition.

On Multiple AER Handshaking Channels over High-Speed Bit-Serial Bidirectional LVDS Links with Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems
A. Yousefzadeh, M. Jablonski, T. Iakymchuk, A. Linares-Barranco, A. Rosado, L.A. Plana, S. Temple, T. Serrano-Gotarredona, S.B. Furber and B. Linares-Barranco
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol 11, no. 5, pp 1133-1147, 2017
abstract      doi      pdf

Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.

Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links
A. Yousefzadeh, L.A. Plana, S. Temple, T. Serrano-Gotarredona, S.B. Furber and B. Linares-Barranco
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 8, pp 763-767, 2016
abstract      doi      pdf

Asynchronous handshaken interchip links are very popular among neuromorphic full-custom chips due to their delay-insensitive and high-speed properties. Of special interest are those links that minimize bit-line transitions for power saving, such as the two-phase handshaken non-return-to-zero (NRZ) 2-of-7 protocol used in the SpiNNaker chips. Interfacing such custom chip links to field-programmable gate arrays (FPGAs) is always of great interest, so that additional functionalities can be experimented and exploited for producing more versatile systems. Present-day commercial FPGAs operate typically in synchronous mode, thus making it necessary to incorporate synchronizers when interfacing with asynchronous chips. This introduces extra latencies and precludes pipelining, deteriorating transmission speed, particularly when sending multisymbols per unit communication packet. In this brief, we present a technique that learns to estimate the delay of a symbol transaction, thus allowing a fast pipelining from symbol to symbol. The technique has been tested on links between FPGAs and SpiNNaker chips, achieving the same throughput as fully asynchronous synchronizerless links between SpiNNaker chips. The links have been tested for periods of over one week without any transaction failure. Verilog codes of FPGA circuits are available as additional material for download.

Conferences


Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization
A. Yousefzadeh, S. Hosseini, P. Holanda, S. Leroux, T. Werner, T. Serrano-Gotarredona and B. Linares-Barranco, B. Dhoedt and P. Simoens
Conference · IEEE International Conference on Artificial Intelligence Circuits and Systems AICAS 2019
abstract     

Artificial Neural Networks (ANNs) show great performance in several data analysis tasks including visual and auditory applications. However, direct implementation of these algorithms without considering the sparsity of data requires high processing power, consume vast amounts of energy and suffer from scalability issues. Inspired by biology, one of the methods which can reduce power consumption and allow scalability in the implementation of neural networks is asynchronous processing and communication by means of action potentials, so-called spikes. In this work, we use the wellknown sigma-delta quantization method and introduce an easy and straightforward solution to convert an Artificial Neural Network to a Spiking Neural Network which can be implemented asynchronously in a neuromorphic platform. Briefly, we used asynchronous spikes to communicate the quantized output activations of the neurons. Despite the fact that our proposed mechanism is simple and applicable to a wide range of different ANNs, it outperforms the state-of-the-art implementations from the accuracy and energy consumption point of view. All source code for this project is available upon request for the academic purpose.

On the Hardware Efficiency of 1-bit Homeostatic Stochastic STDP
A. Yousefzadeh, E. Stromatias, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · Cognitive Computing Conference 2018
abstract     

Here we propose and demonstrate on FPGA hardware a homeostatic stochastic 1-bit weight STDP rule (whose 19 neurons have separate thresholds for integrating spikes and for triggering STDP update) used in a self-learning 20 feature extraction layer, which when combined with a rudimentary hebbian spiking classifier is capable of classifying with up to 100% accuracy a DVS recorded poker card symbol benchmark.

Hybrid Neural Network, an Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network
A. Yousefzadeh, G. Orchard, E. Stromatias, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract     

Interest in event-based vision sensors has proliferated in recent years, with innovative technology becoming more accessible to new researchers and highlighting such sensors' potential to enable low-latency sensing at low computational cost. These sensors can outperform frame-based vision sensors regarding data compression, dynamic range, temporal resolution and power efficiency. However, available mature frame-based processing methods by using Artificial Neural Networks (ANNs) surpass Spiking Neural Networks (SNNs) in terms of accuracy of recognition. In this paper, we introduce a Hybrid Neural Network which is an intermediate solution to exploit advantages of both event-based and frame-based processing. We have implemented this network in FPGA and benchmarked its performance by using different event-based versions of MNIST dataset. HDL codes for this project are available for academic purpose upon request.

Performance Comparison of Time-Step-Driven Versus Event-Driven Neural State Update Approaches in Spinnaker
M. Soto, A. Yousefzadeh, T. Serrano-Gotarredona, F. Galluppi, L. Plana, S. Furber and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2018
abstract     

The SpiNNaker chip is a multi-core processor optimized for neuromorphic applications. Many SpiNNaker chips are assembled to make a highly parallel million core platform. This system can be used for simulation of a large number of neurons in real-time. SpiNNaker is using a general purpose ARM processor that gives a high amount of flexibility to implement different methods for processing spikes. Various libraries and packages are provided to translate a high-level description of Spiking Neural Networks (SNN) to low-level machine language that can be used in the ARM processors. In this paper, we introduce and compare three different methods to implement this intermediate layer of abstraction. We have examined the advantages of each method by various criteria, which can be useful for professional users to choose between them. All the codes that are used in this paper are available for academic propose.

Passive localization and detection of quadcopter UAVs by using dynamic vision sensor
S. Hoseini, G. Orchard, A. Yousefzadeh, B. Deverakonda, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · Iranian Joint Congress on Fuzzy and Intelligent Systems, Conference on Fuzzy Systems and Conference on Intelligent Systems CFIS 2017
abstract     

We present a new passive and low power localization method for quadcopter UAVs (Unmanned aerial vehicles) by using dynamic vision sensors. This method works by detecting the speed of rotation of propellers that is normally higher than the speed of movement of other objects in the background. Dynamic vision sensors are fast and power efficient. We have presented the algorithm along with the results of implementation.

Live Demonstration: Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems
A. Yousefzadeh, M. Jabłoński, T. Iakymchuk, A. Linares-Barranco, A. Rosado, A. Plana, T. Serrano-Gotarredona, S. Furber and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
abstract     

We propose demonstration of a serial link for fast asynchronous communication in massively parallel platforms connected to DVS for real-time implementation of bio-inspired vision processing and spiking neural networks.

Live Demonstration: Hardware Implementation of Convolutional STDP for On-line Visual Feature Learning
A. Yousefzadeh, T Masquelier, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
abstract     

This is a proposal for live demonstration of a hardware that can learn visual feature online and in real-time during presentation of an object. Input Spikes are coming from a bio-inspired silicon retina or Dynamic Vision Sensor (DVS) and will be processed in a Spiking Convolutional Neural Network (SCNN) that is equipped with Synaptic Time Dependent Plasticity (STDP) learning rule and has been implemented in FPGA.

Hardware Implementation of Convolutional STDP for On-line Visual Feature Learning
A. Yousefzadeh, T Masquelier, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
abstract     

We present a highly hardware friendly STDP (Spike Timing Dependent Plasticity) learning rule for training Spiking Convolutional Cores in Unsupervised mode and training Fully Connected Classifiers in Supervised Mode. Examples are given for a 2-layer Spiking Neural System which learns in real time features from visual scenes obtained with spiking DVS (Dynamic Vision Sensor) Cameras.

Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems
A. Yousefzadeh, M. Jabłoński, T. Iakymchuk, A. Linares-Barranco, A. Rosado, A. Plana, T. Serrano-Gotarredona, S. Furber and B. Linares-Barranco
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
abstract     

Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging "neural spikes" among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical wires together with a pair of handshaking signals (Request and Acknowledge). Here we present a fully serial implementation using bidirectional SATA connectors with a pair of LVDS (low voltage differential signaling) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links per LVDS physical connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs reaching a maximum event transmission speed of 75Meps (Mega Events per second) for 32-bit events at 3.0Gbps line data rate.

Fast Pipeline 128×128 pixel spiking convolution core for event-driven vision processing in FPGAs
A. Yousefzadeh, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · International Conference on Event-Based Control, Communication and Signal Processing EBCCSP 2015
abstract     

This paper describes a digital implementation of a parallel and pipelined spiking convolutional neural network (S-ConvNet) core for processing spikes in an event-driven system. Event-driven vision systems use typically as sensor some bio-inspired spiking device, such as the popular Dynamic Vision Sensor (DVS). DVS cameras generate spikes related to changes in light intensity. In this paper we present a 2D convolution event-driven processing core with 128×128 pixels. S-ConvNet is an Event-Driven processing method to extract event features from an input event flow. The nature of spiking systems is highly parallel, in general. Therefore, S-ConvNet processors can benefit from the parallelism offered by Field Programmable Gate Arrays (FPGAs) to accelerate the operation. Using 3 stages of pipeline and a parallel structure, results in updating the state of a 128 neuron row in just 12ns. This improves with respect to previously reported approaches.

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