IMSE Publications

Found results matching for:

Author: Cristina Aledo González
Year: Since 2002

Journal Papers


Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder
A.J. Ginés, E. Peralías, C. Aledo and A. Rueda
Journal Paper · International Journal of Circuit Theory and Applications, vol. 47, no. 3, pp 333-349, 2019
abstract      doi      

This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

Conferences


Power Optimization and Stage Op-amp Linearity Relaxation in Pipeline ADCs with Digital Comparator Offset Calibration
A. Ginés, E. Peralias, C. Aledo and A. Rueda
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2014
abstract     

This paper presents a power optimization technique for Pipeline ADCs using digital background calibration of comparator offsets as an extra design variable. Thanks to calibration, comparator offset errors above half the stage least-significant bit (LSB) margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax the power consumption of stage amplifiers within the Pipeline queue, since output swing and driving capability are significantly lower. The proposal was validated using realistic hardware-behavioral models and transistor-level simulations. A 1.8V 15-bit 74dB-SNDR 100Msps Pipeline ADC was used as a demonstrator. Thanks to comparator calibration, the total power of stage subADCs was reduced by 75%, while a factor of 19% was found in stage amplifiers.

Mixed-Signal Techniques for Robust Auto-Tuning of Split-Tuned PLL Frequency Synthesizers
C. Aledo, A.J. Ginés, E. Peralías and A. Rueda
Conference · Conference on the Design of Circuits and Integrated Systems DCIS 2013
abstract     

This paper proposes two different phase-locked loop (PLL) auto-tuning techniques for low-cost sub-band selec-tion in split-tuned frequency synthesizers. The methods conti-nuously monitor the tuning voltage Vtune of the voltage-controlled oscillator (VCO) using two comparators whose threshold voltages define the PLL design region. Considering the comparators deci-sion, a simple digital control unit (DCU) generates a correction signal which assures Vtune is always within the allowable range, hence concurrently dealing with process, voltage and tempera-ture (PVT) variations. Two alternative algorithms depending on the DCU implementation have been proposed as trade-off between hardware complexity and convergence response. Both algorithms have been experimentally validated in a 1.2V PLL frequency synthesizer. This PLL block is part of a monolithical 2.4GHz IEEE 802.15.4 ZigBee transceiver implemented in a RF 90nm CMOS technology.

Books


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Book Chapters


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Other publications


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