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Author: Carranza González , Luis
Year: Since 2002
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Characterization, Screening and Qualification of the MEDA Wind-Sensor ASIC
S. Espejo, J. Ceballos, A. Ragel, L. Carranza, J.M. Mora, M.A. Lagos, J. Ramos, S. Sordo, E. Cordero and D. López
Conference - Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2018
[abstract]
The paper describes the final characterization results of the MEDA-WS ASIC, which was described in a previous paper in AMICSA-2016. It describes as well the qualification and the screening processes that have been carried out, and the present status of its integration and calibration in the final engineering and flying modules of the wind-sensor instrument.

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutierrez and M.A. Lagos-Florido
Journal Paper - IEEE Transactions on Nuclear Science, vol. 63, no. 4, pp. 2379-2389, 2016
IEEE    DOI: 10.1109/TNS.2016.2586140    ISSN: 0018-9499    » doi
[abstract]
This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35 μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.

A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz,A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Journal Paper - IEEE Transactions on Magnetics, vo. 51, no. 1, article 4001804, 2015
IEEE    DOI: 10.1109/TMAG.2014.2356976    ISSN: 0018-9464    » doi
[abstract]
This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D magnetometer for space applications, with a significant reduction in mass and volume while maintaining a high sensitivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances and a rad-hard mixed-signal ASIC designed in a standard 0.35 μm CMOS technology. The ASIC performs sensor-signal conditioning and analogue-to-digital conversion, and handles calibration tasks, system configuration, and communication with the outside. The proposed system provides high sensitivity to low magnetic fields, down to 3 nT, while offering a small and reliable solution under extreme environmental conditions in terms of radiation and temperature.

Four-channel self-compensating single-slope ADC for space environments
S. Sordo-Ibáñez, S. Espejo-Meana, B. Piñero-García, A. Ragel-Morales, J. Ceballos-Cáceres, M. Muñoz-Díaz, L. Carranza-González, A. Arias-Drake, J.M. Mora-Gutiérrez, M.A. Lagos-Florido and J. Ramos-Martos
Journal Paper - Electronics Letters, vol. 50, no.8, pp 579-581, 2014
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2014.0664    ISSN: 0013-5194    » doi
[abstract]
A multichannel high-resolution single-slope analogue-to-digital converter (SS ADC) is presented that automatically compensates for process, voltage and temperature variations, as well as for radiation effects, in order to be used in extreme environmental conditions. The design combines an efficient implementation by using a feedback loop that ensures an inherently monotonic and very accurate ramp generation, with high levels of configurability in terms of resolution and conversion rate, as well as input voltage range. The SS ADC was designed in a standard 0.35 μm CMOS technology. Experimental measurements of the performance and stability against radiation and temperature are presented to verify the proposed approach.

A Front-End ASIC for a 3-D Magnetometer for Space Applications Based on Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - European Conference on Magnetic Sensors and Actuators EMSA 2014
[abstract]
Abstract not avaliable

A Rad-Hard Multichannel Front-End Readout ASIC for Space Applications
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - IEEE International Workshop on Metrology for Aerospace METROAEROSPACE 2014
[abstract]
This paper presents a single-chip solution for sensor-signals conditioning and digitalization in space applications. The rad-hard ASIC implements a set of 6 generic instrumentation channels that are highly configurable in terms of resolution, conversion rate, and input voltage range, providing a flexible solution for space applications requiring the digital acquisition of slow input signals with medium-to-high resolutions. The resolution can be configured between 12 bits at 19.6 kS/s and 16 bits at 2.6 kS/s. The differential input voltage range can be extended up to 4 Vpp. The instrumentation channels combine a programmable-gain, high input impedance instrumentation amplifier and dual-slope analog-to-digital converters with radiation hardening by design (RHBD) techniques in a standard 0.35 μm CMOS technology. Experimental results demonstrate the performance of the ASIC across an operating temperature range of -90 ºC to +125 ºC and its robustness against radiation effects up to 318 krad of TID, absence of latch-up up to at least 81.8 MeV·cm2/mg, and a SEUs LETth of 22.5 MeV·cm2/mg.

SEE Characterization of a Magnetometer Front-End ASIC using a RHBD Digital Library in AMS 0.35μm CMOS
J. Ramos-Martos, A. Arias-Drake, L. Carranza-González, S. Sordo-Ibáñez, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, S. Espejo-Meana and M.A. Lagos-Florido
Conference - Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2014
[abstract]
A radiation-hardened-by-design (RHBD) digital library, developed for the Austria Microsystems (AMS) 0.35μm CMOS technology has been applied in a mixedsignal ASIC that operates as a multi-channel data acquisition system for magnetometers using anisotropic magnetoresistances (AMR). The circuit has been tested in the Heavy-Ion facilities of the Université Catholique de Louvain-la-Neuve (HIF-UCL). The experimental results demonstrate a LET threshold of 22.5 MeV·cm2/mg and absence of latchup up to 81.8 MeV·cm2/mg. This radiation-tolerant performance is obtained at the cost of a penalty in area and power with respect to the unhardened technology.

An Adaptive Approach to On-Chip CMOS Ramp Generation for High Resolution Single-Slope ADCs
S. Sordo-Ibanez, B. Piñero-García, S. Espejo-Meana, A. Ragel-Morales, J. Ceballos-Cáceres, M. Muñoz-Díaz, L. Carranza-González, A. Arias-Drake, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - European Conference on Circuit Theory and Design ECCTD 2013
[abstract]
Many image sensors employ column-parallel ADCs in their readout structures. Single-slope ADCs are ideally suited for these multi-channel applications due to their simplicity, low power and small overall area. The ramp generator, shared by all the converters in the readout architecture, is a key element that has a direct effect in the transfer characteristic of single-slope ADCs. Because a digital counter is inherently present in this conversion scheme, one common practice is to use a digital-to-analog converter driven by the counter to generate the ramp. Given the direct relationship between the DAC and the ADC transfer characteristics, one of the main issues is to ensure a sufficient linearity of the DAC, with special emphasis on its monotonicity. Very often, in particular when medium to high resolutions are aimed, this requires calibration of the DAC, which must be repeated every once in a while to account for temperature, process, power supply, and aging variations. This paper presents an inherently monotonic ramp generator with high levels of linearity and stability against any expected source of variations, combined with a very efficient realization and an inherent automatic adaptability to different resolutions. The ramp generator has been designed using radiation hardening by design (RHBD) techniques, allowing its use in space applications.

SEE Characterization of the AMS 0.35 μm CMOS Technology
J. Ramos-Martos, A. Arias-Drake, J.M. Mora-Gutiérrez, M. Muñoz-Díaz, A. Ragel-Morales, B. Piñero-García, J. Ceballos-Cáceres, L. Carranza-González, S. Sordo-Ibáñez, M.A. Lagos-Florido and S. Espejo-Meana
Conference - European Conference on Radiation and Its Effects on Components and Systems RADECS 2013
[abstract]
This work presents experimental results for the single-event effects characterization of a commercial (Austria Microsystems) 0.35 ΣΔm CMOS technology. It improves and expands previous results. The knowledge gained is being applied in the development of a RHBD digital library.

Design Methodology and Development of Mixed-Signal ASICs for Space Applications in Standard CMOS Technology
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2013
[abstract]
The design of mixed-signal ASICs for on-board space applications can provide several advantages that would not otherwise be possible with discrete components. However, extreme environmental conditions in terms of radiation and temperature imply a detailed knowledge of the technology used while CMOS commercial foundries do not usually have or make available these data. The aim of this work is to overcome these obstacles and offer solutions for space applications based on mixed-signal ASICs in commercial CMOS technologies. This paper presents the methodology followed for the assessment of a commercial (Austria Microsystems, AMS) 0.35 µm CMOS technology and for the development of a radiation hardened by design (RHBD) digital library. In addition, the described methodology has been applied to the development of two mixed-signal ASICs. The first chip performs the function of an optical digital transceiver for diffused-light intra-satellite optical communications. The second one implements a front-end solution for sensor data acquisition and signal conditioning and consists in a set of configurable multi-mode dual slope ADCs with resolution up to 16 bits.

A Front-End ASIC for a 16-Bit Three-Axis Magnetometer for Space Applications Based on Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - Conference on the Design of Circuits and Integrated Systems DCIS 2013
[abstract]
Many space applications require the measurement of magnetic fields. This includes many scientific and meteorological instruments, as well as satellite attitude control systems. The most widely used method for measuring magnetic fields in space missions has been the use of fluxgate sensors, mainly due to their reliability, robustness and relatively small mass and volume with respect to the total size of the satellite. However, the current trends of cost reduction and standardization in aerospace technology tends towards the design of small satellites, commonly called nano-satellites or even picosatellites, embodying a new challenge in the design of low-cost space instrumentation. In this scope, fluxgate sensors are massy and large enough so that their use is not addressable for these small satellites. This paper presents an alternative design of a three-axis magnetometer for the measurement of the strength and direction of an incident magnetic field in space applications, with a significant reduction in mass and volume while maintaining a high detectivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances (AMR) and a radiation hardened by design (RHBD) mixed-signal ASIC that performs signal conditioning and analog to digital conversion up to 16 bits, and also handles calibration tasks, system configuration and communication with the outside. The use of an ASIC instead of discrete components reduces both weight and volume, and achieves improvements in performance and consumption. The proposed magnetometer provides high sensitivy to low magnetic fields up to 30 μG of resolution while offering a small, low cost and reliable solution for space applications.

A focal plane processor for continuous-time 1-D optical correlation applications
G. Liñán-Cembrano, L. Carranza, B. Alexandre, A. Rodríguez-Vázquez, P. de la Fuente and T. Morlanes
Book Chapter - Focal-Plane Sensor-Processor Chips, pp 151-179, 2011
SPRINGER    DOI: 10.1007/978-1-4419-6475-5_7    ISBN: 978-1-4419-6474-8    » doi
[abstract]
This chapter describes a 1-D Focal Plane Processor, which has been designed to run continuous-time optical correlation applications. The chip contains 200 sensory processing elements, which acquire light patterns through a 2mm×10.9μm photodiode. The photogenerated current is scaled at the pixel level by five independent 3-bit programmable-gain current scaling blocks. The correlation patterns are defined as five sets of two hundred 3-bit numbers (from 0 to 7), which are provided to the chip through a standard I2C interface. Correlation outputs are provided in current form through 8-bit programmable gain amplifiers (PGA), whose configurations are also defined via I2C. The chip contains a mounting alignment help, which consists of three rows of 100 conventional active pixel sensors (APS) inserted at the top, middle and bottom part of the main photodiode array. The chip has been fabricated in a standard 0.35μm CMOS technology and its maximum power consumption is below 30mW. Experimental results demonstrate that the chip is able to process interference patterns moving at an equivalent frequency of 500kHz.

Diseño de microprocesadores de propósito específico y sistemas de desarrollo y testado para circuitos integrados de visión artificial
L. Carranza-González
Thesis - Date of defense: 21/10/2011
UNIVERSIDAD DE SEVILLA, IMSE-CNM    
[abstract]
Abstract not available

Focal-plane generation of multi-resolution and multi-scale image representation for low-power vision applications
J. Fernández-Berni, R. Carmona-Galán, L. Carranza-González, A. Zarandy and A. Rodríguez-Vázquez
Conference - SPIE Infrared Technology and Applications XXXVII, 2011
[abstract]
Early vision stages represent a considerably heavy computational load. A huge amount of data needs to be processed under strict timing and power requirements. Conventional architectures usually fail to adhere to the specifications in many application fields, especially when autonomous vision-enabled devices are to be implemented, like in lightweight UAVs, robotics or wireless sensor networks. A bioinspired architectural approach can be employed consisting of a hierarchical division of the processing chain, conveying the highest computational demand to the focal plane. There, distributed processing elements, concurrent with the photosensitive devices, influence the image capture and generate a pre-processed representation of the scene where only the information of interest for subsequent stages remains. These focal-plane operators are implemented by analog building blocks, which may individually be a little imprecise, but as a whole render the appropriate image processing very efficiently. As a proof of concept, we have developed a 176x144-pixel smart CMOS imager that delivers lighter but enriched representations of the scene. Each pixel of the array contains a photosensor and some switches and weighted paths allowing reconfigurable resolution and spatial filtering. An energy-based image representation is also supported. These functionalities greatly simplify the operation of the subsequent digital processor implementing the high level logic of the vision algorithm. The resulting figures, 5.6mW@30fps, permit the integration of the smart image sensor with a wireless interface module (Imote2 from Memsic Corp.) for the development of vision-enabled

FLIP-Q: a QCIF resolution focal-plane array for low-power image processing
J. Fernández-Berni, R. Carmona-Galán and L. Carranza-González
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 46,  no. 3, pp 669-680, 2011
IEEE    DOI: 10.1109/JSSC.2010.2102591    ISSN: 0018-9200    » doi
[abstract]
This paper reports a 176x144-pixel smart image sensor designed and fabricated in a 0.35 mu m CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power. The array is composed of pixel-level processing elements which carry out analog image processing concurrently with photosensing. These processing elements can be grouped into fully-programmable rectangular-shape areas by loading the appropriate interconnection patterns into the registers at the edge of the array. The targeted processing can be thus performed block-wise. Readout is done pixel-by-pixel in a random access fashion. On-chip 8b ADC is provided. The image processing primitives implemented by the chip, experimentally tested and fully functional, are scale space and Gaussian pyramid generation, fully-programmable multiresolution scene representation-including foveation-and block-wise energy-based scene representation. The power consumption associated to the capture, processing and A/D conversion of an image flow at 30 fps, with full-frame processing but reduced frame size output, ranges from 2.7 mW to 5.6 mW, depending on the operation to be performed.

On-site forest fire smoke detection by low-power autonomous vision sensor
J. Fernández-Berni, R. Carmona-Galán, L. Carranza-González, A. Cano-Rojas, J. F. Martínez-Carmona, A. Rodríguez-Vázquez and S. Morillas-Castillo
Conference - International Conference on Forest Fire Research ICFFR 2010
[abstract]
Early detection plays a crucial role to prevent forest fires from spreading. Wireless vision sensor networks deployed throughout high-risk areas can perform fine-grained surveillance and thereby very early detection and precise location of forest fires. One of the fundamental requirements that need to be met at the network nodes is reliable low-power on-site image processing. It greatly simplifies the communication infrastructure of the network as only alarm signals instead of complete images are transmitted, anticipating thus a very competitive cost. As a first approximation to fulfill such a requirement, this paper reports the results achieved from field tests carried out in collaboration with the Andalusian Fire-Fighting Service (INFOCA). Two controlled burns of forest debris were realized (www.youtube.com/user/vmoteProject). Smoke was successfully detected on-site by the EyeRISTM v1.2, a general-purpose autonomous vision system, built by AnaFocus Ltd., in which a vision algorithm was programmed. No false alarm was triggered despite the significant motion other than smoke present in the scene. Finally, as a further step, we describe the preliminary laboratory results obtained from a prototype vision chip which implements, at very low energy cost, some image processing primitives oriented to environmental monitoring.

A focal plane processor for continuous-time 1-D optical correlation applications
G. Liñán-Cembrano, L. Carranza, B. Alexandre, E. Roca and A. Rodríguez-Vázquez
Conference - European Conference on Circuit Theory and Design ECCTD 2009
[abstract]
This paper describes a 1-D Focal Plane Processor incorporating 200 pixels for Continuous-Time Optical Correlation Applications. Each pixel incorporates a 2mmx10.9mm photodiode whose current is scaled, at the pixel level, by 5 independent 3-bit programmable-gain current amplifiers. Correlation patterns, defined as 5 sets of 200 3-bits numbers, are communicated to the chip via . a standard (IC)-C-2 interface. Correlation outputs are provided in current form through independent 8-bit-programmable amplifiers whose gains are also defined via I2C. The chip contains an alignment help by incorporating 3 rows of 100 conventional Active Pixel Sensors (AI'S) inserted at the top, middle, and lower part of the main photodiode array. The chip has been fabricated in a standard 0.35mm CMOS technology and maximum power consumption is below 30mW.

A VLSI-oriented and power-efficient approach for dynamic texture recognition applied to smoke detection
J. Fernández-Berni, R. Carmona-Galán and L. Carranza-González
Conference - International Conference on Computer Vision Theory and Applications VISAPP 2009
[abstract]
The recognition of dynamic textures is fundamental in processing image sequences as they are very common in natural scenes. The computation of the optic flow is the most popular method to detect, segment and analyse dynamic textures. For weak dynamic textures, this method is specially adequate. However, for strong dynamic textures, it implies heavy computational load and therefore an important energy consumption. In this paper, we propose a novel approach intented to be implemented by very low-power integrated vision devices. It is based on a simple and flexible computation at the focal plane implemented by power-efficient hardware. The first stages of the processing are dedicated to remove redundant spatial information in order to obtain a simplified representation of the original scene. This simplified representation can be used by subsequent digital processing stages to finally decide about the presence and evolution of a certain dynamic texture in the scene. As an application of the proposed approach, we present the preliminary results of smoke detection for the development of a forest fire detection system based on a wireless vision sensor network.

Insect-vision inspired collision warning vision processor for automobiles
G. Liñán-Cembrano, L. Carranza, C. Rind, A. Zarandy, M. Soininen and A. Rodríguez-Vázquez
Journal Paper - IEEE Circuits and Systems Magazine, vol. 8, no. 2, pp 6-24, 2008
IEEE    DOI: 10.1109/MCAS.2008.916097    ISSN: 1531-636X    » doi
[abstract]
Vision is expected to play important roles for car safety enhancement. Imaging systems can be used to enlarging the vision field of the driver. For instance capturing and displaying views of hidden areas around the car which the driver can analyze for safer decision-making. Vision systems go a step further. They can autonomously analyze the visual information, identify dangerous situations and prompt the delivery of warning signals. For instance in case of road lane departure, if an overtaking car is in the blind spot, if an object is approaching within collision course, etc. Processing capabilities are also needed for applications viewing the car inteRíor such as "intelligent airbag systems" that base deployment decisions on passenger features. On-line processing of visual information for car safety involves multiple sensors and views, huge amount of data per view and large frame rates. The associated computational load may be prohibitive for conventional processing architectures. Dedicated systems with embedded local processing capabilities may be needed to confront the challenges. This paper describes a dedicated sensory-processing architecture for collision warning which is inspired by insect vision. Particularly, the paper relies on the exploitation of the knowledge about the behavior of Locusta Migratoria to develop dedicated chips and systems which are integrated into model cars as well as into a commercial car (Volvo XC90) and tested to deliver collision warnings in real traffic scenaríos.

A vision-based monitoring system for very early automatic detection of forest fires
J. Fernández-Berni, R. Carmona-Galán and L. Carranza-González
Conference - International Conference on Modelling, Monitoring and Management of Forest Fires, 2008
DOI:     » doi
[abstract]
This paper describes a system capable of detecting smoke at the very beginning of a forest fire with a precise spatial resolution. The system is based on a wireless vision sensor network. Each sensor monitors a small area of vegetation by running on-site a tailored vision algorithm to detect the presence of smoke. This algorithm examines chromaticity changes and spatio-temporal patterns in the scene that are characteristic of the smoke dynamics at early stages of propagation. Processing takes place at the sensor nodes and, if that is the case, an alarm signal is transmitted through the network along with a reference to the location of the triggered zone - without requiring complex GIS systems. This method improves the spatial resolution on the surveilled area and reduces the rate of false alarms. An energy efficient implementation of the sensor/processor devices is crucial as it determines the autonomy of the network nodes. At this point, we have developed an ad hoc vision algorithm, adapted to the nature of the problem, to be integrated into a single-chip sensor/processor. As a first step to validate the feasibility of the system, we applied the algorithm to smoke sequences recorded with commercial cameras at real-world scenaRíos that simulate the working conditions of the network nodes. The results obtained point to a very high reliability and robustness in the detection process.

Locust-Inspired Vision System On Chip Architecture for Collision Detection in Automotive Applications
L. Carranza-González, R. Laviana-Gonzalez, S. Vargas-Sierra, J. Cuadri-Carvajo, G. Liñan-Cembrano and E. Roca-Moreno
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2006
[abstract]
Abstract not available

Locust-inspired vision system on chip architecture for collision detection in automotive applications
L. Carranza, R. Laviana, S. Vargas, J. Cuadri, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Conference - International Symposium on Circuits and Systems ISCAS 2006
[abstract]
This paper describes a programmable digital computing architecture dedicated to process information in accordance to the organization and operating principles of the four-layer neuron structure encountered at the visual system of Locusts. This architecture takes advantage of the natural collision detection skills of locusts and is capable of processing images and ascertaining collision threats in real-time automotive scenaRíos. In addition to the Locust features, the architecture embeds a Topological Feature Estimator module to identify and classify objects in collision course.

Vehículo-Robot para aplicaciones de Control y Visión Artificial
L. Carranza-González, E. Roca-Moreno and A. Rodríguez-Vázquez
Conference - V Jornadas de Computación Reconfigurable y Aplicaciones CEDI 2005
[abstract]
Este trabajo presenta el diseño del vehículo-robot LRC-1, ideado para aplicaciones de control y visión en tiempo real. El LRC-1 está compuesto por sistemas electrónicos y mecánicos. Los sistemas electrónicos se han basado en un microcontrolador, circuitería de control, adquisición de datos y cómputo sintetizada en lógica reconfigurable, un subsistema de comunicaciones bidireccional de radiofrecuencia, una cámara de vídeo y un transmisor de microondas. Las aplicaciones del robot son generales y actualmente se está usando como plataforma para el desarrollo de un SoC sensor-procesador para automoción. Con esa finalidad, en fase de descripción HDL se encuentran una unidad de detección temprana de colisiones inspirada en el sistema de visión del insecto langosta (Locusta migratoria) y un clasificador topológico-estadístico de objetos que en breve estarán sintetizados en lógica reconfigurable formando parte del LRC-1, junto con un sensor de imágenes CMOS de gran rango dinámico diseñado en el IMSE-CNM. Por otra parte, el sistema mecánico está compuesto por un motor eléctrico, un sistema de tracción diferencial y servomecanismos. El robot puede operar básicamente en tres modos: control manual, control automático gobernado por un ordenador y modo autónomo.

ACE16k based stand-alone system for real-time pre-processing tasks
L. Carranza, F. Jiménez Garrido, G. Liñán-Cembrano, E. Roca, S. Espejo-Meana and A. Rodríguez-Vázquez
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.

A bioinspired vision chip architecture for collision detection in automotive applications
R. Laviana, L. Carranza, S. Vargas, G. Liñán and E. Roca
Conference - Conference on Bioengineered and Bioinspired Systems II, 2005
[abstract]
This paper describes the architecture and retino-topic unit of a bio-inspired vision chip intended for automotive applications. The chip contains an array of 100 x 150 sensors which are able to capture high dynamic range (HDR) images, with a programmable compressive characteristic. The chip also incorporates a mechanism for adaptation of the global exposition time to the average illumination conditions. Average values are evaluated over image areas which are programmable by the user. In addition to the HDR pixel, every retino-topic unit in the array incorporates digital memory for three 6-bit pixel values (18-bits), as required for the implementation of a bionspired computing model for collisions detection which has been developed in the framework of a multidisciplinary European research project. All processing steps are executed off-chip, though we are currently working in the design of tiny digital processors (one per column) which will allow for running the whole model on-chip in a future version of this prototype. The chip has been designed in a 0.3 5 mu m 2P-4M technology and maintains its correct operation in extreme temperature conditions (from -40 degrees C to 110 degrees C).

ACE16k-Ds: un Sistema autónomo programable para el preprocesamiento de imágenes en tiempo real
L. Carranza-González, F.J. Jimenez-Garrido, G. Liñán-Cembrano, E. Roca-Moreno, S. Espejo-Meana and A. Rodríguez-Vázquez
Conference - Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2004
[abstract]
Este artículo describe un sistema electrónico autónomo y programable, denominado ACE16k-DS, que permite sensar y procesar imágenes en tiempo real. La arquitectura del sistema está basada en el chip ACE16k y en la FPGA Xc4028xl de Xilinx en la que se han sintetizado una Unidad de Control Programable de propósito específico y un generador de vídeo digital. Las imágenes son sensadas y procesadas, en modo analógico, en el chip ACE16k, siguiendo instrucciones secuenciadas por la Unidad de Control Programable. El generador de vídeo digital permite visualizar, en una pantalla TFT, las imágenes procesadas en tiempo real.

CMOS mixed-signal flexible vision chips
G. Liñán-Cembrano, L. Carranza-González, S. Espejo-Meana, R. Domínguez-Castro and A. Rodríguez-Vázquez
Book Chapter - Smart Adaptive Systems on Silicon, pp 103-118, 2004
SPRINGER    DOI: 10.1007/978-1-4020-2782-6_7    ISBN: 978-1-4757-1051-9    » doi
[abstract]
Today, with 0.18μm technologies fully mature for mixed-signal design, CMOS compatible optical sensors available, and with 0.09μm knocking at the door of designers, we have the pieces to confront the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last years towards the realization of Vision Systems on Chips. Such VSoCs are targeted to integrate in a semiconductor substrate the functions of sensing, image processing in space and time, high-level processing and control of actuators. Based on newest discoveries of neurobiologists about the behavior of mammalian retinas, a new generation of flexible mixed-signal vision chips has been created which feature better Speed vs. Power figures than DSP-based systems. These devices are true mixed-signal microprocessors including standard digital I/O, embedded image and program memories. This chapter presents some concepts related to the architectures, circuits and methodologies associated to the design of these chips. Due to space limitations, and for the sake of illustrating different topics related to the design of such a kind of vision chips we will concentrate on the series of ACE devices developed by our group since 1996, referring the interested reader to some of the references at the end of the chapter.

ACE16k: The third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs
A. Rodríguez-Vázquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro and S. Espejo-Meana
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 851-863, 2004
IEEE    DOI: 10.1109/TCSI.2004.827621    ISSN: 1057-7122    » doi
[abstract]
Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm(2) and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3 x 3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.

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