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Research Units » Design and Test of Mixed-Signal Integrated Circuits » Circuit Design using Emerging Devices and Non-Conventional Logic Concepts

Circuit Design using Emerging Devices and Non-Conventional Logic Concepts


José M. Quintana Toledo


María J. Avedillo de Juan


Keywords: emerging devices; non-conventional logic; energy efficiency; low power; resonant tunel diode (RTD); negative differential resistance (NDR); tunel transistor (TFET); steep subthreshold slope devices; memristor; monostable-to-bistable operating principle (MOBILE); nanopipelining; threshold logic

a) Programable MOS-NDR exhibiting negative differential resistance; b) Experimental results of a two-phase single-gate-per phase MOBILE pipeline.
Main research objective is the development, analysis and design of circuits using emerging devices and/or nonconventional logic models, with emphasis on applications with severe constraints on power or energy like IoT. In particular, we explore circuits based on resonant tunel diodes (RTDs), tunel transistors (TFETs and SymFETs), transistors integrating phase transition devices and memristors. The distinguishing features of these devices is exploited to obtain circuits competitive with respect to their CMOS counterparts in terms of speed, power, energy or area or exhibiting better trade-offs among those criteria. From the logic point of view, we study threshold logic as an alternative to conventional Boolean logic. At the architectural level, we focus the development of memory free gate-level pipelines (nanopileline) suitable in high performance applicattions.
Main recent activities in this line include:
  • Design and evaluation of logic circuits using TFETs and HyperFETs for low power and energy efficient applications. Technology benchmarlking and identification of application areas, development of gate topologies and logic architectures suitable for the specific characteristics of these devices.
  • Design and evaluation of memristor based circuits
  • Development of logic gates working on the basis of the Mostable to bistable opetaing principle (MOBILE) enable by the negative differential resistance of RTDs and SymFETs. Implementation of MOBILE threshold gates, muti-threshold gates and generalized threshold gates.
  • Development of nano-pipelined architectures based on MOBILE.
Evaluation in terms of energy and speed of CMOS transistors (MOSFETs and FinFETs) and tunel transistors (PSUHETE and NDHETE1). Different logic-deths and switching activities are explored
Research Highlights
J. Nuñez and M.J. Avedillo, "Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications", IEEE Journal of the Electron Devices Society, vol. 5, no. 6, pp. 530-534, 2017 » doi
M.J. Avedillo and J. Nuñez, "Insights into the Operation of Hyper-FET-Based Circuits", IEEE Transactions on Electron Devices, vol. 64, no. 9, pp 3912-3918, 2017 » doi
J. Núñez and M.J. Avedillo, "Comparison of TFETs and CMOS Using Optimal Design Points for Power–Speed Tradeoffs", IEEE Transactions on Nanotechnology, vol. 16, no. 1, pp. 83-89, Jan 2017 » doi
J. Núñez and M.J. Avedillo, "Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Applications Areas", IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 5012-5020, 2016 » doi
M.J. Avedillo and J. Nuñez, "Improving speed of tunnel FETs logic circuits," IET Electronics Letters, vol. 51, no. 21, pp. 1702-1704, Oct 2015 » doi
Key Research Projects & Contracts
PULPOSS: Circuitos y arquitecturas con dispositivos Steep Slope para aplicaciones de muy bajo consumo de potencia (TEC2017-)
PI: María José Avedillo de Juan / José María Quintana Toledo
Funding Body: Min. de Economía y Competitividad
Jan 2018 - Dec 2020
NACLUDE: Nano-architectures for logic computing using emergent devices (TEC2013-40670-P)
PI: Jose María Quintana Toledo / María J. Avedillo de Juan
Funding Body: Min. de Economía y Competitividad
Jan 2014 - Dec 2017
RTDs: Architectures and circuits for logic and non-linear applications using RTDs (TEC2010-18937)
PI: María J. Avedillo de Juan
Funding Body: Min. de Ciencia e Innovación
Jan 2011 - Dec 2014
QUDOS: Quantum Tunneling Device Technology on Silicon (IST-2001-32358)
PI: Werner Prost / WP Coordinator: José M. Quintana Toledo
Funding Body: Comisión Europea
Jan 2002 - Dec 2004
NDR: Diseño e implementación de circuitos nano-microelectrónicos usando dispositivos con característica NDR (TEC2007-67245/MIC)
PI: María J. Avedillo de Juan
Funding Body: Min. de Educación y Ciencia
Oct 2007 - Dec 2010