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Research Units » Micro/Nanometric Circuits and Systems » Modeling, Design and Synthesis Techniques of Analog, Mixed-Signal, RF and Heterogeneous Circuits and Systems

Modeling, Design and Synthesis Techniques of Analog, Mixed-Signal, RF and Heterogeneous Circuits and Systems

Contact:

Francisco V. Fernández Fernández

pacovimse-cnmcsices

Keywords: systematic design methodologies; single-objective and multi-objective optimization; reconfigurable design; layout-aware design; variability-aware design; unreliability effects

Description
The general objective of this research line is to develop new modeling, design and synthesis strategies for analog, mixed-signal, radio-frequency (RF) and heterogeneous integrated circuits and systems, aiming at better performances, smaller design and fabrication cost and smaller power consumption. This also involves dealing with the increasing variability of modern technologies.
More specifically, the work include activities in different aspects of the circuit design flow, as well as their exploitation in industrial-class designs:
  • Behavioral modeling and simulation methods supporting different kinds of hierarchical design flows.
  • Layout-aware synthesis methodologies for analog/RF circuits, given the importance of early inclusion of physical design effects in the design flow.
  • Systematic reconfigurable circuit design for optimum use of area and power in multi-mode circuits and systems.
  • Electromagnetic simulation-based performance modeling of passive devices, providing the best trade-offs among performances and cost for RF circuit design.
  • Characterization and modeling of time-zero and time-dependent variability effects in micro/nano-electronic devices.
  • Variability-aware design techniques.
  • Exploitation of physical unreliability effects in microelectronic devices, e.g., in security applications.
  • Development and exploitation of emerging design methodologies aimed at better performance-cost trade-offs: bottom-up techniques, hybrid techniques, competitive strategies.
  • Design tools that implement the design methodologies and techniques developed by the group: SIDe-O, TARS and CASE.
Design Tool developed in the group: SIDe-O Toolbox
Design Tool developed in the group: CASE
Research Highlights
B. Liu, Q. Zhang, F.V. Fernandez and G. Gielen, "An efficient evolutionary algorithm for chance-constrained bi-objective stochastic optimization and its application to manufacturing engineering", IEEE Trans. on Evolutionary Computation, vol. 17, no. 6, pp. 786-796, 2013 » doi
R. Castro-Lopez, O. Guerra, E. Roca and F.V. Fernandez, "An Integrated Layout-Synthesis Approach for Analog ICs", IEEE Trans. on Computer-Aided Design, vol. 27, no. 7, pp. 1179-1189, 2008 » doi
R. Gonzalez-Echevarria, R. Castro-Lopez, E. Roca, F.V. Fernandez, J. Sieiro, N. Vidal and J.M. López-Villegas, "Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1269-1273, 2014 » doi
A. Toro-Frías, P. Martín-Lloret, J. Martin-Martinez, R. Castro-López, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernández, "Reliability simulation for analog ICs: Goals, solutions, and challenges," Integration, the VLSI Journal, vol. 55, pp. 341-348, 2016 » doi
R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, J. Sieiro, J.M. López-Villegas and N. Vidal, "An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, pp. 15-26, 2017 » doi
Key Research Projects & Contracts
AMADEUS:  Analog Modeling and Design Using a Symbolic Environment (ESPRIT IV 21821)
IP: Francisco V. Fernández Fernández
1996 - 2000
PLATFORM4G: Desarrollo de una plataforma de diseño de sistemas adaptables para sistemas de telecomunicaciones de cuarta generación (TIC 2532)
PI: Francisco V. Fernández Fernández
Funding Body: Junta de Andalucía
Jan 2008 - Dec 2012
MARAGDA: Multilevel approach to the reliability-aware design of analog and digital integrated circuits (TEC2013-45638-C3-3-R) » web
PI: Francisco V. Fernández Fernández
Funding Body: Min. de Economía y Competitividad
Jan 2014 - Dec 2016
KIT-LTCC: Design Kit Development in LTCC ceramic technology: modeling, simulation and fabrication of components and circuits, and design methodology (RTC-2014-2426-7)
PI: Elisenda Roca
Funding Body: Min. de Economía y Competitividad
Sep 2014 - Jan 2017
TOGETHER: Towards Trusted Low-Power Things: Devices, Circuits and Architectures (TEC2016-75151-C3-3-R)
Funding Body: Min. de Economía, Industria y Competitividad
PI: Francisco V. Fernández Fernández / Rafael Castro López
Dec 2016 - Dec 2019